diff options
author | Miod Vallat <miod@cvs.openbsd.org> | 2008-08-18 23:07:27 +0000 |
---|---|---|
committer | Miod Vallat <miod@cvs.openbsd.org> | 2008-08-18 23:07:27 +0000 |
commit | 884436909ca85671f0d985d9435e4f29aa8adeec (patch) | |
tree | a286c76db2a54d37987b6046353ddb45af54a2ba /sys/arch/vax | |
parent | 0b443839c20c0d6d8b1e9a1f91f71816a69fe853 (diff) |
Move common CVAX defines and code (internal cache IPR, SSC layout, machine
check frame format...) to a single place. Get rid of duplicated KAxx_FOO
constants.
Diffstat (limited to 'sys/arch/vax')
-rw-r--r-- | sys/arch/vax/conf/files.vax | 3 | ||||
-rw-r--r-- | sys/arch/vax/include/cvax.h | 129 | ||||
-rw-r--r-- | sys/arch/vax/include/ka420.h | 10 | ||||
-rw-r--r-- | sys/arch/vax/include/ka650.h | 66 | ||||
-rw-r--r-- | sys/arch/vax/vax/cvax.c | 107 | ||||
-rw-r--r-- | sys/arch/vax/vax/ka410.c | 6 | ||||
-rw-r--r-- | sys/arch/vax/vax/ka650.c | 73 |
7 files changed, 263 insertions, 131 deletions
diff --git a/sys/arch/vax/conf/files.vax b/sys/arch/vax/conf/files.vax index 5524e546c7d..11ae4b2987d 100644 --- a/sys/arch/vax/conf/files.vax +++ b/sys/arch/vax/conf/files.vax @@ -1,4 +1,4 @@ -# $OpenBSD: files.vax,v 1.46 2008/08/18 23:04:26 miod Exp $ +# $OpenBSD: files.vax,v 1.47 2008/08/18 23:07:22 miod Exp $ # $NetBSD: files.vax,v 1.60 1999/08/27 20:04:32 ragge Exp $ # # new style config file for vax architecture @@ -369,6 +369,7 @@ file arch/vax/vax/ka660.c vax660 file arch/vax/vax/ka670.c vax670 file arch/vax/vax/ka680.c vax680 file arch/vax/vax/vxt.c vxt +file arch/vax/vax/cvax.c vax60 | vax650 file arch/vax/vax/scb.c file arch/vax/vax/conf.c file arch/vax/vax/urem.s diff --git a/sys/arch/vax/include/cvax.h b/sys/arch/vax/include/cvax.h new file mode 100644 index 00000000000..5137b598cd4 --- /dev/null +++ b/sys/arch/vax/include/cvax.h @@ -0,0 +1,129 @@ +/* $OpenBSD: cvax.h,v 1.1 2008/08/18 23:07:24 miod Exp $ */ +/* $NetBSD: ka650.h,v 1.6 1997/07/26 10:12:43 ragge Exp $ */ +/* + * Copyright (c) 1988 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Mt. Xinu. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ka650.h 7.5 (Berkeley) 6/28/90 + */ + +/* + * + * Definitions specific to CVAX processors. + */ + +/* + * CADR: Cache Disable Register (IPR 37) + */ +#define CADR_STMASK 0x000000f0 /* 1st level cache state mask */ +#define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */ +#define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */ +#define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */ +#define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */ + +/* + * Internal State Info 2: (for mcheck recovery) + */ +#define IS2_VCR 0x00008000 /* VAX Can't Restart flag */ + +#ifndef _LOCORE + +/* + * System Support Chip (SSC) registers + */ +struct cvax_ssc { + u_long ssc_sscbr; /* SSC Base Addr Register */ + u_long pad1[3]; + u_long ssc_ssccr; /* SSC Configuration Register */ + u_long pad2[3]; + u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */ + u_long pad3[18]; + u_long ssc_todr; /* TOY Clock Register */ + u_long pad4[36]; + u_long ssc_tcr0; /* timer control reg 0 */ + u_long ssc_tir0; /* timer interval reg 0 */ + u_long ssc_tnir0; /* timer next interval reg 0 */ + u_long ssc_tivr0; /* timer interrupt vector reg 0 */ + u_long ssc_tcr1; /* timer control reg 1 */ + u_long ssc_tir1; /* timer interval reg 1 */ + u_long ssc_tnir1; /* timer next interval reg 1 */ + u_long ssc_tivr1; /* timer interrupt vector reg 1 */ + u_long pad5[184]; + u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */ + u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */ + u_char ssc_keyboard; /* Keyboard code */ +}; +#define CVAX_SSC 0x20140000 + +extern struct cvax_ssc *cvax_ssc_ptr; + +/* + * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr) + */ +#define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */ +#define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */ + +/* + * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01]) + * (The rest of the bits are the same as in the standard VAX + * Interval timer and are defined in clock.h) + */ +#define TCR_STP 0x00000004 /* Stop after time-out */ + +/* + * Flags for Console Program Mail Box + */ +#define CPMB_CVAX_HALTACT 0x03 /* Field for halt action */ +#define CPMB_CVAX_RESTART 0x01 /* Restart */ +#define CPMB_CVAX_REBOOT 0x02 /* Reboot */ +#define CPMB_CVAX_HALT 0x03 /* Halt */ +#define CPMB_CVAX_BIP 0x04 /* Bootstrap in progress */ +#define CPMB_CVAX_RIP 0x08 /* Restart in progress */ +#define CPMB_CVAX_DOTHIS 0x30 /* Execute sommand */ +#define CPMB_CVAX_LANG 0xf0 /* Language field */ + +/* + * Machine Check frame + */ +struct cvax_mchk_frame { + int cvax_bcnt; /* byte count == 0xc */ + int cvax_summary; /* summary parameter */ + int cvax_mrvaddr; /* most recent vad */ + int cvax_istate1; /* internal state */ + int cvax_istate2; /* internal state */ + int cvax_pc; /* trapped pc */ + int cvax_psl; /* trapped psl */ +}; + +const char *cvax_mchk_descr(int); +void cvax_halt(void); +void cvax_reboot(int); + +#endif /* _LOCORE */ diff --git a/sys/arch/vax/include/ka420.h b/sys/arch/vax/include/ka420.h index 8c771914324..b7c4e4536cc 100644 --- a/sys/arch/vax/include/ka420.h +++ b/sys/arch/vax/include/ka420.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ka420.h,v 1.4 2006/07/25 21:11:08 miod Exp $ */ +/* $OpenBSD: ka420.h,v 1.5 2008/08/18 23:07:24 miod Exp $ */ /* $NetBSD: ka420.h,v 1.2 1998/06/07 18:34:09 ragge Exp $ */ /* * Copyright (c) 1996 Ludd, University of Lule}, Sweden. @@ -138,14 +138,6 @@ #define KA420_CFG_CURTEST 0x10 /* Cursor Test (monochrom) */ #define KA420_CFG_VIDOPT 0x08 /* Video option present */ -/* Primary cache bits (CADR, IPR 37) */ -#define KA420_CADR_S2E 0x80 /* set 2 enable */ -#define KA420_CADR_S1E 0x40 /* set 1 enable */ -#define KA420_CADR_ISE 0x20 /* insn caching enable */ -#define KA420_CADR_DSE 0x10 /* data caching enable */ -#define KA420_CADR_WWP 0x02 /* write wrong parity */ -#define KA420_CADR_DIA 0x01 /* diagnostic mode */ - /* Secondary cache bits (CACR, 20084000) */ #define KA420_CACR_CP3 0x80000000 /* last parity read */ #define KA420_CACR_CP2 0x40000000 /* last parity read */ diff --git a/sys/arch/vax/include/ka650.h b/sys/arch/vax/include/ka650.h index 512bb8bee01..f941a5298cf 100644 --- a/sys/arch/vax/include/ka650.h +++ b/sys/arch/vax/include/ka650.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ka650.h,v 1.10 2003/06/02 23:27:57 millert Exp $ */ +/* $OpenBSD: ka650.h,v 1.11 2008/08/18 23:07:24 miod Exp $ */ /* $NetBSD: ka650.h,v 1.6 1997/07/26 10:12:43 ragge Exp $ */ /* * Copyright (c) 1988 The Regents of the University of California. @@ -49,20 +49,6 @@ #define CAER_TAG 0x00000001 /* tag parity in 1st level cache */ /* - * CADR: Cache Disable Register (IPR 37) - */ -#define CADR_STMASK 0x000000f0 /* 1st level cache state mask */ -#define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */ -#define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */ -#define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */ -#define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */ - -/* - * Internal State Info 2: (for mcheck recovery) - */ -#define IS2_VCR 0x00008000 /* VAX Can't Restart flag */ - -/* * DMA System Error Register (merr_dser) */ #define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */ @@ -146,56 +132,6 @@ struct ka650_cbd { #define CACR_CPE 0x00000020 /* Cache Parity Error */ /* - * System Support Chip (SSC) registers - */ -struct ka650_ssc { - u_long ssc_sscbr; /* SSC Base Addr Register */ - u_long pad1[3]; - u_long ssc_ssccr; /* SSC Configuration Register */ - u_long pad2[3]; - u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */ - u_long pad3[55]; - u_long ssc_tcr0; /* timer control reg 0 */ - u_long ssc_tir0; /* timer interval reg 0 */ - u_long ssc_tnir0; /* timer next interval reg 0 */ - u_long ssc_tivr0; /* timer interrupt vector reg 0 */ - u_long ssc_tcr1; /* timer control reg 1 */ - u_long ssc_tir1; /* timer interval reg 1 */ - u_long ssc_tnir1; /* timer next interval reg 1 */ - u_long ssc_tivr1; /* timer interrupt vector reg 1 */ - u_long pad4[184]; - u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */ - u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */ - u_char ssc_keyboard; /* Keyboard code */ -}; -#define KA650_SSC 0x20140000 - -/* - * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr) - */ -#define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */ -#define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */ - -/* - * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01]) - * (The rest of the bits are the same as in the standard VAX - * Interval timer and are defined in clock.h) - */ -#define TCR_STP 0x00000004 /* Stop after time-out */ - -/* - * Flags for Console Program Mail Box - */ -#define CPMB650_HALTACT 0x03 /* Field for halt action */ -#define CPMB650_RESTART 0x01 /* Restart */ -#define CPMB650_REBOOT 0x02 /* Reboot */ -#define CPMB650_HALT 0x03 /* Halt */ -#define CPMB650_BIP 0x04 /* Bootstrap in progress */ -#define CPMB650_RIP 0x08 /* Restart in progress */ -#define CPMB650_DOTHIS 0x30 /* Execute sommand */ -#define CPMB650_LANG 0xf0 /* Language field */ - -/* * Inter Processor Communication Register * To determine if memory error was from QBUS device DMA (as opposed to cpu). */ diff --git a/sys/arch/vax/vax/cvax.c b/sys/arch/vax/vax/cvax.c new file mode 100644 index 00000000000..805b42baebe --- /dev/null +++ b/sys/arch/vax/vax/cvax.c @@ -0,0 +1,107 @@ +/* $OpenBSD: cvax.c,v 1.1 2008/08/18 23:07:26 miod Exp $ */ +/* $NetBSD: ka650.c,v 1.25 2001/04/27 15:02:37 ragge Exp $ */ +/* + * Copyright (c) 1988 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Mt. Xinu. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ka650.c 7.7 (Berkeley) 12/16/90 + */ + +/* + * CVAX-specific code. + */ + +#include <sys/param.h> +#include <sys/time.h> +#include <sys/kernel.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <uvm/uvm_extern.h> + +#include <machine/cvax.h> +#include <machine/clock.h> +#include <machine/cpu.h> +#include <machine/psl.h> +#include <machine/mtpr.h> +#include <machine/sid.h> + +struct cvax_ssc *cvax_ssc_ptr; + +/* + * Machine Check descriptions + */ +const char *cvax_mcheck[] = { + NULL, /* 00 */ + "FPA proto err", /* 01 */ + "FPA resv inst", /* 02 */ + "FPA Ill Stat 2", /* 03 */ + "FPA Ill Stat 1", /* 04 */ + "PTE in P0, TB miss", /* 05 */ + "PTE in P1, TB miss", /* 06 */ + "PTE in P0, Mod", /* 07 */ + "PTE in P1, Mod", /* 08 */ + "Illegal intr IPL", /* 09 */ + "MOVC state error", /* 0a */ + + "bus read error", /* 80 */ + "SCB read error", /* 81 */ + "bus write error", /* 82 */ + "PCB write error" /* 83 */ +}; + +const char * +cvax_mchk_descr(int summary) +{ + if ((unsigned int)summary < 11) + return cvax_mcheck[summary]; + + if (summary >= 0x80 && summary <= 0x83) + return cvax_mcheck[summary - 0x80 + 11]; + + return NULL; +} + +/* + * CVAX Mailbox routines + */ + +void +cvax_halt() +{ + cvax_ssc_ptr->ssc_cpmbx = CPMB_CVAX_DOTHIS | CPMB_CVAX_HALT; + asm("halt"); +} + +void +cvax_reboot(arg) + int arg; +{ + cvax_ssc_ptr->ssc_cpmbx = CPMB_CVAX_DOTHIS | CPMB_CVAX_REBOOT; +} diff --git a/sys/arch/vax/vax/ka410.c b/sys/arch/vax/vax/ka410.c index 657b3e747a9..b4075d467c1 100644 --- a/sys/arch/vax/vax/ka410.c +++ b/sys/arch/vax/vax/ka410.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ka410.c,v 1.10 2008/08/18 23:05:38 miod Exp $ */ +/* $OpenBSD: ka410.c,v 1.11 2008/08/18 23:07:26 miod Exp $ */ /* $NetBSD: ka410.c,v 1.21 1999/09/06 19:52:53 ragge Exp $ */ /* * Copyright (c) 1996 Ludd, University of Lule}, Sweden. @@ -50,6 +50,7 @@ #include <machine/uvax.h> #include <machine/ka410.h> #include <machine/ka420.h> +#include <machine/cvax.h> #include <machine/clock.h> #include <machine/vsbus.h> @@ -102,8 +103,7 @@ ka410_conf() ka410_cpu->vc_vdcorg = 0; /* XXX */ ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ; printf("cpu: Enabling primary cache, "); - mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE, - PR_CADR); + mtpr(CADR_SEN2 | CADR_SEN1 | CADR_CENI | CADR_CEND, PR_CADR); if (vax_confdata & KA420_CFG_CACHPR) { l2cache = (void *)vax_map_physmem(KA420_CH2_BASE, (KA420_CH2_SIZE / VAX_NBPG)); diff --git a/sys/arch/vax/vax/ka650.c b/sys/arch/vax/vax/ka650.c index 851e9f33127..988e17e9564 100644 --- a/sys/arch/vax/vax/ka650.c +++ b/sys/arch/vax/vax/ka650.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ka650.c,v 1.17 2008/08/18 23:05:38 miod Exp $ */ +/* $OpenBSD: ka650.c,v 1.18 2008/08/18 23:07:26 miod Exp $ */ /* $NetBSD: ka650.c,v 1.25 2001/04/27 15:02:37 ragge Exp $ */ /* * Copyright (c) 1988 The Regents of the University of California. @@ -45,16 +45,17 @@ #include <sys/device.h> #include <uvm/uvm_extern.h> +#include <machine/cvax.h> #include <machine/ka650.h> #include <machine/clock.h> #include <machine/cpu.h> #include <machine/psl.h> #include <machine/mtpr.h> #include <machine/sid.h> +#include <machine/nexus.h> struct ka650_merr *ka650merr_ptr; struct ka650_cbd *ka650cbd_ptr; -struct ka650_ssc *ka650ssc_ptr; struct ka650_ipcr *ka650ipcr_ptr; int *KA650_CACHE_ptr; @@ -62,8 +63,6 @@ int *KA650_CACHE_ptr; #define CACHEON 1 static void ka650setcache(int); -static void ka650_halt(void); -static void ka650_reboot(int); static void uvaxIII_conf(void); static void uvaxIII_memerr(void); static int uvaxIII_mchk(caddr_t); @@ -77,8 +76,8 @@ struct cpu_dep ka650_calls = { generic_clkwrite, 4, /* ~VUPS */ 2, /* SCB pages */ - ka650_halt, - ka650_reboot, + cvax_halt, + cvax_reboot, NULL, NULL, hardclock @@ -99,7 +98,7 @@ uvaxIII_conf() */ ka650merr_ptr = (void *)vax_map_physmem(KA650_MERR, 1); ka650cbd_ptr = (void *)vax_map_physmem(KA650_CBD, 1); - ka650ssc_ptr = (void *)vax_map_physmem(KA650_SSC, 3); + cvax_ssc_ptr = (void *)vax_map_physmem(CVAX_SSC, 3); ka650ipcr_ptr = (void *)vax_map_physmem(KA650_IPCR, 1); KA650_CACHE_ptr = (void *)vax_map_physmem(KA650_CACHE, (KA650_CACHESIZE/VAX_NBPG)); @@ -155,45 +154,27 @@ uvaxIII_memerr() #endif } -#define NMC650 15 -char *mc650[] = { - 0, "FPA proto err", "FPA resv inst", - "FPA Ill Stat 2", "FPA Ill Stat 1", "PTE in P0, TB miss", - "PTE in P1, TB miss", "PTE in P0, Mod", "PTE in P1, Mod", - "Illegal intr IPL", "MOVC state error", "bus read error", - "SCB read error", "bus write error", "PCB write error" -}; u_int cache1tag; u_int cache1data; u_int cdalerr; u_int cache2tag; -struct mc650frame { - int mc65_bcnt; /* byte count == 0xc */ - int mc65_summary; /* summary parameter */ - int mc65_mrvaddr; /* most recent vad */ - int mc65_istate1; /* internal state */ - int mc65_istate2; /* internal state */ - int mc65_pc; /* trapped pc */ - int mc65_psl; /* trapped psl */ -}; - int uvaxIII_mchk(cmcf) caddr_t cmcf; { - register struct mc650frame *mcf = (struct mc650frame *)cmcf; - register u_int type = mcf->mc65_summary; - register u_int i; + struct cvax_mchk_frame *mcf = (struct cvax_mchk_frame *)cmcf; + u_int type = mcf->cvax_summary; + const char *descr; + u_int i; printf("machine check %x", type); - if (type >= 0x80 && type <= 0x83) - type -= 0x80 - 11; - if (type < NMC650 && mc650[type]) - printf(": %s", mc650[type]); + descr = cvax_mchk_descr(type); + if (descr != NULL) + printf(": %s", descr); printf("\n\tvap %x istate1 %x istate2 %x pc %x psl %x\n", - mcf->mc65_mrvaddr, mcf->mc65_istate1, mcf->mc65_istate2, - mcf->mc65_pc, mcf->mc65_psl); + mcf->cvax_mrvaddr, mcf->cvax_istate1, mcf->cvax_istate2, + mcf->cvax_pc, mcf->cvax_psl); printf("dmaser=0x%b qbear=0x%x dmaear=0x%x\n", ka650merr_ptr->merr_dser, DMASER_BITS, (int)ka650merr_ptr->merr_qbear, @@ -231,14 +212,14 @@ uvaxIII_mchk(cmcf) * only if FPD is set in the saved PSL, or bit VCR in Istate2 * is clear. */ - if ((type > 0 && type < 5) || type == 11 || type == 12) { - if ((mcf->mc65_psl & PSL_FPD) - || !(mcf->mc65_istate2 & IS2_VCR)) { + if ((type > 0 && type < 5) || type == 0x80 || type == 0x81) { + if ((mcf->cvax_psl & PSL_FPD) + || !(mcf->cvax_istate2 & IS2_VCR)) { uvaxIII_memerr(); - return 0; + return MCHK_RECOVERED; } } - return -1; + return MCHK_PANIC; } /* @@ -273,17 +254,3 @@ ka650setcache(int state) } } } - -static void -ka650_halt() -{ - ka650ssc_ptr->ssc_cpmbx = CPMB650_DOTHIS | CPMB650_HALT; - asm("halt"); -} - -static void -ka650_reboot(arg) - int arg; -{ - ka650ssc_ptr->ssc_cpmbx = CPMB650_DOTHIS | CPMB650_REBOOT; -} |