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authorMark Kettenis <kettenis@cvs.openbsd.org>2018-05-14 09:33:21 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2018-05-14 09:33:21 +0000
commit13eb08ddc301d491c6a62453606f2953a8dd8960 (patch)
treecf9fa4700aec1e47b314e168551f8a431c9ec1cf /sys/arch
parent34d89714ef390dfb54fee4b16eb100d6f1b25534 (diff)
Expose memory barriers to userland.
ok visa@, mpi@
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/hppa/include/atomic.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/sys/arch/hppa/include/atomic.h b/sys/arch/hppa/include/atomic.h
index e255611d0e8..54889a670aa 100644
--- a/sys/arch/hppa/include/atomic.h
+++ b/sys/arch/hppa/include/atomic.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: atomic.h,v 1.10 2016/02/09 06:46:02 dlg Exp $ */
+/* $OpenBSD: atomic.h,v 1.11 2018/05/14 09:33:20 kettenis Exp $ */
/* Public Domain */
@@ -242,6 +242,8 @@ atomic_clearbits_long(volatile unsigned long *uip, unsigned long v)
atomic_leave(eiem);
}
+#endif /* defined(_KERNEL) */
+
/*
* Although the PA-RISC 2.0 architecture allows an implementation to
* be weakly ordered, all PA-RISC processers to date implement a
@@ -261,5 +263,4 @@ __insn_barrier(void)
#define membar_consumer() __insn_barrier()
#define membar_sync() __insn_barrier()
-#endif /* defined(_KERNEL) */
#endif /* _MACHINE_ATOMIC_H_ */