diff options
| author | Patrick Wildt <patrick@cvs.openbsd.org> | 2017-02-17 19:14:59 +0000 |
|---|---|---|
| committer | Patrick Wildt <patrick@cvs.openbsd.org> | 2017-02-17 19:14:59 +0000 |
| commit | 2f8b48b0c535e9921061758b5242152585482117 (patch) | |
| tree | 18c0239b3e998541c6cd1338ee838de952760e62 /sys/arch | |
| parent | 3155769ea33b4b14c776c4543e6d9c7b7a63a6ec (diff) | |
Use a proper memory attribute for write-through instead of reusing
the nocache attribute.
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/arm64/arm64/locore.S | 9 | ||||
| -rw-r--r-- | sys/arch/arm64/arm64/pmap.c | 6 | ||||
| -rw-r--r-- | sys/arch/arm64/include/pte.h | 3 |
3 files changed, 11 insertions, 7 deletions
diff --git a/sys/arch/arm64/arm64/locore.S b/sys/arch/arm64/arm64/locore.S index 304017790b3..b472afc4b4b 100644 --- a/sys/arch/arm64/arm64/locore.S +++ b/sys/arch/arm64/arm64/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.14 2017/02/08 09:18:24 patrick Exp $ */ +/* $OpenBSD: locore.S,v 1.15 2017/02/17 19:14:58 patrick Exp $ */ /*- * Copyright (c) 2012-2014 Andrew Turner * All rights reserved. @@ -624,8 +624,11 @@ switch_mmu_kernel: .align 3 mair: - /* Device Normal, no cache Normal, write-back */ - .quad MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2) + /* Device | Normal (no cache, write-back, write-through) */ + .quad MAIR_ATTR(0x00, 0) | \ + MAIR_ATTR(0x44, 1) | \ + MAIR_ATTR(0xff, 2) | \ + MAIR_ATTR(0x88, 3) tcr: .quad (TCR_T1SZ(64 - VIRT_BITS) | TCR_T0SZ(64 - 48) | \ TCR_ASID_16 | TCR_TG1_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS) diff --git a/sys/arch/arm64/arm64/pmap.c b/sys/arch/arm64/arm64/pmap.c index d9b9c18c1ce..fca3dabdb9c 100644 --- a/sys/arch/arm64/arm64/pmap.c +++ b/sys/arch/arm64/arm64/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.21 2017/02/17 09:59:28 jsg Exp $ */ +/* $OpenBSD: pmap.c,v 1.22 2017/02/17 19:14:58 patrick Exp $ */ /* * Copyright (c) 2008-2009,2014-2016 Dale Rahn <drahn@dalerahn.com> * @@ -1647,8 +1647,8 @@ pmap_pte_update(struct pte_desc *pted, uint64_t *pl3) attr |= ATTR_IDX(PTE_ATTR_WB); // inner and outer writeback attr |= ATTR_SH(SH_INNER); break; - case PMAP_CACHE_WT: /* for the momemnt treating this as uncached */ - attr |= ATTR_IDX(PTE_ATTR_CI); // inner and outer uncached + case PMAP_CACHE_WT: + attr |= ATTR_IDX(PTE_ATTR_WT); // inner and outer writethrough attr |= ATTR_SH(SH_INNER); break; case PMAP_CACHE_CI: diff --git a/sys/arch/arm64/include/pte.h b/sys/arch/arm64/include/pte.h index 78bb2588eb2..7aeffb4ec9a 100644 --- a/sys/arch/arm64/include/pte.h +++ b/sys/arch/arm64/include/pte.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pte.h,v 1.2 2017/02/03 09:47:26 patrick Exp $ */ +/* $OpenBSD: pte.h,v 1.3 2017/02/17 19:14:58 patrick Exp $ */ /* * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com> * @@ -56,6 +56,7 @@ #define PTE_ATTR_DEV 0 #define PTE_ATTR_CI 1 #define PTE_ATTR_WB 2 +#define PTE_ATTR_WT 3 #define SH_INNER 3 |