Small steps towards getting the serial clock correct on IOC4 serial ports.

3 files changed, 50 insertions, 7 deletions

diff --git a/sys/arch/sgi/dev/com_iof.c b/sys/arch/sgi/dev/com_iof.c
index 66e61bfc47a..73dc9638400 100644
--- a/sys/arch/sgi/dev/com_iof.c
+++ b/sys/arch/sgi/dev/com_iof.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: com_iof.c,v 1.1 2009/08/18 19:34:15 miod Exp $	*/
+/*	$OpenBSD: com_iof.c,v 1.2 2009/10/07 04:17:46 miod Exp $	*/
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -87,7 +87,10 @@ com_iof_attach(struct device *parent, struct device *self, void *aux)
 
 	sc->sc_hwflags = 0;
 	sc->sc_swflags = 0;
-	sc->sc_frequency = 22000000 / 3;
+	/* XXX need to get PCI bus speed from parent */
+	sc->sc_frequency = 66666667;
+	if (0)
+		sc->sc_frequency >>= 1;
 
 	/* if it's in use as console, it's there. */
 	if (!(console && !comconsattached)) {
@@ -107,6 +110,7 @@ com_iof_attach(struct device *parent, struct device *self, void *aux)
 		 */
 		sc->sc_iot = comconsiot;
 		sc->sc_iobase = comconsaddr;
+		sc->sc_frequency = comconsfreq;
 
 		if (comcnattach(sc->sc_iot, sc->sc_iobase, TTYDEF_SPEED,
 		    sc->sc_frequency, (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8))
diff --git a/sys/arch/sgi/sgi/ip27_machdep.c b/sys/arch/sgi/sgi/ip27_machdep.c
index c8859142a75..e10fa1df3c8 100644
--- a/sys/arch/sgi/sgi/ip27_machdep.c
+++ b/sys/arch/sgi/sgi/ip27_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip27_machdep.c,v 1.19 2009/08/18 19:31:56 miod Exp $	*/
+/*	$OpenBSD: ip27_machdep.c,v 1.20 2009/10/07 04:17:48 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -80,6 +80,7 @@ ip27_setup()
 {
 	size_t gsz;
 	uint node;
+	uint32_t ctrl;
 	nmi_t *nmi;
 
 	uncached_base = PHYS_TO_XKPHYS_UNCACHED(0, SP_NC);
@@ -139,16 +140,51 @@ ip27_setup()
 
 	/*
 	 * Initialize the early console parameters.
-	 * This assumes IOC3 is accessible through a widget small window.
+	 * This assumes it is either on IOC3 or IOC4, accessible through
+	 * a widget small window.
+	 *
+	 * Since IOC3 and IOC4 use different clocks, we need to tell them
+	 * apart early. We rely on the serial port offset within the IOC
+	 * space.
 	 */
 
-	xbow_build_bus_space(&sys_config.console_io, 0, 8 /* whatever */);
+	xbow_build_bus_space(&sys_config.console_io, 0,
+	    8 /* whatever nonzero */);
 	/* Constrain to the correct window */
 	sys_config.console_io.bus_base =
 	    kl_get_console_base() & 0xffffffffff000000UL;
 
 	comconsaddr = kl_get_console_base() & 0x0000000000ffffffUL;
-	comconsfreq = 22000000 / 3;
+	if ((comconsaddr & 0xfff) < 0x380) {
+		/* IOC3 */
+		comconsfreq = 22000000 / 3;
+		bios_printf("IOC3 style console\n");
+	} else {
+		/* IOC4 */
+		/*
+		 * IOC4 clocks are derived from the PCI clock, so we need to
+		 * figure out whether this is an 66MHz or a 33MHz bus.
+		 * Note that this assumes the IOC4 is connected to a Bridge
+		 * or PIC widget, and that even if this is a PIC widget,
+		 * the common widget register space can be correctly read
+		 * with non-doubleword aligned word reads.
+		 */
+		comconsfreq = 66666667;
+		bios_printf("IOC4 style console\n");
+		ctrl = *(volatile uint32_t *)
+		    ((sys_config.console_io.bus_base + WIDGET_CONTROL) | 4);
+		switch (ctrl & BRIDGE_WIDGET_CONTROL_SPEED_MASK) {
+		default:
+			bios_printf("WARNING! UNRECOGNIZED IOC4 SPEED\n"
+			    "ASSUMING 66MHZ\n");
+			break;
+		case BRIDGE_WIDGET_CONTROL_SPEED_66MHZ:
+			break;
+		case BRIDGE_WIDGET_CONTROL_SPEED_33MHZ:
+			comconsfreq >>= 1;
+			break;
+		}
+	}
 	comconsiot = &sys_config.console_io;
 
 	/*
diff --git a/sys/arch/sgi/xbow/xbridgereg.h b/sys/arch/sgi/xbow/xbridgereg.h
index 7039f126a64..997738ef877 100644
--- a/sys/arch/sgi/xbow/xbridgereg.h
+++ b/sys/arch/sgi/xbow/xbridgereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xbridgereg.h,v 1.8 2009/08/18 19:31:59 miod Exp $	*/
+/*	$OpenBSD: xbridgereg.h,v 1.9 2009/10/07 04:17:48 miod Exp $	*/
 
 /*
  * Copyright (c) 2008 Miodrag Vallat.
@@ -37,6 +37,9 @@
 #define	BRIDGE_WIDGET_CONTROL_IO_SWAP		0x00800000
 #define	BRIDGE_WIDGET_CONTROL_MEM_SWAP		0x00400000
 #define	BRIDGE_WIDGET_CONTROL_LARGE_PAGES	0x00200000
+#define	BRIDGE_WIDGET_CONTROL_SPEED_MASK	0x00000030
+#define	BRIDGE_WIDGET_CONTROL_SPEED_33MHZ	0x00000000
+#define	BRIDGE_WIDGET_CONTROL_SPEED_66MHZ	0x00000010
 
 /*
  * DMA Direct Window