Sigh! The sun4v TTEs have a different layout than sun4u TTEs. Rename the

existing sun4u defines and add sun4v.  For now, decide which set to use
at compile time.  Change the sun4u-specific code in locore.s to use the sun4u
defines.

3 files changed, 143 insertions, 63 deletions

diff --git a/sys/arch/sparc64/include/pte.h b/sys/arch/sparc64/include/pte.h
index cd5a30efbf0..5389bfd01c1 100644
--- a/sys/arch/sparc64/include/pte.h
+++ b/sys/arch/sparc64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.8 2007/10/17 19:25:22 kettenis Exp $	*/
+/*	$OpenBSD: pte.h,v 1.9 2008/03/23 21:49:48 kettenis Exp $	*/
 /*	$NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */
 
 /*
@@ -152,46 +152,133 @@ void smp_tlb_flush_ctx(int);
 #define	PGSZ_512K		2
 #define	PGSZ_4M			3
 
-#define	PGSZ_SHIFT		61
-#define	TLB_SZ(s)		(((uint64_t)(s))<<PGSZ_SHIFT)
+#define	SUN4U_PGSZ_SHIFT	61
+#define	SUN4U_TLB_SZ(s)		(((uint64_t)(s)) << SUN4U_PGSZ_SHIFT)
 
 /* TLB data masks */
-#define TLB_V			0x8000000000000000LL
-#define TLB_8K			TLB_SZ(PGSZ_8K)
-#define TLB_64K			TLB_SZ(PGSZ_64K)
-#define TLB_512K		TLB_SZ(PGSZ_512K)
-#define TLB_4M			TLB_SZ(PGSZ_4M)
-#define TLB_SZ_MASK		0x6000000000000000LL
-#define TLB_NFO			0x1000000000000000LL
-#define TLB_IE			0x0800000000000000LL
-#define TLB_SOFT2_MASK		0x07fc000000000000LL
-#define TLB_RESERVED_MASK	0x0003f80000000000LL
-#define TLB_PA_MASK		0x000007ffffffe000LL
-#define TLB_SOFT_MASK		0x0000000000001f80LL
+#define SUN4U_TLB_V		0x8000000000000000LL
+#define SUN4U_TLB_8K		SUN4U_TLB_SZ(PGSZ_8K)
+#define SUN4U_TLB_64K		SUN4U_TLB_SZ(PGSZ_64K)
+#define SUN4U_TLB_512K		SUN4U_TLB_SZ(PGSZ_512K)
+#define SUN4U_TLB_4M		SUN4U_TLB_SZ(PGSZ_4M)
+#define SUN4U_TLB_SZ_MASK	0x6000000000000000LL
+#define SUN4U_TLB_NFO		0x1000000000000000LL
+#define SUN4U_TLB_IE		0x0800000000000000LL
+#define SUN4U_TLB_SOFT2_MASK	0x07fc000000000000LL
+#define SUN4U_TLB_RESERVED_MASK	0x0003f80000000000LL
+#define SUN4U_TLB_PA_MASK	0x000007ffffffe000LL
+#define SUN4U_TLB_SOFT_MASK	0x0000000000001f80LL
 /* S/W bits */
-/* Access & TSB locked bits are swapped so I can set access w/one insn */
-/* #define TLB_ACCESS		0x0000000000001000LL */
-#define TLB_ACCESS		0x0000000000000200LL
-#define TLB_MODIFY		0x0000000000000800LL
-#define TLB_REAL_W		0x0000000000000400LL
-/* #define TLB_TSB_LOCK		0x0000000000000200LL */
-#define TLB_TSB_LOCK		0x0000000000001000LL
-#define TLB_EXEC		0x0000000000000100LL
-#define TLB_EXEC_ONLY		0x0000000000000080LL
+#define SUN4U_TLB_ACCESS	0x0000000000000200LL
+#define SUN4U_TLB_MODIFY	0x0000000000000800LL
+#define SUN4U_TLB_REAL_W	0x0000000000000400LL
+#define SUN4U_TLB_TSB_LOCK	0x0000000000001000LL
+#define SUN4U_TLB_EXEC		0x0000000000000100LL
+#define SUN4U_TLB_EXEC_ONLY	0x0000000000000080LL
 /* H/W bits */
-#define TLB_L			0x0000000000000040LL
-#define TLB_CACHE_MASK		0x0000000000000030LL
-#define TLB_CP			0x0000000000000020LL
-#define TLB_CV			0x0000000000000010LL
-#define TLB_E			0x0000000000000008LL
-#define TLB_P			0x0000000000000004LL
-#define TLB_W			0x0000000000000002LL
-#define TLB_G			0x0000000000000001LL
-
-#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
-(((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\
-((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\
-((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL))
+#define SUN4U_TLB_L		0x0000000000000040LL
+#define SUN4U_TLB_CACHE_MASK	0x0000000000000030LL
+#define SUN4U_TLB_CP		0x0000000000000020LL
+#define SUN4U_TLB_CV		0x0000000000000010LL
+#define SUN4U_TLB_E		0x0000000000000008LL
+#define SUN4U_TLB_P		0x0000000000000004LL
+#define SUN4U_TLB_W		0x0000000000000002LL
+#define SUN4U_TLB_G		0x0000000000000001LL
+
+#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
+(((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|\
+(((u_int64_t)(pa))&SUN4U_TLB_PA_MASK)|\
+((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):SUN4U_TLB_E)|\
+((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|\
+((ie)?SUN4U_TLB_IE:0LL))
+
+#define SUN4V_PGSZ_SHIFT	0
+#define	SUN4V_TLB_SZ(s)		(((uint64_t)(s))<<SUN4V_PGSZ_SHIFT)
+
+/* TLB data masks */
+#define SUN4V_TLB_V		0x8000000000000000LL
+#define SUN4V_TLB_8K		SUN4V_TLB_SZ(PGSZ_8K)
+#define SUN4V_TLB_64K		SUN4V_TLB_SZ(PGSZ_64K)
+#define SUN4V_TLB_512K		SUN4V_TLB_SZ(PGSZ_512K)
+#define SUN4V_TLB_4M		SUN4V_TLB_SZ(PGSZ_4M)
+#define SUN4V_TLB_SZ_MASK	0x000000000000000fLL
+#define SUN4V_TLB_NFO		0x4000000000000000LL
+#define SUN4V_TLB_IE		0x0000000000001000LL
+#define SUN4V_TLB_SOFT2_MASK	0x3f00000000000000LL
+#define SUN4V_TLB_PA_MASK	0x00ffffffffffe000LL
+#define SUN4V_TLB_SOFT_MASK	0x0000000000000030LL
+/* S/W bits */
+#define SUN4V_TLB_ACCESS	0x0000000000000010LL
+#define SUN4V_TLB_MODIFY	0x0000000000000020LL
+#define SUN4V_TLB_REAL_W	0x2000000000000000LL
+#define SUN4V_TLB_TSB_LOCK	0x1000000000000000LL
+#define SUN4V_TLB_EXEC		SUN4V_TLB_X
+#define SUN4V_TLB_EXEC_ONLY	0x0200000000000000LL
+/* H/W bits */
+#define SUN4V_TLB_CACHE_MASK	0x0000000000000600LL
+#define SUN4V_TLB_CP		0x0000000000000400LL
+#define SUN4V_TLB_CV		0x0000000000000200LL
+#define SUN4V_TLB_E		0x0000000000000800LL
+#define SUN4V_TLB_P		0x0000000000000100LL
+#define SUN4V_TLB_X		0x0000000000000080LL
+#define SUN4V_TLB_W		0x0000000000000040LL
+#define SUN4V_TLB_G		0x0000000000000000LL
+
+#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
+(((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\
+(((u_int64_t)(pa))&SUN4V_TLB_PA_MASK)|\
+((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):SUN4V_TLB_E)|\
+((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\
+((ie)?SUN4V_TLB_IE:0LL))
+
+#ifdef SUN4V
+#define TLB_SZ		SUN4V_TLB_SZ
+
+#define TLB_V		SUN4V_TLB_V
+#define TLB_NFO		SUN4V_TLB_NFO
+#define TLB_IE		SUN4V_TLB_IE
+#define TLB_PA_MASK	SUN4V_TLB_PA_MASK
+#define TLB_ACCESS	SUN4V_TLB_ACCESS
+#define TLB_MODIFY	SUN4V_TLB_MODIFY
+#define TLB_REAL_W	SUN4V_TLB_REAL_W
+#define TLB_TSB_LOCK	SUN4V_TLB_TSB_LOCK
+#define TLB_EXEC	SUN4V_TLB_EXEC
+#define TLB_EXEC_ONLY	SUN4V_TLB_EXEC_ONLY
+#define TLB_L		0ULL
+#define TLB_CACHE_MASK	SUN4V_TLB_CACHE_MASK
+#define TLB_CP		SUN4V_TLB_CP
+#define TLB_CV		SUN4V_TLB_CV
+#define TLB_E		SUN4V_TLB_E
+#define TLB_P		SUN4V_TLB_P
+#define TLB_W		SUN4V_TLB_W
+#define TLB_G		SUN4V_TLB_G
+
+#define TSB_DATA	SUN4V_TSB_DATA
+#else
+#define TLB_SZ		SUN4U_TLB_SZ
+
+#define TLB_V		SUN4U_TLB_V
+#define TLB_NFO		SUN4U_TLB_NFO
+#define TLB_IE		SUN4U_TLB_IE
+#define TLB_PA_MASK	SUN4U_TLB_PA_MASK
+#define TLB_ACCESS	SUN4U_TLB_ACCESS
+#define TLB_MODIFY	SUN4U_TLB_MODIFY
+#define TLB_REAL_W	SUN4U_TLB_REAL_W
+#define TLB_TSB_LOCK	SUN4U_TLB_TSB_LOCK
+#define TLB_EXEC	SUN4U_TLB_EXEC
+#define TLB_EXEC_ONLY	SUN4U_TLB_EXEC_ONLY
+#define TLB_L		SUN4U_TLB_L
+#define TLB_CACHE_MASK	SUN4U_TLB_CACHE_MASK
+#define TLB_CP		SUN4U_TLB_CP
+#define TLB_CV		SUN4U_TLB_CV
+#define TLB_E		SUN4U_TLB_E
+#define TLB_P		SUN4U_TLB_P
+#define TLB_W		SUN4U_TLB_W
+#define TLB_G		SUN4U_TLB_G
+
+#define TSB_DATA	SUN4U_TSB_DATA
+#endif
+
 
 #define MMU_CACHE_VIRT	0x3
 #define MMU_CACHE_PHYS	0x2
diff --git a/sys/arch/sparc64/sparc64/genassym.cf b/sys/arch/sparc64/sparc64/genassym.cf
index ec7e419cdb7..64eca8fa4a4 100644
--- a/sys/arch/sparc64/sparc64/genassym.cf
+++ b/sys/arch/sparc64/sparc64/genassym.cf
@@ -1,4 +1,4 @@
-#	$OpenBSD: genassym.cf,v 1.28 2008/03/22 21:10:29 kettenis Exp $
+#	$OpenBSD: genassym.cf,v 1.29 2008/03/23 21:49:48 kettenis Exp $
 #	$NetBSD: genassym.cf,v 1.23 2001/08/08 00:09:30 eeh Exp $
 
 #
@@ -265,20 +265,11 @@ member	dbr_local
 member	dbr_in
 endif
 
-export	TLB_ACCESS
-export	TLB_MODIFY
-export	TLB_REAL_W
-export	TLB_TSB_LOCK
-export	TLB_EXEC
-export	TLB_EXEC_ONLY
-export	TLB_L
-export	TLB_CACHE_MASK
-export	TLB_CP
-export	TLB_CV
-export	TLB_E
-export	TLB_P
-export	TLB_W
-export	TLB_G
+export	SUN4U_TLB_ACCESS
+export	SUN4U_TLB_MODIFY
+export	SUN4U_TLB_REAL_W
+export	SUN4U_TLB_EXEC
+export	SUN4U_TLB_W
 
 struct	mutex
 member	mtx_wantipl
diff --git a/sys/arch/sparc64/sparc64/locore.s b/sys/arch/sparc64/sparc64/locore.s
index cba2246ff49..070fe349299 100644
--- a/sys/arch/sparc64/sparc64/locore.s
+++ b/sys/arch/sparc64/sparc64/locore.s
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.s,v 1.125 2008/03/23 12:03:50 miod Exp $	*/
+/*	$OpenBSD: locore.s,v 1.126 2008/03/23 21:49:48 kettenis Exp $	*/
 /*	$NetBSD: locore.s,v 1.137 2001/08/13 06:10:10 jdolecek Exp $	*/
 
 /*
@@ -1463,9 +1463,10 @@ dmmu_write_fault:
 1:
 	ldxa	[%g6] ASI_PHYS_CACHED, %g4
 	brgez,pn %g4, winfix				! Entry invalid?  Punt
-	 or	%g4, TLB_MODIFY|TLB_ACCESS|TLB_W, %g7	! Update the modified bit
+	 or	%g4, SUN4U_TLB_MODIFY|SUN4U_TLB_ACCESS|SUN4U_TLB_W, %g7
+		! Update the modified bit
 	
-	btst	TLB_REAL_W|TLB_W, %g4			! Is it a ref fault?
+	btst	SUN4U_TLB_REAL_W|SUN4U_TLB_W, %g4	! Is it a ref fault?
 	bz,pn	%xcc, winfix				! No -- really fault
 #ifdef DEBUG
 	/* Make sure we don't try to replace a kernel translation */
@@ -1491,7 +1492,8 @@ dmmu_write_fault:
 	membar	#StoreLoad
 	cmp	%g4, %g7
 	bne,pn	%xcc, 1b
-	 or	%g4, TLB_MODIFY|TLB_ACCESS|TLB_W, %g4	! Update the modified bit
+	 or	%g4, SUN4U_TLB_MODIFY|SUN4U_TLB_ACCESS|SUN4U_TLB_W, %g4
+		! Update the modified bit
 	stx	%g1, [%g2]				! Update TSB entry tag
 	mov	SFSR, %g7
 	stx	%g4, [%g2+8]				! Update TSB entry data
@@ -1590,15 +1592,15 @@ data_miss:
 1:
 	ldxa	[%g6] ASI_PHYS_CACHED, %g4
 	brgez,pn %g4, data_nfo				! Entry invalid?  Punt
-	 or	%g4, TLB_ACCESS, %g7			! Update the access bit
+	 or	%g4, SUN4U_TLB_ACCESS, %g7		! Update the access bit
 	
-	btst	TLB_ACCESS, %g4				! Need to update access git?
+	btst	SUN4U_TLB_ACCESS, %g4			! Need to update access git?
 	bne,pt	%xcc, 1f
 	 nop
 	casxa	[%g6] ASI_PHYS_CACHED, %g4, %g7		!  and write it out
 	cmp	%g4, %g7
 	bne,pn	%xcc, 1b
-	 or	%g4, TLB_ACCESS, %g4				! Update the modified bit
+	 or	%g4, SUN4U_TLB_ACCESS, %g4		! Update the modified bit
 1:	
 	stx	%g1, [%g2]				! Update TSB entry tag
 	
@@ -2304,19 +2306,19 @@ instr_miss:
 	 nop
 
 	/* Check if it's an executable mapping. */
-	andcc	%g4, TLB_EXEC, %g0
+	andcc	%g4, SUN4U_TLB_EXEC, %g0
 	bz,pn	%xcc, textfault
 	 nop
 
 
-	or	%g4, TLB_ACCESS, %g7			! Update accessed bit
-	btst	TLB_ACCESS, %g4				! Need to update access bit?
+	or	%g4, SUN4U_TLB_ACCESS, %g7		! Update accessed bit
+	btst	SUN4U_TLB_ACCESS, %g4			! Need to update access bit?
 	bne,pt	%xcc, 1f
 	 nop
 	casxa	[%g6] ASI_PHYS_CACHED, %g4, %g7		!  and store it
 	cmp	%g4, %g7
 	bne,pn	%xcc, 1b
-	 or	%g4, TLB_ACCESS, %g4			! Update accessed bit
+	 or	%g4, SUN4U_TLB_ACCESS, %g4		! Update accessed bit
 1:	
 	stx	%g1, [%g2]				! Update TSB entry tag
 	stx	%g4, [%g2+8]				! Update TSB entry data