Pieces of arm11 and armv7 support for newer cpus. This is work in progress

and not complete.

18 files changed, 1296 insertions, 71 deletions

diff --git a/sys/arch/arm/arm/bus_space_asm_generic.S b/sys/arch/arm/arm/bus_space_asm_generic.S
index 80817e5008b..b96ca4ac2ae 100644
--- a/sys/arch/arm/arm/bus_space_asm_generic.S
+++ b/sys/arch/arm/arm/bus_space_asm_generic.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bus_space_asm_generic.S,v 1.1 2004/02/01 05:09:48 drahn Exp $	*/
+/*	$OpenBSD: bus_space_asm_generic.S,v 1.2 2009/05/08 02:57:31 drahn Exp $	*/
 /*	$NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $	*/
 
 /*
@@ -50,7 +50,7 @@ ENTRY(generic_bs_r_1)
 	ldrb	r0, [r1, r2]
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_r_2)
 	ldrh	r0, [r1, r2]
 	mov	pc, lr
@@ -68,7 +68,7 @@ ENTRY(generic_bs_w_1)
 	strb	r3, [r1, r2]
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_w_2)
 	strh	r3, [r1, r2]
 	mov	pc, lr
@@ -96,7 +96,7 @@ ENTRY(generic_bs_rm_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_rm_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -144,7 +144,7 @@ ENTRY(generic_bs_wm_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_wm_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -192,7 +192,7 @@ ENTRY(generic_bs_rr_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_rr_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -240,7 +240,7 @@ ENTRY(generic_bs_wr_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_wr_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -287,7 +287,7 @@ ENTRY(generic_bs_sr_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_sr_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -319,7 +319,7 @@ ENTRY(generic_bs_sr_4)
  * copy region
  */
 
-#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_c_2)
 	add	r0, r1, r2
 	ldr	r2, [sp, #0]
diff --git a/sys/arch/arm/arm/cpu.c b/sys/arch/arm/arm/cpu.c
index 1811237ddc2..8c69b988d9f 100644
--- a/sys/arch/arm/arm/cpu.c
+++ b/sys/arch/arm/arm/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.9 2008/09/11 02:38:14 kevlo Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.10 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $	*/
 
 
@@ -168,7 +168,9 @@ enum cpu_class {
 	CPU_CLASS_ARM9EJS,
 	CPU_CLASS_ARM10E,
 	CPU_CLASS_SA1,
-	CPU_CLASS_XSCALE
+	CPU_CLASS_XSCALE,
+	CPU_CLASS_ARM11J,
+	CPU_CLASS_ARMv7
 };
 
 static const char * const generic_steppings[16] = {
@@ -223,10 +225,10 @@ static const char * const i80321_steppings[16] = {
 };
 
 static const char * const i80219_steppings[16] = {
-        "step A-0",     "rev 1",        "rev 2",        "rev 3",
-        "rev 4",        "rev 5",        "rev 6",        "rev 7",
-        "rev 8",        "rev 9",        "rev 10",       "rev 11",
-        "rev 12",       "rev 13",       "rev 14",       "rev 15",
+	"step A-0",	"rev 1",	"rev 2",	"rev 3",
+	"rev 4",	"rev 5",	"rev 6",	"rev 7",
+	"rev 8",	"rev 9",	"rev 10",	"rev 11",
+	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 
 /* Steppings for PXA2[15]0 */
@@ -351,9 +353,9 @@ const struct cpuidtab cpuids[] = {
 	{ CPU_ID_80321_600_B0,	CPU_CLASS_XSCALE,	"i80321 600MHz",
 	  i80321_steppings },
 
-	{ CPU_ID_80219_400,     CPU_CLASS_XSCALE,       "i80219 400MHz",
+	{ CPU_ID_80219_400,	CPU_CLASS_XSCALE,	"i80219 400MHz",
 	  i80219_steppings },
-	{ CPU_ID_80219_600,     CPU_CLASS_XSCALE,       "i80219 600MHz",
+	{ CPU_ID_80219_600,	CPU_CLASS_XSCALE,	"i80219 600MHz",
 	  i80219_steppings },
 
 	{ CPU_ID_PXA250A,	CPU_CLASS_XSCALE,	"PXA250",
@@ -366,7 +368,7 @@ const struct cpuidtab cpuids[] = {
 	  pxa2x0_steppings },
 	{ CPU_ID_PXA250C, 	CPU_CLASS_XSCALE,	"PXA250",
 	  pxa2x0_steppings },
-	{ CPU_ID_PXA27X,        CPU_CLASS_XSCALE,       "PXA27x",
+	{ CPU_ID_PXA27X,	CPU_CLASS_XSCALE,	"PXA27x",
 	  pxa27x_steppings },
 	{ CPU_ID_PXA210C, 	CPU_CLASS_XSCALE,	"PXA210",
 	  pxa2x0_steppings },
@@ -378,6 +380,17 @@ const struct cpuidtab cpuids[] = {
 	{ CPU_ID_IXP425_266,	CPU_CLASS_XSCALE,	"IXP425 266MHz",
 	  ixp425_steppings },
 
+	{ CPU_ID_ARM1136JS,	CPU_CLASS_ARM11J,	"ARM1136J-S",
+	  generic_steppings },
+	{ CPU_ID_ARM1136JSR1,	CPU_CLASS_ARM11J,	"ARM1136J-S R1",
+	  generic_steppings },
+
+	{ CPU_ID_OMAP3430,	CPU_CLASS_ARMv7,	"ARM OMAP3430",
+	  generic_steppings },
+	{ CPU_ID_OMAP3530,	CPU_CLASS_ARMv7,	"ARM OMAP3530",
+	  generic_steppings },
+
+
 	{ 0, CPU_CLASS_NONE, NULL, NULL }
 };
 
@@ -400,7 +413,10 @@ const struct cpu_classtab cpu_classes[] = {
 	{ "ARM9EJ-S",	"CPU_ARM9E" },		/* CPU_CLASS_ARM9EJS */
 	{ "ARM10E",	"CPU_ARM10" },		/* CPU_CLASS_ARM10E */
 	{ "SA-1",	"CPU_SA110" },		/* CPU_CLASS_SA1 */
-	{ "XScale",	"CPU_XSCALE_..." }	/* CPU_CLASS_XSCALE */
+	{ "XScale",	"CPU_XSCALE_..." },	/* CPU_CLASS_XSCALE */
+	{ "ARM11J",	"CPU_ARM11" },		/* CPU_CLASS_ARM11J */
+	{ "ARMv7",	"CPU_ARMv7" }		/* CPU_CLASS_ARMv7 */
+
 };
 
 /*
@@ -477,6 +493,8 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
 	case CPU_CLASS_ARM10E:
 	case CPU_CLASS_SA1:
 	case CPU_CLASS_XSCALE:
+	case CPU_CLASS_ARM11J:
+	case CPU_CLASS_ARMv7:
 		if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
 			printf(" DC disabled");
 		else
@@ -555,6 +573,13 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
 #ifdef CPU_ARM10
 	case CPU_CLASS_ARM10E:
 #endif
+#ifdef CPU_ARM11
+	case CPU_CLASS_ARM11J:
+#endif
+#ifdef CPU_ARMv7
+	case CPU_CLASS_ARMv7:
+#endif
+
 #if defined(CPU_SA110) || defined(CPU_SA1100) || \
     defined(CPU_SA1110) || defined(CPU_IXP12X0)
 	case CPU_CLASS_SA1:
diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index 316d6775132..f63dc12f918 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.c,v 1.8 2008/09/11 02:38:14 kevlo Exp $	*/
+/*	$OpenBSD: cpufunc.c,v 1.9 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $	*/
 
 /*
@@ -568,6 +568,121 @@ struct cpu_functions arm10_cpufuncs = {
 };
 #endif /* CPU_ARM10 */
 
+#ifdef CPU_ARM11
+struct cpu_functions arm11_cpufuncs = {
+	/* CPU functions */
+
+	cpufunc_id,			/* id				*/
+	cpufunc_nullop,			/* cpwait			*/
+
+	/* MMU functions */
+
+	cpufunc_control,		/* control			*/
+	cpufunc_domains,		/* Domain			*/
+	arm11_setttb,			/* Setttb			*/
+	cpufunc_faultstatus,		/* Faultstatus			*/
+	cpufunc_faultaddress,		/* Faultaddress			*/
+
+	/* TLB functions */
+
+	arm11_tlb_flushID,		/* tlb_flushID			*/
+	arm11_tlb_flushID_SE,		/* tlb_flushID_SE		*/
+	arm11_tlb_flushI,		/* tlb_flushI			*/
+	arm11_tlb_flushI_SE,		/* tlb_flushI_SE		*/
+	arm11_tlb_flushD,		/* tlb_flushD			*/
+	arm11_tlb_flushD_SE,		/* tlb_flushD_SE		*/
+
+	/* Cache operations */
+
+	armv5_icache_sync_all,		/* icache_sync_all	*/
+	armv5_icache_sync_range,	/* icache_sync_range	*/
+
+	armv5_dcache_wbinv_all,		/* dcache_wbinv_all	*/
+	armv5_dcache_wbinv_range,	/* dcache_wbinv_range	*/
+/*XXX*/	armv5_dcache_wbinv_range,	/* dcache_inv_range	*/
+	armv5_dcache_wb_range,		/* dcache_wb_range	*/
+
+	armv5_idcache_wbinv_all,	/* idcache_wbinv_all	*/
+	armv5_idcache_wbinv_range,	/* idcache_wbinv_range	*/
+
+	/* Other functions */
+
+	cpufunc_nullop,			/* flush_prefetchbuf	*/
+	arm11_drain_writebuf,		/* drain_writebuf	*/
+	cpufunc_nullop,			/* flush_brnchtgt_C	*/
+	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
+
+	arm11_cpu_sleep,		/* sleep (wait for interrupt) */
+
+	/* Soft functions */
+
+	cpufunc_null_fixup,		/* dataabt_fixup	*/
+	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
+
+	arm11_context_switch,		/* context_switch	*/
+
+	arm11_setup			/* cpu setup		*/
+};
+#endif /* CPU_ARM11 */
+
+#ifdef CPU_ARMv7
+struct cpu_functions armv7_cpufuncs = {
+	/* CPU functions */
+
+	cpufunc_id,			/* id			*/
+	cpufunc_nullop,			/* cpwait		*/
+
+	/* MMU functions */
+
+	cpufunc_control,		/* control		*/
+	cpufunc_domains,		/* Domain		*/
+	armv7_setttb,			/* Setttb		*/
+	cpufunc_faultstatus,		/* Faultstatus		*/
+	cpufunc_faultaddress,		/* Faultaddress		*/
+
+	/* TLB functions */
+
+	armv7_tlb_flushID,		/* tlb_flushID		*/
+	armv7_tlb_flushID_SE,		/* tlb_flushID_SE	*/
+	armv7_tlb_flushI,		/* tlb_flushI		*/
+	armv7_tlb_flushI_SE,		/* tlb_flushI_SE	*/
+	armv7_tlb_flushD,		/* tlb_flushD		*/
+	armv7_tlb_flushD_SE,		/* tlb_flushD_SE	*/
+
+	/* Cache operations */
+
+	armv7_icache_sync_all,		/* icache_sync_all	*/
+	armv7_icache_sync_range,	/* icache_sync_range	*/
+
+	armv7_dcache_wbinv_all,		/* dcache_wbinv_all	*/
+	armv7_dcache_wbinv_range,	/* dcache_wbinv_range	*/
+/*XXX*/	armv7_dcache_wbinv_range,	/* dcache_inv_range	*/
+	armv7_dcache_wb_range,		/* dcache_wb_range	*/
+
+	armv7_idcache_wbinv_all,	/* idcache_wbinv_all	*/
+	armv7_idcache_wbinv_range,	/* idcache_wbinv_range	*/
+
+	/* Other functions */
+
+	cpufunc_nullop,			/* flush_prefetchbuf	*/
+	armv7_drain_writebuf,		/* drain_writebuf	*/
+	cpufunc_nullop,			/* flush_brnchtgt_C	*/
+	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
+
+	armv7_cpu_sleep,		/* sleep (wait for interrupt) */
+
+	/* Soft functions */
+
+	cpufunc_null_fixup,		/* dataabt_fixup	*/
+	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
+
+	armv7_context_switch,		/* context_switch	*/
+
+	armv7_setup			/* cpu setup		*/
+};
+#endif /* CPU_ARMv7 */
+
+
 #ifdef CPU_SA110
 struct cpu_functions sa110_cpufuncs = {
 	/* CPU functions */
@@ -807,7 +922,7 @@ u_int cputype;
 u_int cpu_reset_needs_v4_MMU_disable;	/* flag used in locore.s */
 
 #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
-    defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+    defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
     defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
 static void get_cachetype_cp15 (void);
@@ -951,6 +1066,91 @@ get_cachetype_table()
 
 #endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA1111 || IXP12X0 */
 
+#ifdef CPU_ARMv7
+void arm_get_cachetype_cp15v7 (void);
+int	arm_dcache_l2_nsets;
+int	arm_dcache_l2_assoc;
+int	arm_dcache_l2_linesize;
+
+static int
+log2(int size)
+{
+	int i = 0;
+	while (size != 0)
+	for (i = 0; size != 0; i++)
+		size >>= 1;
+	return i;
+}
+
+void
+arm_get_cachetype_cp15v7(void)
+{
+	uint32_t cachereg;
+	uint32_t cache_level_id;
+	uint32_t line_size, ways, sets, size;
+	uint32_t sel;
+	__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
+		: "=r" (cache_level_id) :);
+
+	/* dcache L1 */
+	sel = 0;
+	__asm __volatile("mcr p15, 2, %0, c0, c0, 0"
+		:: "r" (sel));
+	__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
+		: "=r" (cachereg) :);
+	line_size = 1 << ((cachereg & 7)+4);
+	ways = ((0x00000ff8 & cachereg) >> 3) + 1;
+	sets = ((0x0ffff000 & cachereg) >> 13) + 1;
+	arm_pcache_unified = (cache_level_id & 0x7) == 2;
+	arm_pdcache_line_size = line_size;
+	arm_pdcache_ways = ways;
+	size = line_size * ways * sets;
+	arm_pdcache_size = size;
+
+	switch (cachereg & 0xc0000000) {
+	case 0x00000000:
+		arm_pcache_type = 0;
+	case 0x40000000:
+		arm_pcache_type = CPU_CT_CTYPE_WT;
+	case 0x80000000:
+	case 0xc0000000:
+		arm_pcache_type = CPU_CT_CTYPE_WB1;
+	}
+
+	/* icache L1 */
+	sel = 1;
+	__asm __volatile("mcr p15, 2, %0, c0, c0, 0"
+		:: "r" (sel));
+	__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
+		: "=r" (cachereg) :);
+	line_size = 1 << ((cachereg & 7)+4);
+	ways = ((0x00000ff8 & cachereg) >> 3) + 1;
+	sets = ((0x0ffff000 & cachereg) >> 13) + 1;
+	arm_picache_line_size = line_size;
+	size = line_size * ways * sets;
+	arm_picache_size = size;
+	arm_picache_ways = ways;
+
+	arm_dcache_align = arm_pdcache_line_size;
+
+	arm_dcache_align_mask = arm_dcache_align - 1;
+
+	/* ucache L2 */
+	sel = 1;
+	__asm __volatile("mcr p15, 2, %0, c0, c0, 0"
+		:: "r" (sel));
+	__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
+		: "=r" (cachereg) :);
+	line_size = 1 << ((cachereg & 7)+4);
+	ways = ((0x00000ff8 & cachereg) >> 3) + 1;
+	sets = ((0x0ffff000 & cachereg) >> 13) + 1;
+	arm_dcache_l2_nsets = log2(sets);
+	arm_dcache_l2_assoc = log2(ways);
+	arm_dcache_l2_linesize = log2(line_size);
+}
+#endif
+
+
 /*
  * Cannot panic here as we may not have a console yet ...
  */
@@ -1063,6 +1263,43 @@ set_cpufuncs()
 		return 0;
 	}
 #endif /* CPU_ARM10 */
+#ifdef CPU_ARM11
+	if (cputype == CPU_ID_ARM1136JS ||
+	    cputype == CPU_ID_ARM1136JSR1 || 1) {
+		cpufuncs = arm11_cpufuncs;
+		cpu_reset_needs_v4_MMU_disable = 1;	/* V4 or higher */
+		get_cachetype_cp15();
+		arm11_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
+		arm11_dcache_sets_max =
+		    (1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
+		    arm11_dcache_sets_inc;
+		arm11_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
+		arm11_dcache_index_max = 0U - arm11_dcache_index_inc;
+		pmap_pte_init_arm11();
+
+		/* Use powersave on this CPU. */
+		cpu_do_powersave = 1;
+		return 0;
+	}
+#endif /* CPU_ARM11 */
+#ifdef CPU_ARMv7
+	if (cputype == CPU_ID_OMAP3430 || cputype == CPU_ID_OMAP3530) {
+		cpufuncs = armv7_cpufuncs;
+		cpu_reset_needs_v4_MMU_disable = 1;	/* V4 or higher */
+		arm_get_cachetype_cp15v7();
+		armv7_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
+		armv7_dcache_sets_max =
+		    (1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
+		    armv7_dcache_sets_inc;
+		armv7_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
+		armv7_dcache_index_max = 0U - armv7_dcache_index_inc;
+		pmap_pte_init_armv7();
+
+		/* Use powersave on this CPU. */
+		cpu_do_powersave = 1;
+		return 0;
+	}
+#endif /* CPU_ARMv7 */
 #ifdef CPU_SA110
 	if (cputype == CPU_ID_SA110) {
 		cpufuncs = sa110_cpufuncs;
@@ -1607,7 +1844,7 @@ late_abort_fixup(arg)
 	defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
 	defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
 	defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
-	defined(CPU_ARM10)
+	defined(CPU_ARM10) | defined(CPU_ARM11) || defined(CPU_ARMv7)
 
 #define IGN	0
 #define OR	1
@@ -1995,6 +2232,109 @@ arm10_setup(args)
 }
 #endif	/* CPU_ARM9E || CPU_ARM10 */
 
+#ifdef CPU_ARM11
+struct cpu_option arm11_options[] = {
+	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "cpu.nocache",	OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "arm11.cache",	BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "arm11.icache",	BIC, OR,  CPU_CONTROL_IC_ENABLE },
+	{ "arm11.dcache",	BIC, OR,  CPU_CONTROL_DC_ENABLE },
+	{ NULL,			IGN, IGN, 0 }
+};
+
+void
+arm11_setup(args)
+	char *args;
+{
+	int cpuctrl, cpuctrlmask;
+
+	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+	    /* | CPU_CONTROL_BPRD_ENABLE */;
+	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+	    | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
+	    | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+	    | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+	cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
+
+#ifdef __ARMEB__
+	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
+#endif
+
+	/* Clear out the cache */
+	cpu_idcache_wbinv_all();
+
+	/* Now really make sure they are clean.  */
+	asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
+
+	/* Set the control register */
+	curcpu()->ci_ctrl = cpuctrl;
+	cpu_control(0xffffffff, cpuctrl);
+
+	/* And again. */
+	cpu_idcache_wbinv_all();
+}
+#endif	/* CPU_ARM11 */
+
+#ifdef CPU_ARMv7
+struct cpu_option armv7_options[] = {
+	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "cpu.nocache",	OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "armv7.cache",	BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "armv7.icache",	BIC, OR,  CPU_CONTROL_IC_ENABLE },
+	{ "armv7.dcache",	BIC, OR,  CPU_CONTROL_DC_ENABLE },
+	{ NULL,			IGN, IGN, 0 }
+};
+
+void
+armv7_setup(args)
+	char *args;
+{
+	int cpuctrl, cpuctrlmask;
+
+	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+	    /* | CPU_CONTROL_BPRD_ENABLE */;
+	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+	    | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
+	    | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+	    | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+	cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl);
+
+#ifdef __ARMEB__
+	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
+#endif
+
+	/* Clear out the cache */
+	cpu_idcache_wbinv_all();
+
+	/* Now really make sure they are clean.  */
+	/* XXX */
+	/*
+	asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
+	*/
+
+	/* Set the control register */
+	curcpu()->ci_ctrl = cpuctrl;
+	cpu_control(0xffffffff, cpuctrl);
+
+	/* And again. */
+	cpu_idcache_wbinv_all();
+}
+#endif	/* CPU_ARMv7 */
+
 #ifdef CPU_SA110
 struct cpu_option sa110_options[] = {
 	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
diff --git a/sys/arch/arm/arm/db_interface.c b/sys/arch/arm/arm/db_interface.c
index 198a391bd7a..cdc4ecfd353 100644
--- a/sys/arch/arm/arm/db_interface.c
+++ b/sys/arch/arm/arm/db_interface.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_interface.c,v 1.5 2006/05/26 17:06:39 miod Exp $	*/
+/*	$OpenBSD: db_interface.c,v 1.6 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: db_interface.c,v 1.34 2003/10/26 23:11:15 chris Exp $	*/
 
 /* 
@@ -43,6 +43,7 @@
 #include <uvm/uvm_extern.h>
 
 #include <arm/db_machdep.h>
+#include <machine/pmap.h>
 #include <arm/undefined.h>
 #include <ddb/db_access.h>
 #include <ddb/db_command.h>
diff --git a/sys/arch/arm/arm/pmap.c b/sys/arch/arm/arm/pmap.c
index cad1f22043d..312c77d7dc5 100644
--- a/sys/arch/arm/arm/pmap.c
+++ b/sys/arch/arm/arm/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.21 2009/04/14 16:01:04 oga Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.22 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $	*/
 
 /*
@@ -2441,6 +2441,30 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot)
 }
 
 void
+pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable)
+{
+	struct vm_page *pg;
+	struct pv_entry *pv;
+	pt_entry_t *pte;
+
+	pmap_kenter_pa(va, pa, prot);
+
+	if (cacheable == 0) {
+		if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
+			simple_lock(&pg->mdpage.pvh_slock);
+			pv = pmap_find_pv(pg, pmap_kernel(), va);
+			if (pv != NULL)
+				pv->pv_flags |= PVF_NC;
+			simple_unlock(&pg->mdpage.pvh_slock);
+		}
+
+		pte = vtopte(va);
+		*pte &= ~L2_S_CACHE_MASK;
+		PTE_SYNC(pte);
+	}
+}
+
+void
 pmap_kremove(vaddr_t va, vsize_t len)
 {
 	struct l2_bucket *l2b;
@@ -4689,6 +4713,52 @@ pmap_pte_init_arm10(void)
 }
 #endif /* CPU_ARM10 */
 
+#if defined(CPU_ARM11)
+void
+pmap_pte_init_arm11(void)
+{
+
+	/*
+	 * XXX 
+	 * ARM11 is compatible with generic, but we want to use
+	 * write-through caching for now.
+	 */
+	pmap_pte_init_generic();
+
+	pte_l1_s_cache_mode = L1_S_B | L1_S_C;
+	pte_l2_l_cache_mode = L2_B | L2_C;
+	pte_l2_s_cache_mode = L2_B | L2_C;
+
+	pte_l1_s_cache_mode_pt = L1_S_C;
+	pte_l2_l_cache_mode_pt = L2_C;
+	pte_l2_s_cache_mode_pt = L2_C;
+
+}
+#endif /* CPU_ARM11 */
+
+#if defined(CPU_ARMv7)
+void
+pmap_pte_init_armv7(void)
+{
+
+	/*
+	 * XXX 
+	 * ARMv7 is compatible with generic, but we to use proper TEX settings
+	 * - not yet however...
+	 */
+	pmap_pte_init_generic();
+
+	pte_l1_s_cache_mode = L1_S_B | L1_S_C;
+	pte_l2_l_cache_mode = L2_B | L2_C;
+	pte_l2_s_cache_mode = L2_B | L2_C;
+
+	pte_l1_s_cache_mode_pt = L1_S_C;
+	pte_l2_l_cache_mode_pt = L2_C;
+	pte_l2_s_cache_mode_pt = L2_C;
+
+}
+#endif /* CPU_ARMv7 */
+
 #if ARM_MMU_SA1 == 1
 void
 pmap_pte_init_sa1(void)
diff --git a/sys/arch/arm/armv7/armv7_a4x_io.S b/sys/arch/arm/armv7/armv7_a4x_io.S
new file mode 100644
index 00000000000..7efc5cbaeb1
--- /dev/null
+++ b/sys/arch/arm/armv7/armv7_a4x_io.S
@@ -0,0 +1,104 @@
+/*	$OpenBSD: armv7_a4x_io.S,v 1.1 2009/05/08 02:57:32 drahn Exp $ */
+/*	$NetBSD: pxa2x0_a4x_io.S,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
+
+/*
+ * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or 
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*	
+ * There are simple bus space functions for IO registers mapped at
+ * 32-bit aligned positions.  offset is multiplied by 4.  
+ */
+
+#include <machine/asm.h>
+
+/*
+ * bus_space I/O functions with offset*4
+ */
+
+/*
+ * read single
+ */
+
+ENTRY(a4x_bs_r_1)
+	ldrb	r0, [r1, r2, LSL #2]
+	mov	pc, lr
+
+ENTRY(a4x_bs_r_2)
+	mov	r2, r2, LSL #2
+	ldrh	r0, [r1, r2]
+	mov	pc, lr
+
+ENTRY(a4x_bs_r_4)
+	ldr	r0, [r1, r2, LSL #2]
+	mov	pc, lr
+
+/*
+ * write single
+ */
+
+ENTRY(a4x_bs_w_1)
+	strb	r3, [r1, r2, LSL #2]
+	mov	pc, lr
+
+ENTRY(a4x_bs_w_2)
+	mov	r2, r2, LSL #2
+	strh	r3, [r1, r2]
+	mov	pc, lr
+
+ENTRY(a4x_bs_w_4)
+	str	r3, [r1, r2, LSL #2]
+	mov	pc, lr
+
+/*
+ * read multiple
+ */
+ENTRY(a4x_bs_rm_1)
+	mov r2, r2, LSL #2
+	b generic_bs_rm_1
+	
+ENTRY(a4x_bs_rm_2)
+	mov r2, r2, LSL #2
+	b generic_armv4_bs_rm_2
+
+
+
+/*
+ * write multiple
+ */
+ENTRY(a4x_bs_wm_1)
+	mov r2, r2, LSL #2
+	b generic_bs_wm_1
+	
+ENTRY(a4x_bs_wm_2)
+	mov r2, r2, LSL #2
+	b generic_armv4_bs_wm_2
diff --git a/sys/arch/arm/armv7/armv7_a4x_space.c b/sys/arch/arm/armv7/armv7_a4x_space.c
new file mode 100644
index 00000000000..3fea5a3129e
--- /dev/null
+++ b/sys/arch/arm/armv7/armv7_a4x_space.c
@@ -0,0 +1,136 @@
+/*	$OpenBSD: armv7_a4x_space.c,v 1.1 2009/05/08 02:57:32 drahn Exp $ */
+/*	$NetBSD: armv7_a4x_space.c,v 1.2 2003/07/15 00:24:54 lukem Exp $ */
+
+/*
+ * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or 
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Bus space tag for 8/16-bit devices on 32-bit bus.
+ * all registers are located at the address of multiple of 4.
+ */
+
+#include <sys/cdefs.h>
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(armv7);
+bs_protos(a4x);
+bs_protos(generic);
+bs_protos(generic_armv4);
+bs_protos(bs_notimpl);
+
+struct bus_space armv7_a4x_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	armv7_bs_map,
+	armv7_bs_unmap,
+	armv7_bs_subregion,
+
+	/* allocation/deallocation */
+	armv7_bs_alloc,	/* not implemented */
+	armv7_bs_free,		/* not implemented */
+
+	/* get kernel virtual address */
+	armv7_bs_vaddr,
+
+	/* mmap */
+	bs_notimpl_bs_mmap,
+
+	/* barrier */
+	armv7_bs_barrier,
+
+	/* read (single) */
+	a4x_bs_r_1,
+	a4x_bs_r_2,
+	a4x_bs_r_4,
+	bs_notimpl_bs_r_8,
+
+	/* read multiple */
+	a4x_bs_rm_1,
+	a4x_bs_rm_2,
+	bs_notimpl_bs_rm_4,
+	bs_notimpl_bs_rm_8,
+
+	/* read region */
+	bs_notimpl_bs_rr_1,
+	bs_notimpl_bs_rr_2,
+	bs_notimpl_bs_rr_4,
+	bs_notimpl_bs_rr_8,
+
+	/* write (single) */
+	a4x_bs_w_1,
+	a4x_bs_w_2,
+	a4x_bs_w_4,
+	bs_notimpl_bs_w_8,
+
+	/* write multiple */
+	a4x_bs_wm_1,
+	a4x_bs_wm_2,
+	bs_notimpl_bs_wm_4,
+	bs_notimpl_bs_wm_8,
+
+	/* write region */
+	bs_notimpl_bs_wr_1,
+	bs_notimpl_bs_wr_2,
+	bs_notimpl_bs_wr_4,
+	bs_notimpl_bs_wr_8,
+
+	/* set multiple */
+	bs_notimpl_bs_sm_1,
+	bs_notimpl_bs_sm_2,
+	bs_notimpl_bs_sm_4,
+	bs_notimpl_bs_sm_8,
+
+	/* set region */
+	bs_notimpl_bs_sr_1,
+	bs_notimpl_bs_sr_2,
+	bs_notimpl_bs_sr_4,
+	bs_notimpl_bs_sr_8,
+
+	/* copy */
+	bs_notimpl_bs_c_1,
+	bs_notimpl_bs_c_2,
+	bs_notimpl_bs_c_4,
+	bs_notimpl_bs_c_8,
+};
+
+
+
diff --git a/sys/arch/arm/armv7/armv7_mutex.c b/sys/arch/arm/armv7/armv7_mutex.c
new file mode 100644
index 00000000000..bc8b37693d7
--- /dev/null
+++ b/sys/arch/arm/armv7/armv7_mutex.c
@@ -0,0 +1,70 @@
+/*	$OpenBSD: armv7_mutex.c,v 1.1 2009/05/08 02:57:32 drahn Exp $	*/
+
+/*
+ * Copyright (c) 2004 Artur Grabowski <art@openbsd.org>
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ *
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL  DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ */
+
+#include <sys/param.h>
+#include <sys/mutex.h>
+#include <sys/systm.h>
+
+#include <machine/intr.h>
+
+#ifdef MULTIPROCESSOR
+#error This code needs work
+#endif
+
+
+/* rewrite with the proper lock mechanism */
+
+/*
+ * Single processor systems don't need any mutexes, but they need the spl
+ * raising semantics of the mutexes.
+ */
+void
+mtx_init(struct mutex *mtx, int wantipl)
+{
+	mtx->mtx_oldipl = 0;
+	mtx->mtx_wantipl = wantipl;
+	mtx->mtx_lock = 0;
+}
+
+void
+mtx_enter(struct mutex *mtx)
+{
+	if (mtx->mtx_wantipl != IPL_NONE)
+		mtx->mtx_oldipl = _splraise(mtx->mtx_wantipl);
+
+	MUTEX_ASSERT_UNLOCKED(mtx);
+	mtx->mtx_lock = 1;
+}
+
+void
+mtx_leave(struct mutex *mtx)
+{
+	MUTEX_ASSERT_LOCKED(mtx);
+	mtx->mtx_lock = 0;
+	if (mtx->mtx_wantipl != IPL_NONE)
+		splx(mtx->mtx_oldipl);
+}
diff --git a/sys/arch/arm/armv7/armv7_space.c b/sys/arch/arm/armv7/armv7_space.c
new file mode 100644
index 00000000000..97fb452e7c0
--- /dev/null
+++ b/sys/arch/arm/armv7/armv7_space.c
@@ -0,0 +1,267 @@
+/*	$OpenBSD: armv7_space.c,v 1.1 2009/05/08 02:57:32 drahn Exp $ */
+
+/*
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * bus_space functions for Intel PXA2[51]0 application processor.
+ * Derived from i80321_space.c.
+ */
+
+#include <sys/cdefs.h>
+/*
+__KERNEL_RCSID(0, "$NetBSD: armv7_space.c,v 1.5 2004/06/07 19:45:22 nathanw Exp $");
+*/
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(armv7);
+bs_protos(generic);
+bs_protos(generic_armv4);
+bs_protos(bs_notimpl);
+
+struct bus_space armv7_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	armv7_bs_map,
+	armv7_bs_unmap,
+	armv7_bs_subregion,
+
+	/* allocation/deallocation */
+	armv7_bs_alloc,	/* not implemented */
+	armv7_bs_free,		/* not implemented */
+
+	/* get kernel virtual address */
+	armv7_bs_vaddr,
+
+	/* mmap */
+	bs_notimpl_bs_mmap,
+
+	/* barrier */
+	armv7_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_armv4_bs_r_2,
+	generic_bs_r_4,
+	bs_notimpl_bs_r_8,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	generic_armv4_bs_rm_2,
+	generic_bs_rm_4,
+	bs_notimpl_bs_rm_8,
+
+	/* read region */
+	generic_bs_rr_1,
+	generic_armv4_bs_rr_2,
+	generic_bs_rr_4,
+	bs_notimpl_bs_rr_8,
+
+	/* write (single) */
+	generic_bs_w_1,
+	generic_armv4_bs_w_2,
+	generic_bs_w_4,
+	bs_notimpl_bs_w_8,
+
+	/* write multiple */
+	generic_bs_wm_1,
+	generic_armv4_bs_wm_2,
+	generic_bs_wm_4,
+	bs_notimpl_bs_wm_8,
+
+	/* write region */
+	generic_bs_wr_1,
+	generic_armv4_bs_wr_2,
+	generic_bs_wr_4,
+	bs_notimpl_bs_wr_8,
+
+	/* set multiple */
+	bs_notimpl_bs_sm_1,
+	bs_notimpl_bs_sm_2,
+	bs_notimpl_bs_sm_4,
+	bs_notimpl_bs_sm_8,
+
+	/* set region */
+	generic_bs_sr_1,
+	generic_armv4_bs_sr_2,
+	bs_notimpl_bs_sr_4,
+	bs_notimpl_bs_sr_8,
+
+	/* copy */
+	bs_notimpl_bs_c_1,
+	generic_armv4_bs_c_2,
+	bs_notimpl_bs_c_4,
+	bs_notimpl_bs_c_8,
+};
+
+int
+armv7_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
+	      int flag, bus_space_handle_t *bshp)
+{
+	u_long startpa, endpa, pa;
+	vaddr_t va;
+	pt_entry_t *pte;
+
+	if ((u_long)bpa > (u_long)KERNEL_BASE) {
+		/* Some IO registers (ex. UART ports for console)
+		   are mapped to fixed address by board specific
+		   routine. */
+		*bshp = bpa;
+		return(0);
+	}
+
+	startpa = trunc_page(bpa);
+	endpa = round_page(bpa + size);
+
+	/* XXX use extent manager to check duplicate mapping */
+
+	va = uvm_km_valloc(kernel_map, endpa - startpa);
+	if (! va)
+		return(ENOMEM);
+
+	*bshp = (bus_space_handle_t)(va + (bpa - startpa));
+
+	for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
+		if ((flag & BUS_SPACE_MAP_CACHEABLE) == 0) {
+			pte = vtopte(va);
+			*pte &= ~L2_S_CACHE_MASK;
+			PTE_SYNC(pte);
+			/* XXX: pmap_kenter_pa() also does PTE_SYNC(). a bit of
+			 *      waste.
+			 */
+		}
+	}
+	pmap_update(pmap_kernel());
+
+	return(0);
+}
+
+void
+armv7_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+	if (bsh > (u_long)KERNEL_BASE) 
+		return;
+
+	uvm_km_free(kernel_map, bsh, size);
+}
+
+
+int
+armv7_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+	*nbshp = bsh + offset;
+	return (0);
+}
+
+void
+armv7_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t len, int flags)
+{
+
+	/* Nothing to do. */
+}
+
+void *
+armv7_bs_vaddr(void *t, bus_space_handle_t bsh)
+{
+
+	return ((void *)bsh);
+}
+
+
+int
+armv7_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+    bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+	panic("armv7_io_bs_alloc(): not implemented");
+}
+
+void    
+armv7_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+	panic("armv7_io_bs_free(): not implemented");
+}
+
diff --git a/sys/arch/arm/armv7/armv7reg.h b/sys/arch/arm/armv7/armv7reg.h
new file mode 100644
index 00000000000..ef901d1c284
--- /dev/null
+++ b/sys/arch/arm/armv7/armv7reg.h
@@ -0,0 +1 @@
+#define MPHONE_INTCTL_BASE	0
diff --git a/sys/arch/arm/armv7/armv7var.h b/sys/arch/arm/armv7/armv7var.h
new file mode 100644
index 00000000000..926bfaf9f83
--- /dev/null
+++ b/sys/arch/arm/armv7/armv7var.h
@@ -0,0 +1,4 @@
+extern struct bus_space armv7_bs_tag;
+extern struct bus_space armv7_a4x_bs_tag;
+
+void armv7_intr_bootstrap(vaddr_t);
diff --git a/sys/arch/arm/armv7/avic_intr.h b/sys/arch/arm/armv7/avic_intr.h
new file mode 100644
index 00000000000..a03354c738d
--- /dev/null
+++ b/sys/arch/arm/armv7/avic_intr.h
@@ -0,0 +1,112 @@
+/*	$OpenBSD: avic_intr.h,v 1.1 2009/05/08 02:57:32 drahn Exp $ */
+/*	$NetBSD: pxa2x0_intr.h,v 1.4 2003/07/05 06:53:08 dogcow Exp $ */
+
+/* Derived from i80321_intr.h */
+/* Derived from xscale_intr.h */
+
+/*
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARMv7_AVIC_INTR_H_
+#define _ARMv7_AVIC_INTR_H_
+
+#define	ARM_IRQ_HANDLER	_C_LABEL(armv7avic_irq_handler)
+
+#ifndef _LOCORE
+
+#include <arm/armreg.h>
+#include <arm/cpufunc.h>
+#include <machine/intr.h>
+#include <arm/softintr.h>
+
+extern vaddr_t armv7avic_base;		/* Shared with armv7avic_irq.S */
+#define read_icu(offset) (*(volatile uint32_t *)(armv7avic_base+(offset)))
+#define write_icu(offset,value) \
+ (*(volatile uint32_t *)(armv7avic_base+(offset))=(value))
+
+extern __volatile int current_spl_level;
+extern __volatile int softint_pending;
+extern int armv7avic_imask[];
+void armv7avic_do_pending(void);
+
+#define SI_TO_IRQBIT(si)  (1U<<(si))
+void armv7avic_setipl(int new);
+void armv7avic_splx(int new);
+int armv7avic_splraise(int ipl);
+int armv7avic_spllower(int ipl);
+void armv7avic_setsoftintr(int si);
+
+
+/*
+ * An useful function for interrupt handlers.
+ * XXX: This shouldn't be here.
+ */
+static __inline int
+find_first_bit( uint32_t bits )
+{
+	int count;
+
+	/* since CLZ is available only on ARMv5, this isn't portable
+	 * to all ARM CPUs.  This file is for ARMv7_AVIC processor. 
+	 */
+	asm( "clz %0, %1" : "=r" (count) : "r" (bits) );
+	return 31-count;
+}
+
+
+int	_splraise(int);
+int	_spllower(int);
+void	splx(int);
+void	_setsoftintr(int);
+
+/*
+ * This function *MUST* be called very early on in a port's
+ * initarm() function, before ANY spl*() functions are called.
+ *
+ * The parameter is the virtual address of the ARMv7_AVIC's Interrupt
+ * Controller registers.
+ */
+void armv7avic_intr_bootstrap(vaddr_t);
+
+void armv7avic_irq_handler(void *);
+void *armv7avic_intr_establish(int irqno, int level, int (*func)(void *),
+    void *cookie, char *name);
+void armv7avic_intr_disestablish(void *cookie);
+const char *armv7avic_intr_string(void *cookie);
+
+#endif /* ! _LOCORE */
+
+#endif /* _ARMv7_AVIC_INTR_H_ */
+
diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm
index 7218097bf26..9b07d5b6548 100644
--- a/sys/arch/arm/conf/files.arm
+++ b/sys/arch/arm/conf/files.arm
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.arm,v 1.14 2008/09/11 02:38:14 kevlo Exp $
+#	$OpenBSD: files.arm,v 1.15 2009/05/08 02:57:32 drahn Exp $
 #	$NetBSD: files.arm,v 1.76 2003/11/05 12:53:15 scw Exp $
 
 # Floating point emulator
@@ -66,6 +66,7 @@ file	arch/arm/arm/cpufunc_asm_armv4.S	cpu_arm9 | cpu_arm9e |
 							cpu_xscale_pxa2x0
 file	arch/arm/arm/cpufunc_asm_armv5.S	cpu_arm10
 file	arch/arm/arm/cpufunc_asm_armv5_ec.S	cpu_arm9e | cpu_arm10
+file	arch/arm/arm/cpufunc_asm_armv7.S	cpu_armv7
 file	arch/arm/arm/cpufunc_asm_sa1.S		cpu_sa110 | cpu_sa1100 |
 							cpu_sa1110 |
 							cpu_ixp12x0
diff --git a/sys/arch/arm/conf/ldscript.tail b/sys/arch/arm/conf/ldscript.tail
index a4cfc438f6c..ba13fedf6cb 100644
--- a/sys/arch/arm/conf/ldscript.tail
+++ b/sys/arch/arm/conf/ldscript.tail
@@ -1,4 +1,4 @@
-/*     $OpenBSD: ldscript.tail,v 1.2 2005/01/02 19:57:57 drahn Exp $         */
+/*     $OpenBSD: ldscript.tail,v 1.3 2009/05/08 02:57:32 drahn Exp $         */
   } =0
   PROVIDE (__etext = .);
   PROVIDE (_etext = .);
@@ -24,6 +24,7 @@
   __bss_start = .;
   __bss_start__ = .;
   .sbss      :
+  AT (LOADADDR(.sdata) + (ADDR(.sbss) - ADDR(.sdata)))
   {
     PROVIDE (__sbss_start = .);
     PROVIDE (___sbss_start = .);
@@ -35,6 +36,7 @@
     PROVIDE (___sbss_end = .);
   }
   .bss       :
+  AT (LOADADDR(.sbss) + (ADDR(.bss) - ADDR(.sbss)))
   {
    *(.dynbss)
    *(.bss)
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
index e82954ef952..b1ce7f9d296 100644
--- a/sys/arch/arm/include/armreg.h
+++ b/sys/arch/arm/include/armreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: armreg.h,v 1.4 2008/09/11 02:38:14 kevlo Exp $	*/
+/*	$OpenBSD: armreg.h,v 1.5 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $	*/
 
 /*
@@ -52,7 +52,7 @@
  *      +-+-+-+-+-+-------------------------------------+-+-+-+---------+
  */
 
-#define	PSR_FLAGS 0xf0000000	/* flags */
+#define PSR_FLAGS 0xf0000000	/* flags */
 #define PSR_N_bit (1 << 31)	/* negative */
 #define PSR_Z_bit (1 << 30)	/* zero */
 #define PSR_C_bit (1 << 29)	/* carry */
@@ -118,7 +118,7 @@
 #define CPU_ID_ARM_LTD		0x41000000 /* 'A' */
 #define CPU_ID_DEC		0x44000000 /* 'D' */
 #define CPU_ID_INTEL		0x69000000 /* 'i' */
-#define	CPU_ID_TI		0x54000000 /* 'T' */
+#define CPU_ID_TI		0x54000000 /* 'T' */
 
 /* How to decide what format the CPUID is in. */
 #define CPU_ID_ISOLD(x)		(((x) & 0x0000f000) == 0x00000000)
@@ -143,6 +143,8 @@
 #define CPU_ID_ARCH_V5		0x00030000
 #define CPU_ID_ARCH_V5T		0x00040000
 #define CPU_ID_ARCH_V5TE	0x00050000
+#define CPU_ID_ARCH_V6		0x00070000
+#define CPU_ID_ARCH_V7		0x00080000
 #define CPU_ID_VARIANT_MASK	0x00f00000
 
 /* Next three nybbles are part number */
@@ -187,13 +189,16 @@
 #define CPU_ID_ARM926EJS	0x41069260
 #define CPU_ID_ARM940T		0x41029400 /* XXX no MMU */
 #define CPU_ID_ARM946ES		0x41049460 /* XXX no MMU */
-#define	CPU_ID_ARM966ES		0x41049660 /* XXX no MMU */
-#define	CPU_ID_ARM966ESR1	0x41059660 /* XXX no MMU */
+#define CPU_ID_ARM966ES		0x41049660 /* XXX no MMU */
+#define CPU_ID_ARM966ESR1	0x41059660 /* XXX no MMU */
 #define CPU_ID_ARM1020E		0x4115a200 /* (AKA arm10 rev 1) */
 #define CPU_ID_ARM1022ES	0x4105a220
+#define CPU_ID_ARM1022EJS	0x4106a260
+#define CPU_ID_ARM1136JS	0x4107b360
+#define CPU_ID_ARM1136JSR1	0x4117b360
 #define CPU_ID_SA110		0x4401a100
 #define CPU_ID_SA1100		0x4401a110
-#define	CPU_ID_TI925T		0x54029250
+#define CPU_ID_TI925T		0x54029250
 #define CPU_ID_SA1110		0x6901b110
 #define CPU_ID_IXP1200		0x6901c120
 #define CPU_ID_80200		0x69052000
@@ -208,13 +213,16 @@
 #define CPU_ID_80219_400        0x69052e20
 #define CPU_ID_80219_600        0x69052e30
 #define CPU_ID_PXA27X		0x69054110
-#define	CPU_ID_80321_400	0x69052420
-#define	CPU_ID_80321_600	0x69052430
-#define	CPU_ID_80321_400_B0	0x69052c20
-#define	CPU_ID_80321_600_B0	0x69052c30
-#define	CPU_ID_IXP425_533	0x690541c0
-#define	CPU_ID_IXP425_400	0x690541d0
-#define	CPU_ID_IXP425_266	0x690541f0
+#define CPU_ID_80321_400	0x69052420
+#define CPU_ID_80321_600	0x69052430
+#define CPU_ID_80321_400_B0	0x69052c20
+#define CPU_ID_80321_600_B0	0x69052c30
+#define CPU_ID_IXP425_533	0x690541c0
+#define CPU_ID_IXP425_400	0x690541d0
+#define CPU_ID_IXP425_266	0x690541f0
+#define CPU_ID_OMAP3430		0x411fc080
+#define CPU_ID_OMAP3530		0x411fc090	/* XXX */
+
 
 /* ARM3-specific coprocessor 15 registers */
 #define ARM3_CP15_FLUSH		1
@@ -285,29 +293,29 @@
 #define CPU_CONTROL_IDC_ENABLE	CPU_CONTROL_DC_ENABLE
 
 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
-#define	XSCALE_AUXCTL_K		0x00000001 /* dis. write buffer coalescing */
-#define	XSCALE_AUXCTL_P		0x00000002 /* ECC protect page table access */
-#define	XSCALE_AUXCTL_MD_WB_RA	0x00000000 /* mini-D$ wb, read-allocate */
-#define	XSCALE_AUXCTL_MD_WB_RWA	0x00000010 /* mini-D$ wb, read/write-allocate */
-#define	XSCALE_AUXCTL_MD_WT	0x00000020 /* mini-D$ wt, read-allocate */
-#define	XSCALE_AUXCTL_MD_MASK	0x00000030
+#define XSCALE_AUXCTL_K		0x00000001 /* dis. write buffer coalescing */
+#define XSCALE_AUXCTL_P		0x00000002 /* ECC protect page table access */
+#define XSCALE_AUXCTL_MD_WB_RA	0x00000000 /* mini-D$ wb, read-allocate */
+#define XSCALE_AUXCTL_MD_WB_RWA	0x00000010 /* mini-D$ wb, read/write-allocate */
+#define XSCALE_AUXCTL_MD_WT	0x00000020 /* mini-D$ wt, read-allocate */
+#define XSCALE_AUXCTL_MD_MASK	0x00000030
 
 /* Cache type register definitions */
-#define	CPU_CT_ISIZE(x)		((x) & 0xfff)		/* I$ info */
-#define	CPU_CT_DSIZE(x)		(((x) >> 12) & 0xfff)	/* D$ info */
-#define	CPU_CT_S		(1U << 24)		/* split cache */
-#define	CPU_CT_CTYPE(x)		(((x) >> 25) & 0xf)	/* cache type */
-
-#define	CPU_CT_CTYPE_WT		0	/* write-through */
-#define	CPU_CT_CTYPE_WB1	1	/* write-back, clean w/ read */
-#define	CPU_CT_CTYPE_WB2	2	/* w/b, clean w/ cp15,7 */
-#define	CPU_CT_CTYPE_WB6	6	/* w/b, cp15,7, lockdown fmt A */
-#define	CPU_CT_CTYPE_WB7	7	/* w/b, cp15,7, lockdown fmt B */
-
-#define	CPU_CT_xSIZE_LEN(x)	((x) & 0x3)		/* line size */
-#define	CPU_CT_xSIZE_M		(1U << 2)		/* multiplier */
-#define	CPU_CT_xSIZE_ASSOC(x)	(((x) >> 3) & 0x7)	/* associativity */
-#define	CPU_CT_xSIZE_SIZE(x)	(((x) >> 6) & 0x7)	/* size */
+#define CPU_CT_ISIZE(x)		((x) & 0xfff)		/* I$ info */
+#define CPU_CT_DSIZE(x)		(((x) >> 12) & 0xfff)	/* D$ info */
+#define CPU_CT_S		(1U << 24)		/* split cache */
+#define CPU_CT_CTYPE(x)		(((x) >> 25) & 0xf)	/* cache type */
+
+#define CPU_CT_CTYPE_WT		0	/* write-through */
+#define CPU_CT_CTYPE_WB1	1	/* write-back, clean w/ read */
+#define CPU_CT_CTYPE_WB2	2	/* w/b, clean w/ cp15,7 */
+#define CPU_CT_CTYPE_WB6	6	/* w/b, cp15,7, lockdown fmt A */
+#define CPU_CT_CTYPE_WB7	7	/* w/b, cp15,7, lockdown fmt B */
+
+#define CPU_CT_xSIZE_LEN(x)	((x) & 0x3)		/* line size */
+#define CPU_CT_xSIZE_M		(1U << 2)		/* multiplier */
+#define CPU_CT_xSIZE_ASSOC(x)	(((x) >> 3) & 0x7)	/* associativity */
+#define CPU_CT_xSIZE_SIZE(x)	(((x) >> 6) & 0x7)	/* size */
 
 /* Fault status register definitions */
 
@@ -331,13 +339,13 @@
 #define FAULT_PERM_S    0x0d /* Permission -- Section */
 #define FAULT_PERM_P    0x0f /* Permission -- Page */
 
-#define	FAULT_IMPRECISE	0x400	/* Imprecise exception (XSCALE) */
+#define FAULT_IMPRECISE	0x400	/* Imprecise exception (XSCALE) */
 
 /*
  * Address of the vector page, low and high versions.
  */
-#define	ARM_VECTORS_LOW		0x00000000U
-#define	ARM_VECTORS_HIGH	0xffff0000U
+#define ARM_VECTORS_LOW		0x00000000U
+#define ARM_VECTORS_HIGH	0xffff0000U
 
 /*
  * ARM Instructions
diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h
index e54d179becf..00c6b909b9f 100644
--- a/sys/arch/arm/include/cpuconf.h
+++ b/sys/arch/arm/include/cpuconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpuconf.h,v 1.4 2008/09/11 02:38:14 kevlo Exp $	*/
+/*	$OpenBSD: cpuconf.h,v 1.5 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $	*/
 
 /*
@@ -76,6 +76,18 @@
 #define	ARM_ARCH_5	0
 #endif
 
+#if defined(CPU_ARM11)
+#define ARM_ARCH_6     1
+#else 
+#define ARM_ARCH_6     0
+#endif
+
+#if defined(CPU_ARMv7)
+#define ARM_ARCH_7     1
+#else 
+#define ARM_ARCH_7     0
+#endif
+
 /*
  * Define which MMU classes are configured:
  *
@@ -99,7 +111,7 @@
 
 #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) ||	\
      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||	\
-     defined(CPU_ARM10))
+     defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) )
 #define	ARM_MMU_GENERIC		1
 #else
 #define	ARM_MMU_GENERIC		0
@@ -119,8 +131,14 @@
 #define	ARM_MMU_XSCALE		0
 #endif
 
+#if defined(CPU_ARMv7)
+#define ARM_MMU_v7		1
+#else
+#define ARM_MMU_v7		0
+#endif
+
 #define	ARM_NMMUS		(ARM_MMU_MEMC + ARM_MMU_GENERIC +	\
-				 ARM_MMU_SA1 + ARM_MMU_XSCALE)
+				 ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_v7)
 
 /*
  * Define features that may be present on a subset of CPUs
diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index 5b1d4e53879..1385cc5d9ab 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.5 2008/09/11 02:38:14 kevlo Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.6 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
 
 /*
@@ -360,7 +360,26 @@ void	armv5_ec_idcache_wbinv_all	(void);
 void	armv5_ec_idcache_wbinv_range	(vaddr_t, vsize_t);
 #endif
 
-#if defined (CPU_ARM10)
+#ifdef CPU_ARM11
+void	arm11_setttb		(u_int);
+
+void	arm11_tlb_flushID_SE	(u_int);
+void	arm11_tlb_flushI_SE	(u_int);
+
+void	arm11_context_switch	(u_int);
+
+void	arm11_setup		(char	*string);
+void	arm11_tlb_flushID	(void);
+void	arm11_tlb_flushI	(void);
+void	arm11_tlb_flushD	(void);
+void	arm11_tlb_flushD_SE	(u_int	va);
+
+void	arm11_drain_writebuf	(void);
+void	arm11_cpu_sleep		(int	mode);
+#endif
+
+
+#if defined (CPU_ARM10) || defined(CPU_ARM11)
 void	armv5_setttb			(u_int);
 
 void	armv5_icache_sync_all		(void);
@@ -380,6 +399,44 @@ extern unsigned armv5_dcache_index_max;
 extern unsigned armv5_dcache_index_inc;
 #endif
 
+#ifdef CPU_ARMv7
+void	armv7_setttb		(u_int);
+
+void	armv7_tlb_flushID_SE	(u_int);
+void	armv7_tlb_flushI_SE	(u_int);
+
+void	armv7_context_switch	(u_int);
+void	armv7_context_switch	(u_int);
+
+void	armv7_setup		(char *string);
+void	armv7_tlb_flushID	(void);
+void	armv7_tlb_flushI	(void);
+void	armv7_tlb_flushD	(void);
+void	armv7_tlb_flushD_SE	(u_int va);
+
+void	armv7_drain_writebuf	(void);
+void	armv7_cpu_sleep		(int mode);
+
+void	armv7_setttb			(u_int);
+
+void	armv7_icache_sync_all		(void);
+void	armv7_icache_sync_range		(vaddr_t, vsize_t);
+
+void	armv7_dcache_wbinv_all		(void);
+void	armv7_dcache_wbinv_range	(vaddr_t, vsize_t);
+void	armv7_dcache_inv_range		(vaddr_t, vsize_t);
+void	armv7_dcache_wb_range		(vaddr_t, vsize_t);
+
+void	armv7_idcache_wbinv_all		(void);
+void	armv7_idcache_wbinv_range	(vaddr_t, vsize_t);
+
+extern unsigned armv7_dcache_sets_max;
+extern unsigned armv7_dcache_sets_inc;
+extern unsigned armv7_dcache_index_max;
+extern unsigned armv7_dcache_index_inc;
+#endif
+
+
 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
     defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
@@ -459,10 +516,10 @@ __set_cpsr_c(u_int bic, u_int eor)
 	u_int32_t	tmp, ret;
 
 	__asm __volatile(
-		"mrs     %0, cpsr\n"	/* Get the CPSR */
+		"mrs	%0, cpsr\n"	/* Get the CPSR */
 		"bic	 %1, %0, %2\n"	/* Clear bits */
 		"eor	 %1, %1, %3\n"	/* XOR bits */
-		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
+		"msr	cpsr_c, %1\n"	/* Set the control field of CPSR */
 	: "=&r" (ret), "=&r" (tmp)
 	: "r" (bic), "r" (eor));
 
diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h
index 2e5b139324d..3d891b182f2 100644
--- a/sys/arch/arm/include/pmap.h
+++ b/sys/arch/arm/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.9 2007/10/10 15:53:51 art Exp $	*/
+/*	$OpenBSD: pmap.h,v 1.10 2009/05/08 02:57:32 drahn Exp $	*/
 /*	$NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $	*/
 
 /*
@@ -273,6 +273,9 @@ void	pmap_postinit(void);
 
 void	vector_page_setprot(int);
 
+/* XXX */
+void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable);
+
 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
 
@@ -400,6 +403,12 @@ void	pmap_pte_init_arm9(void);
 #if defined(CPU_ARM10)
 void	pmap_pte_init_arm10(void);
 #endif /* CPU_ARM10 */
+#if defined(CPU_ARM11)
+void	pmap_pte_init_arm11(void);
+#endif /* CPU_ARM11 */
+#if defined(CPU_ARMv7)
+void	pmap_pte_init_armv7(void);
+#endif /* CPU_ARMv7 */
 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
 
 #if ARM_MMU_SA1 == 1