Sync "Structured Extended Feature Flags" cpuid bits with

the August 2012 revision of
"Intel Architecture Instruction Set Extensions Programming Reference".

Correct definitions of EREP and INVPCID, rename EREP to ERMS to
match Intel's docs.  Add some more Haswell feature bits.

4 files changed, 44 insertions, 10 deletions

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index a90f69d77c9..c597bb099f7 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: identcpu.c,v 1.40 2012/10/09 04:40:36 jsg Exp $	*/
+/*	$OpenBSD: identcpu.c,v 1.41 2012/10/09 09:16:09 jsg Exp $	*/
 /*	$NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $	*/
 
 /*
@@ -146,9 +146,17 @@ const struct {
 	{ CPUIDECX_TOPEXT,	"TOPEXT" },
 }, cpu_seff0_ebxfeatures[] = {
 	{ SEFF0EBX_FSGSBASE,	"FSGSBASE" },
+	{ SEFF0EBX_BMI1,	"BMI1" },
+	{ SEFF0EBX_HLE,		"HLE" },
+	{ SEFF0EBX_AVX2,	"AVX2" },
 	{ SEFF0EBX_SMEP,	"SMEP" },
-	{ SEFF0EBX_EREP,	"EREP" },
+	{ SEFF0EBX_BMI2,	"BMI2" },
+	{ SEFF0EBX_ERMS,	"ERMS" },
 	{ SEFF0EBX_INVPCID,	"INVPCID" },
+	{ SEFF0EBX_RTM,		"RTM" },
+	{ SEFF0EBX_RDSEED,	"RDSEED" },
+	{ SEFF0EBX_ADX,		"ADX" },
+	{ SEFF0EBX_SMAP,	"SMAP" },
 };
 
 int
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index a53b47142e5..142fbbcbd57 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.22 2012/08/24 02:49:23 guenther Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.23 2012/10/09 09:16:09 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -89,6 +89,7 @@
 #define	CR4_PCIDE	0x00020000	/* enable process-context IDs */
 #define	CR4_OSXSAVE	0x00040000	/* enable XSAVE and extended states */
 #define	CR4_SMEP	0x00100000	/* supervisor mode exec protection */
+#define	CR4_SMAP	0x00200000	/* supervisor mode access prevention */
 
 /*
  * CPUID "features" bits (CPUID function 0x1):
@@ -164,9 +165,17 @@
  */
 
 #define	SEFF0EBX_FSGSBASE	0x00000001 /* {RD,WR}[FG]SBASE instructions */
+#define	SEFF0EBX_BMI1		0x00000008 /* advanced bit manipulation */
+#define	SEFF0EBX_HLE		0x00000010 /* Hardware Lock Elision */
+#define	SEFF0EBX_AVX2		0x00000020 /* Advanced Vector Extensions 2 */
 #define	SEFF0EBX_SMEP		0x00000080 /* Supervisor mode exec protection */
-#define	SEFF0EBX_EREP		0x00000100 /* Enhanced REP MOVSB/STOSB */
-#define	SEFF0EBX_INVPCID	0x00000200 /* INVPCID instruction */
+#define	SEFF0EBX_BMI2		0x00000100 /* advanced bit manipulation */
+#define	SEFF0EBX_ERMS		0x00000200 /* Enhanced REP MOVSB/STOSB */
+#define	SEFF0EBX_INVPCID	0x00000400 /* INVPCID instruction */
+#define	SEFF0EBX_RTM		0x00000800 /* Restricted Transactional Memory */
+#define	SEFF0EBX_RDSEED		0x00040000 /* RDSEED instruction */
+#define	SEFF0EBX_ADX		0x00080000 /* ADCX/ADOX instructions */
+#define	SEFF0EBX_SMAP		0x00100000 /* Supervisor mode access prevent */
 
 /*
  * CPUID "extended features" bits (CPUID function 0x80000001):
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 726ba4b711a..2c11ebedf5a 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.514 2012/10/09 04:40:36 jsg Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.515 2012/10/09 09:16:09 jsg Exp $	*/
 /*	$NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $	*/
 
 /*-
@@ -1054,9 +1054,17 @@ const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = {
 
 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = {
 	{ SEFF0EBX_FSGSBASE,	"FSGSBASE" },
+	{ SEFF0EBX_BMI1,	"BMI1" },
+	{ SEFF0EBX_HLE,		"HLE" },
+	{ SEFF0EBX_AVX2,	"AVX2" },
 	{ SEFF0EBX_SMEP,	"SMEP" },
-	{ SEFF0EBX_EREP,	"EREP" },
+	{ SEFF0EBX_BMI2,	"BMI2" },
+	{ SEFF0EBX_ERMS,	"ERMS" },
 	{ SEFF0EBX_INVPCID,	"INVPCID" },
+	{ SEFF0EBX_RTM,		"RTM" },
+	{ SEFF0EBX_RDSEED,	"RDSEED" },
+	{ SEFF0EBX_ADX,		"ADX" },
+	{ SEFF0EBX_SMAP,	"SMAP" },
 };
 
 void
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index db11cdf31ef..d693449f881 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.42 2012/08/24 02:49:23 guenther Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.43 2012/10/09 09:16:09 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -88,6 +88,7 @@
 #define	CR4_PCIDE	0x00020000	/* enable process-context IDs */
 #define	CR4_OSXSAVE	0x00040000	/* enable XSAVE and extended states */
 #define	CR4_SMEP	0x00100000	/* supervisor mode exec protection */
+#define	CR4_SMAP	0x00200000	/* supervisor mode access prevention */
 
 /*
  * CPUID "features" bits (CPUID function 0x1):
@@ -163,9 +164,17 @@
  */
 
 #define	SEFF0EBX_FSGSBASE	0x00000001 /* {RD,WR}[FG]SBASE instructions */
+#define	SEFF0EBX_BMI1		0x00000008 /* advanced bit manipulation */
+#define	SEFF0EBX_HLE		0x00000010 /* Hardware Lock Elision */
+#define	SEFF0EBX_AVX2		0x00000020 /* Advanced Vector Extensions 2 */
 #define	SEFF0EBX_SMEP		0x00000080 /* Supervisor mode exec protection */
-#define	SEFF0EBX_EREP		0x00000100 /* Enhanced REP MOVSB/STOSB */
-#define	SEFF0EBX_INVPCID	0x00000200 /* INVPCID instruction */
+#define	SEFF0EBX_BMI2		0x00000100 /* advanced bit manipulation */
+#define	SEFF0EBX_ERMS		0x00000200 /* Enhanced REP MOVSB/STOSB */
+#define	SEFF0EBX_INVPCID	0x00000400 /* INVPCID instruction */
+#define	SEFF0EBX_RTM		0x00000800 /* Restricted Transactional Memory */
+#define	SEFF0EBX_RDSEED		0x00040000 /* RDSEED instruction */
+#define	SEFF0EBX_ADX		0x00080000 /* ADCX/ADOX instructions */
+#define	SEFF0EBX_SMAP		0x00100000 /* Supervisor mode access prevent */
 
 /*
  * CPUID "extended features" bits (CPUID function 0x80000001):