Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL.

Even with the latest microcode this is not set on all CPUs with TSX, but
is set on CPUs which don't need MDS mitigations.

MDS mitigations also mitigate TSX Asynchronous Abort (TAA) but aren't
done if the CPU claims to not be affected by MDS (MDS_NO).
According to "Deep Dive: Intel Transactional Synchronization Extensions
(Intel TSX) Asynchronous Abort" CPUs requiring additional mitigations
for this are:
06-8e-0c	Whiskey Lake (ULT refresh)
06-55-0{6,7}	2nd Gen Xeon Scalable Processors based on Cascade Lake
06-9e-0d	Coffee Lake R

Currently TSX is disabled unconditionally when possible even if TAA_NO
is set.

We don't currently do MDS mitigations on i386.  Attempt to disable TSX
regardless to match amd64.

4 files changed, 36 insertions, 4 deletions

diff --git a/sys/arch/i386/i386/acpi_machdep.c b/sys/arch/i386/i386/acpi_machdep.c
index 2fd866d968c..0e6d32de972 100644
--- a/sys/arch/i386/i386/acpi_machdep.c
+++ b/sys/arch/i386/i386/acpi_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: acpi_machdep.c,v 1.71 2019/08/27 22:39:53 deraadt Exp $	*/
+/*	$OpenBSD: acpi_machdep.c,v 1.72 2019/12/20 07:55:30 jsg Exp $	*/
 /*
  * Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com>
  *
@@ -446,6 +446,7 @@ acpi_resume_cpu(struct acpi_softc *sc, int state)
 
 	cpu_init(&cpu_info_primary);
 	cpu_ucode_apply(&cpu_info_primary);
+	cpu_tsx_disable(&cpu_info_primary);
 	
 	/* Re-initialise memory range handling on BSP */
 	if (mem_range_softc.mr_op != NULL)
diff --git a/sys/arch/i386/i386/cpu.c b/sys/arch/i386/i386/cpu.c
index ea81df66231..b31a431c594 100644
--- a/sys/arch/i386/i386/cpu.c
+++ b/sys/arch/i386/i386/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.97 2019/01/18 01:34:50 pd Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.98 2019/12/20 07:55:30 jsg Exp $	*/
 /* $NetBSD: cpu.c,v 1.1.2.7 2000/06/26 02:04:05 sommerfeld Exp $ */
 
 /*-
@@ -316,6 +316,7 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
 #ifndef SMALL_KERNEL
 		cpu_ucode_apply(ci);
 #endif
+		cpu_tsx_disable(ci);
 		identifycpu(ci);
 #ifdef MTRR
 		mem_range_attach();
@@ -330,6 +331,7 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
 #ifndef SMALL_KERNEL
 		cpu_ucode_apply(ci);
 #endif
+		cpu_tsx_disable(ci);
 		identifycpu(ci);
 #ifdef MTRR
 		mem_range_attach();
@@ -361,6 +363,7 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
 #ifndef SMALL_KERNEL
 		cpu_ucode_apply(ci);
 #endif
+		cpu_tsx_disable(ci);
 		identifycpu(ci);
 		sched_init_cpu(ci);
 		ci->ci_next = cpu_info_list->ci_next;
@@ -467,6 +470,26 @@ cpu_init(struct cpu_info *ci)
 }
 
 void
+cpu_tsx_disable(struct cpu_info *ci)
+{
+	uint64_t msr;
+	uint32_t dummy, sefflags_edx;
+
+	/* this runs before identifycpu() populates ci_feature_sefflags_edx */
+	if (cpuid_level >= 0x07)
+		CPUID_LEAF(0x7, 0, dummy, dummy, dummy, sefflags_edx);
+	if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
+	    (sefflags_edx & SEFF0EDX_ARCH_CAP)) {
+		msr = rdmsr(MSR_ARCH_CAPABILITIES);
+		if (msr & ARCH_CAPABILITIES_TSX_CTRL) {
+			msr = rdmsr(MSR_TSX_CTRL);
+			msr |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_TSX_CPUID_CLEAR;
+			wrmsr(MSR_TSX_CTRL, msr);
+		}
+	}
+}
+
+void
 patinit(struct cpu_info *ci)
 {
 	extern int	pmap_pg_wc;
diff --git a/sys/arch/i386/include/cpu.h b/sys/arch/i386/include/cpu.h
index 5c53af46020..8f8d0535687 100644
--- a/sys/arch/i386/include/cpu.h
+++ b/sys/arch/i386/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.167 2019/01/18 01:34:50 pd Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.168 2019/12/20 07:55:30 jsg Exp $	*/
 /*	$NetBSD: cpu.h,v 1.35 1996/05/05 19:29:26 christos Exp $	*/
 
 /*-
@@ -364,6 +364,7 @@ extern int cpu_apmi_edx;
 extern u_int cpu_mwait_size;
 extern u_int cpu_mwait_states;
 extern void cpu_update_nmi_cr3(vaddr_t);
+extern void cpu_tsx_disable(struct cpu_info *);
 
 /* machdep.c */
 extern int cpu_apmhalt;
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 8b1e398a93e..c100f75fe4b 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.74 2019/06/14 18:13:55 kettenis Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.75 2019/12/20 07:55:30 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -365,6 +365,10 @@
 #define ARCH_CAPABILITIES_RSBA		(1 << 2)	/* RSB Alternate */
 #define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY	(1 << 3)
 #define ARCH_CAPABILITIES_SSB_NO	(1 << 4)	/* Spec St Byp safe */
+#define ARCH_CAPABILITIES_MDS_NO	(1 << 5) /* microarch data-sampling */
+#define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO	(1 << 6) /* PS MCE safe */
+#define ARCH_CAPABILITIES_TSX_CTRL	(1 << 7)	/* has TSX_CTRL MSR */
+#define ARCH_CAPABILITIES_TAA_NO	(1 << 8)	/* TSX AA safe */
 #define MSR_FLUSH_CMD		0x10b
 #define FLUSH_CMD_L1D_FLUSH	(1ULL << 0)
 #define	MSR_BBL_CR_ADDR		0x116	/* PII+ only */
@@ -373,6 +377,9 @@
 #define	MSR_BBL_CR_TRIG		0x11a	/* PII+ only */
 #define	MSR_BBL_CR_BUSY		0x11b	/* PII+ only */
 #define	MSR_BBL_CR_CTR3		0x11e	/* PII+ only */
+#define	MSR_TSX_CTRL		0x122
+#define TSX_CTRL_RTM_DISABLE		(1ULL << 0)
+#define TSX_CTRL_TSX_CPUID_CLEAR	(1ULL << 1)
 #define MSR_SYSENTER_CS		0x174
 #define MSR_SYSENTER_ESP	0x175
 #define MSR_SYSENTER_EIP	0x176