Probe the PCI bus.

6 files changed, 547 insertions, 2 deletions

diff --git a/sys/arch/powerpc64/conf/GENERIC b/sys/arch/powerpc64/conf/GENERIC
index 97af77c8ead..c60c134dbc6 100644
--- a/sys/arch/powerpc64/conf/GENERIC
+++ b/sys/arch/powerpc64/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.2 2020/06/07 13:17:24 kettenis Exp $
+#	$OpenBSD: GENERIC,v 1.3 2020/06/07 16:14:47 kettenis Exp $
 #
 # For further information on compiling OpenBSD kernels, see the config(8)
 # man page.
@@ -13,7 +13,13 @@ machine		powerpc64
 include		"../../../conf/GENERIC"
 maxusers	80
 
+option		PCIVERBOSE
+
 config		bsd	swap generic
 
 mainbus0	at root
 cpu0		at mainbus?
+phb*		at fdt?
+pci*		at phb?
+ppb*		at pci?
+pci*		at ppb?
diff --git a/sys/arch/powerpc64/conf/files.powerpc64 b/sys/arch/powerpc64/conf/files.powerpc64
index 4aaa43e5dc7..27b61d7b545 100644
--- a/sys/arch/powerpc64/conf/files.powerpc64
+++ b/sys/arch/powerpc64/conf/files.powerpc64
@@ -1,4 +1,4 @@
-# $OpenBSD: files.powerpc64,v 1.5 2020/06/07 13:17:24 kettenis Exp $
+# $OpenBSD: files.powerpc64,v 1.6 2020/06/07 16:14:47 kettenis Exp $
 
 maxpartitions	16
 maxusers	2 8 128
@@ -23,6 +23,8 @@ file	arch/powerpc64/powerpc64/trap.c
 file	arch/powerpc64/powerpc64/trap_subr.S
 file	arch/powerpc64/powerpc64/vm_machdep.c
 
+file	arch/powerpc64/dev/pci_machdep.c
+
 file	netinet/in_cksum.c
 file	netinet/in4_cksum.c
 
@@ -41,3 +43,11 @@ attach  cpu at mainbus
 include "dev/ofw/files.ofw"
 
 include "scsi/files.scsi"
+
+# MII and PCI
+include "dev/mii/files.mii"
+include "dev/pci/files.pci"
+
+device	phb: pcibus
+attach	phb at fdt
+file	arch/powerpc64/dev/phb.c		phb
diff --git a/sys/arch/powerpc64/dev/pci_machdep.c b/sys/arch/powerpc64/dev/pci_machdep.c
new file mode 100644
index 00000000000..f1d3c4b1286
--- /dev/null
+++ b/sys/arch/powerpc64/dev/pci_machdep.c
@@ -0,0 +1,168 @@
+/*	$OpenBSD: pci_machdep.c,v 1.1 2020/06/07 16:14:47 kettenis Exp $	*/
+
+/*
+ * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <machine/bus.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+void
+pci_msi_enable(pci_chipset_tag_t pc, pcitag_t tag,
+    bus_addr_t addr, uint32_t data)
+{
+	pcireg_t reg;
+	int off;
+
+	if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, &reg) == 0)
+		panic("%s: no msi capability", __func__);
+
+	if (reg & PCI_MSI_MC_C64) {
+		pci_conf_write(pc, tag, off + PCI_MSI_MA, addr);
+		pci_conf_write(pc, tag, off + PCI_MSI_MAU32, addr >> 32);
+		pci_conf_write(pc, tag, off + PCI_MSI_MD64, data);
+	} else {
+		pci_conf_write(pc, tag, off + PCI_MSI_MA, addr);
+		pci_conf_write(pc, tag, off + PCI_MSI_MD32, data);
+	}
+	pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
+}
+
+#ifdef notyet
+
+int
+pci_msix_table_map(pci_chipset_tag_t pc, pcitag_t tag,
+    bus_space_tag_t memt, bus_space_handle_t *memh)
+{
+	bus_addr_t base;
+	pcireg_t reg, table, type;
+	int bir, offset;
+	int off, tblsz;
+
+	if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, &reg) == 0)
+		panic("%s: no msix capability", __func__);
+
+	table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE);
+	bir = (table & PCI_MSIX_TABLE_BIR);
+	offset = (table & PCI_MSIX_TABLE_OFF);
+	tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
+
+	bir = PCI_MAPREG_START + bir * 4;
+	type = pci_mapreg_type(pc, tag, bir);
+	if (pci_mapreg_info(pc, tag, bir, type, &base, NULL, NULL) ||
+	    bus_space_map(memt, base + offset, tblsz * 16, 0, memh))
+		return -1;
+
+	return 0;
+}
+
+void
+pci_msix_table_unmap(pci_chipset_tag_t pc, pcitag_t tag,
+    bus_space_tag_t memt, bus_space_handle_t memh)
+{
+	pcireg_t reg;
+	int tblsz;
+
+	if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, &reg) == 0)
+		panic("%s: no msix capability", __func__);
+
+	tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
+	bus_space_unmap(memt, memh, tblsz * 16);
+}
+
+void
+pci_msix_enable(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt,
+    int vec, bus_addr_t addr, uint32_t data)
+{
+	bus_space_handle_t memh;
+	pcireg_t reg;
+	uint32_t ctrl;
+	int off;
+
+	if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, &reg) == 0)
+		panic("%s: no msix capability", __func__);
+
+	KASSERT(vec <= PCI_MSIX_MC_TBLSZ(reg));
+
+	if (pci_msix_table_map(pc, tag, memt, &memh))
+		panic("%s: cannot map registers", __func__);
+
+	bus_space_write_4(memt, memh, PCI_MSIX_MA(vec), addr);
+	bus_space_write_4(memt, memh, PCI_MSIX_MAU32(vec), addr >> 32);
+	bus_space_write_4(memt, memh, PCI_MSIX_MD(vec), data);
+	bus_space_barrier(memt, memh, PCI_MSIX_MA(vec), 16,
+	    BUS_SPACE_BARRIER_WRITE);
+	ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(vec));
+	bus_space_write_4(memt, memh, PCI_MSIX_VC(vec),
+	    ctrl & ~PCI_MSIX_VC_MASK);
+
+	pci_msix_table_unmap(pc, tag, memt, memh);
+
+	pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
+}
+
+#endif
+
+int
+_pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
+{
+	pci_chipset_tag_t pc = pa->pa_pc;
+	pcitag_t tag = pa->pa_tag;
+
+	if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 ||
+	    pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0)
+		return -1;
+
+	ihp->ih_pc = pa->pa_pc;
+	ihp->ih_tag = pa->pa_tag;
+	ihp->ih_type = PCI_MSI;
+
+	return 0;
+}
+
+int
+_pci_intr_map_msix(struct pci_attach_args *pa, int vec,
+    pci_intr_handle_t *ihp)
+{
+	pci_chipset_tag_t pc = pa->pa_pc;
+	pcitag_t tag = pa->pa_tag;
+	pcireg_t reg, table, type;
+	int bir, off;
+
+	if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 ||
+	    pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, &reg) == 0)
+		return -1;
+
+	if (vec > PCI_MSIX_MC_TBLSZ(reg))
+		return -1;
+
+	table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE);
+	bir = PCI_MAPREG_START + (table & PCI_MSIX_TABLE_BIR) * 4;
+	type = pci_mapreg_type(pc, tag, bir);
+	if (pci_mapreg_assign(pa, bir, type, NULL, NULL))
+		return -1;
+
+	ihp->ih_pc = pa->pa_pc;
+	ihp->ih_tag = pa->pa_tag;
+	ihp->ih_intrpin = vec;
+	ihp->ih_type = PCI_MSIX;
+
+	return 0;
+}
diff --git a/sys/arch/powerpc64/dev/phb.c b/sys/arch/powerpc64/dev/phb.c
new file mode 100644
index 00000000000..d9aef68bc5a
--- /dev/null
+++ b/sys/arch/powerpc64/dev/phb.c
@@ -0,0 +1,228 @@
+/*	$OpenBSD: phb.c,v 1.1 2020/06/07 16:14:47 kettenis Exp $	*/
+/*
+ * Copyright (c) 2020 Mark Kettenis <kettenis@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+#include <machine/opal.h>
+
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/fdt.h>
+
+struct phb_softc {
+	struct device		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+
+	uint64_t		sc_phb_id;
+
+	struct ppc64_pci_chipset sc_pc;
+	int			sc_bus;
+};
+
+int	phb_match(struct device *, void *, void *);
+void	phb_attach(struct device *, struct device *, void *);
+
+struct cfattach	phb_ca = {
+	sizeof (struct phb_softc), phb_match, phb_attach
+};
+
+struct cfdriver phb_cd = {
+	NULL, "phb", DV_DULL
+};
+
+void	phb_attach_hook(struct device *, struct device *,
+	    struct pcibus_attach_args *);
+int	phb_bus_maxdevs(void *, int);
+pcitag_t phb_make_tag(void *, int, int, int);
+void	phb_decompose_tag(void *, pcitag_t, int *, int *, int *);
+int	phb_conf_size(void *, pcitag_t);
+pcireg_t phb_conf_read(void *, pcitag_t, int);
+void	phb_conf_write(void *, pcitag_t, int, pcireg_t);
+
+int	phb_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
+const char *phb_intr_string(void *, pci_intr_handle_t);
+void	*phb_intr_establish(void *, pci_intr_handle_t, int,
+	    int (*)(void *), void *, char *);
+void	phb_intr_disestablish(void *, void *);
+
+int
+phb_match(struct device *parent, void *match, void *aux)
+{
+	struct fdt_attach_args *faa = aux;
+
+	return OF_is_compatible(faa->fa_node, "ibm,ioda3-phb");
+}
+
+void
+phb_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct phb_softc *sc = (struct phb_softc *)self;
+	struct fdt_attach_args *faa = aux;
+	struct pcibus_attach_args pba;
+
+	if (faa->fa_nreg < 1) {
+		printf(": no registers\n");
+		return;
+	}
+
+	sc->sc_phb_id = OF_getpropint64(faa->fa_node, "ibm,opal-phbid", 0);
+
+	printf("\n");
+
+	sc->sc_pc.pc_conf_v = sc;
+	sc->sc_pc.pc_attach_hook = phb_attach_hook;
+	sc->sc_pc.pc_bus_maxdevs = phb_bus_maxdevs;
+	sc->sc_pc.pc_make_tag = phb_make_tag;
+	sc->sc_pc.pc_decompose_tag = phb_decompose_tag;
+	sc->sc_pc.pc_conf_size = phb_conf_size;
+	sc->sc_pc.pc_conf_read = phb_conf_read;
+	sc->sc_pc.pc_conf_write = phb_conf_write;
+
+	sc->sc_pc.pc_intr_v = sc;
+	sc->sc_pc.pc_intr_map = phb_intr_map;
+	sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi;
+	sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix;
+	sc->sc_pc.pc_intr_string = phb_intr_string;
+	sc->sc_pc.pc_intr_establish = phb_intr_establish;
+	sc->sc_pc.pc_intr_disestablish = phb_intr_disestablish;
+
+	memset(&pba, 0, sizeof(pba));
+	pba.pba_busname = "pci";
+	pba.pba_iot = faa->fa_iot;
+	pba.pba_memt = faa->fa_iot;
+	pba.pba_dmat = faa->fa_dmat;
+	pba.pba_pc = &sc->sc_pc;
+	pba.pba_domain = pci_ndomains++;
+	pba.pba_bus = sc->sc_bus;
+	pba.pba_flags |= PCI_FLAGS_MSI_ENABLED;
+
+	config_found(self, &pba, NULL);
+}
+
+void
+phb_attach_hook(struct device *parent, struct device *self,
+    struct pcibus_attach_args *pba)
+{
+}
+
+int
+phb_bus_maxdevs(void *v, int bus)
+{
+	struct phb_softc *sc = v;
+
+	if (bus == sc->sc_bus || bus == sc->sc_bus + 1)
+		return 1;
+	return 32;
+}
+
+pcitag_t
+phb_make_tag(void *v, int bus, int device, int function)
+{
+	/* Return OPAL bus_dev_func. */
+	return ((bus << 8) | (device << 3) | (function << 0));
+}
+
+void
+phb_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
+{
+	if (bp != NULL)
+		*bp = (tag >> 8) & 0xff;
+	if (dp != NULL)
+		*dp = (tag >> 3) & 0x1f;
+	if (fp != NULL)
+		*fp = (tag >> 0) & 0x7;
+}
+
+int
+phb_conf_size(void *v, pcitag_t tag)
+{
+	return PCIE_CONFIG_SPACE_SIZE;
+}
+
+pcireg_t
+phb_conf_read(void *v, pcitag_t tag, int reg)
+{
+	struct phb_softc *sc = v;
+	int64_t error;
+	uint32_t data;
+
+	error = opal_pci_config_read_word(sc->sc_phb_id, tag, reg, &data);
+	if (error == OPAL_SUCCESS)
+		return data;
+
+	return 0xffffffff;
+}
+
+void
+phb_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
+{
+	struct phb_softc *sc = v;
+
+	opal_pci_config_write_word(sc->sc_phb_id, tag, reg, data);
+}
+
+int
+phb_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
+{
+	int pin = pa->pa_rawintrpin;
+
+	if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX)
+		return -1;
+
+	if (pa->pa_tag == 0)
+		return -1;
+
+	ihp->ih_pc = pa->pa_pc;
+	ihp->ih_tag = pa->pa_intrtag;
+	ihp->ih_intrpin = pa->pa_intrpin;
+	ihp->ih_type = PCI_INTX;
+
+	return 0;
+}
+
+const char *
+phb_intr_string(void *v, pci_intr_handle_t ih)
+{
+	switch (ih.ih_type) {
+	case PCI_MSI:
+		return "msi";
+	case PCI_MSIX:
+		return "msix";
+	}
+
+	return "intx";
+}
+
+void *
+phb_intr_establish(void *v, pci_intr_handle_t ih, int level,
+    int (*func)(void *), void *arg, char *name)
+{
+	return NULL;
+}
+
+void
+phb_intr_disestablish(void *v, void *cookie)
+{
+}
diff --git a/sys/arch/powerpc64/include/bus.h b/sys/arch/powerpc64/include/bus.h
index abd61063a5f..6c41f393d16 100644
--- a/sys/arch/powerpc64/include/bus.h
+++ b/sys/arch/powerpc64/include/bus.h
@@ -7,6 +7,9 @@ typedef u_long bus_size_t;
 typedef u_long bus_space_handle_t;
 typedef struct bus_space *bus_space_tag_t;
 
+#define BUS_SPACE_MAP_PREFETCHABLE	0x01
+
+#define bus_space_map(t, o, s, c, p)	ENOMEM
 #define bus_space_write_4(t, h, o, v)
 #define bus_space_read_4(t, h, o) 0xffffffff
 
diff --git a/sys/arch/powerpc64/include/pci_machdep.h b/sys/arch/powerpc64/include/pci_machdep.h
new file mode 100644
index 00000000000..f97e3ae5ef9
--- /dev/null
+++ b/sys/arch/powerpc64/include/pci_machdep.h
@@ -0,0 +1,130 @@
+/*	$OpenBSD: pci_machdep.h,v 1.1 2020/06/07 16:14:47 kettenis Exp $ */
+
+/*
+ * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+typedef struct ppc64_pci_chipset *pci_chipset_tag_t;
+typedef uint64_t pcitag_t;
+
+/* Supported interrupt types. */
+#define PCI_NONE		0
+#define PCI_INTX		1
+#define PCI_MSI			2
+#define PCI_MSIX		3
+
+typedef struct {
+	pci_chipset_tag_t	ih_pc;
+	pcitag_t		ih_tag;
+	int			ih_intrpin;
+	int			ih_type;
+} pci_intr_handle_t;
+
+struct pci_attach_args;
+
+/*
+ * powerpc64-specific PCI structure and type definitions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ */
+struct ppc64_pci_chipset {
+	void		*pc_conf_v;
+	void		(*pc_attach_hook)(struct device *,
+			    struct device *, struct pcibus_attach_args *);
+	int		(*pc_bus_maxdevs)(void *, int);
+	pcitag_t	(*pc_make_tag)(void *, int, int, int);
+	void		(*pc_decompose_tag)(void *, pcitag_t, int *,
+			    int *, int *);
+	int		(*pc_conf_size)(void *, pcitag_t);
+	pcireg_t	(*pc_conf_read)(void *, pcitag_t, int);
+	void		(*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
+
+	void		*pc_intr_v;
+	int		(*pc_intr_map)(struct pci_attach_args *,
+			    pci_intr_handle_t *);
+	int		(*pc_intr_map_msi)(struct pci_attach_args *,
+			    pci_intr_handle_t *);
+	int		(*pc_intr_map_msix)(struct pci_attach_args *,
+			    int, pci_intr_handle_t *);
+	const char	*(*pc_intr_string)(void *, pci_intr_handle_t);
+	void		*(*pc_intr_establish)(void *, pci_intr_handle_t,
+			    int, int (*)(void *), void *, char *);
+	void		(*pc_intr_disestablish)(void *, void *);
+};
+
+/*
+ * Functions provided to machine-independent PCI code.
+ */
+#define	pci_attach_hook(p, s, pba)					\
+    (*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
+#define	pci_bus_maxdevs(c, b)						\
+    (*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
+#define	pci_make_tag(c, b, d, f)					\
+    (*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
+#define	pci_decompose_tag(c, t, bp, dp, fp)				\
+    (*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
+#define	pci_conf_size(c, t)						\
+    (*(c)->pc_conf_size)((c)->pc_conf_v, (t))
+#define	pci_conf_read(c, t, r)						\
+    (*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
+#define	pci_conf_write(c, t, r, v)					\
+    (*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
+#define	pci_intr_map(c, ihp)						\
+    (*(c)->pa_pc->pc_intr_map)((c), (ihp))
+#define	pci_intr_map_msi(c, ihp)					\
+    (*(c)->pa_pc->pc_intr_map_msi)((c), (ihp))
+#define	pci_intr_map_msix(c, vec, ihp)					\
+    (*(c)->pa_pc->pc_intr_map_msix)((c), (vec), (ihp))
+#define	pci_intr_string(c, ih)						\
+    (*(c)->pc_intr_string)((c)->pc_intr_v, (ih))
+#define	pci_intr_establish(c, ih, l, h, a, nm)				\
+    (*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (h), (a), (nm))
+#define	pci_intr_disestablish(c, iv)					\
+    (*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
+#define	pci_probe_device_hook(c, a)	(0)
+
+#define	pci_min_powerstate(c, t)	(PCI_PMCSR_STATE_D3)
+#define	pci_set_powerstate_md(c, t, s, p)
+
+#define	pci_dev_postattach(a, b)
+
+void	pci_mcfg_init(bus_space_tag_t, bus_addr_t, int, int, int);
+pci_chipset_tag_t pci_lookup_segment(int);
+
+void	pci_msi_enable(pci_chipset_tag_t, pcitag_t, bus_addr_t, uint32_t);
+void	pci_msix_enable(pci_chipset_tag_t, pcitag_t, bus_space_tag_t,
+	    int, bus_addr_t, uint32_t);
+int	_pci_intr_map_msi(struct pci_attach_args *, pci_intr_handle_t *);
+int	_pci_intr_map_msix(struct pci_attach_args *, int, pci_intr_handle_t *);
+
+#ifdef notyet
+
+#define __HAVE_PCI_MSIX
+
+int	pci_msix_table_map(pci_chipset_tag_t, pcitag_t,
+	    bus_space_tag_t, bus_space_handle_t *);
+void	pci_msix_table_unmap(pci_chipset_tag_t, pcitag_t,
+	    bus_space_tag_t, bus_space_handle_t);
+
+#endif