add MTRR support from FreeBSD

4 files changed, 88 insertions, 4 deletions

diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC
index 81296b25e39..1feaafaf4de 100644
--- a/sys/arch/i386/conf/GENERIC
+++ b/sys/arch/i386/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.137 1999/11/14 11:53:00 ho Exp $
+#	$OpenBSD: GENERIC,v 1.138 1999/11/20 11:18:58 matthieu Exp $
 #	$NetBSD: GENERIC,v 1.48 1996/05/20 18:17:23 mrg Exp $
 #
 #	GENERIC -- everything that's currently supported
@@ -315,6 +315,7 @@ joy*	at isapnp?
 #aeon*	at pci? dev ? function ?		# Aeon crypto card
 
 pseudo-device	pctr		1
+pseudo-device	mtrr		1	# Memory range attributes control
 pseudo-device	sequencer	1
 #pseudo-device	raid		4	# RAIDframe disk driver
 
diff --git a/sys/arch/i386/conf/files.i386 b/sys/arch/i386/conf/files.i386
index e561c290bf7..85379746a39 100644
--- a/sys/arch/i386/conf/files.i386
+++ b/sys/arch/i386/conf/files.i386
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.i386,v 1.60 1999/11/08 15:36:08 mickey Exp $
+#	$OpenBSD: files.i386,v 1.61 1999/11/20 11:18:59 matthieu Exp $
 #	$NetBSD: files.i386,v 1.73 1996/05/07 00:58:36 thorpej Exp $
 #
 # new style config file for i386 architecture
@@ -24,6 +24,8 @@ file	arch/i386/i386/ipx_cksum.c	ipx
 file	arch/i386/i386/machdep.c
 file	arch/i386/i386/math_emulate.c	math_emulate
 file	arch/i386/i386/mem.c
+file	arch/i386/i386/i686_mem.c	mtrr
+file	arch/i386/i386/k6_mem.c		mtrr
 file	arch/i386/i386/microtime.s
 file	arch/i386/i386/ns_cksum.c	ns
 file	arch/i386/i386/pmap.c
@@ -178,6 +180,9 @@ file	arch/i386/isa/ahc_isa.c		ahc_isa
 pseudo-device	pctr
 file	arch/i386/i386/pctr.c		pctr needs-flag
 
+pseudo-device	mtrr
+file 	arch/i386/i386/mtrr.c		mtrr needs-flag
+
 #
 # EISA-only drivers
 #
diff --git a/sys/arch/i386/include/cpufunc.h b/sys/arch/i386/include/cpufunc.h
index 03f70906624..c6d5110c809 100644
--- a/sys/arch/i386/include/cpufunc.h
+++ b/sys/arch/i386/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.4 1999/10/26 03:44:17 downsj Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.5 1999/11/20 11:18:59 matthieu Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.8 1994/10/27 04:15:59 cgd Exp $	*/
 
 /*
@@ -220,4 +220,26 @@ enable_intr()
 	__asm __volatile("sti");
 }
 
+static __inline void
+wbinvd(void)
+{
+        __asm __volatile("wbinvd");
+}
+
+
+static __inline void
+wrmsr(u_int msr, u_int64_t newval)
+{
+        __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
+}
+
+static __inline u_int64_t
+rdmsr(u_int msr)
+{
+        u_int64_t rv;
+
+        __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
+        return (rv);
+}
+
 #endif /* !_I386_CPUFUNC_H_ */
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index d3b8c027aff..69d56cb97de 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.7 1999/03/08 23:47:25 downsj Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.8 1999/11/20 11:18:59 matthieu Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -116,6 +116,62 @@
 #define CPUID_3DNOW	0x80000000	/* has 3DNow! instructions (AMD) */
 
 /*
+ * Model-specific registers for the i386 family
+ */
+#define MSR_P5_MC_ADDR		0x000
+#define MSR_P5_MC_TYPE		0x001
+#define MSR_APICBASE		0x01b
+#define MSR_EBL_CR_POWERON	0x02a
+#define MSR_BIOS_UPDT_TRIG	0x079
+#define MSR_BIOS_SIGN		0x08b
+#define MSR_PERFCTR0		0x0c1
+#define MSR_PERFCTR1		0x0c2
+#define MSR_MTRRcap		0x0fe
+#define MSR_MCG_CAP		0x179
+#define MSR_MCG_STATUS		0x17a
+#define MSR_MCG_CTL		0x17b
+#define MSR_EVNTSEL0		0x186
+#define MSR_EVNTSEL1		0x187
+#define MSR_DEBUGCTLMSR		0x1d9
+#define MSR_LASTBRANCHFROMIP	0x1db
+#define MSR_LASTBRANCHTOIP	0x1dc
+#define MSR_LASTINTFROMIP	0x1dd
+#define MSR_LASTINTTOIP		0x1de
+#define MSR_ROB_CR_BKUPTMPDR6	0x1e0
+#define MSR_MTRRVarBase		0x200
+#define MSR_MTRR64kBase		0x250
+#define MSR_MTRR16kBase		0x258
+#define MSR_MTRR4kBase		0x268
+#define MSR_MTRRdefType		0x2ff
+#define MSR_MC0_CTL		0x400
+#define MSR_MC0_STATUS		0x401
+#define MSR_MC0_ADDR		0x402
+#define MSR_MC0_MISC		0x403
+#define MSR_MC1_CTL		0x404
+#define MSR_MC1_STATUS		0x405
+#define MSR_MC1_ADDR		0x406
+#define MSR_MC1_MISC		0x407
+#define MSR_MC2_CTL		0x408
+#define MSR_MC2_STATUS		0x409
+#define MSR_MC2_ADDR		0x40a
+#define MSR_MC2_MISC		0x40b
+#define MSR_MC4_CTL		0x40c
+#define MSR_MC4_STATUS		0x40d
+#define MSR_MC4_ADDR		0x40e
+#define MSR_MC4_MISC		0x40f
+#define MSR_MC3_CTL		0x410
+#define MSR_MC3_STATUS		0x411
+#define MSR_MC3_ADDR		0x412
+#define MSR_MC3_MISC		0x413
+
+/*
+ * Constants related to MTRRs
+ */
+#define MTRR_N64K		8	/* numbers of fixed-size entries */
+#define MTRR_N16K		16
+#define MTRR_N4K		64
+
+/*
  * the following four 3-byte registers control the non-cacheable regions.
  * These registers must be written as three seperate bytes.
  *