make ppc_intr_(enable|disable)() inlined functions.

2 files changed, 26 insertions, 29 deletions

diff --git a/sys/arch/macppc/macppc/machdep.c b/sys/arch/macppc/macppc/machdep.c
index 24a9d461946..ac252e14dbb 100644
--- a/sys/arch/macppc/macppc/machdep.c
+++ b/sys/arch/macppc/macppc/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.51 2003/06/23 21:48:24 mickey Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.52 2003/07/02 21:23:35 drahn Exp $	*/
 /*	$NetBSD: machdep.c,v 1.4 1996/10/16 19:33:11 ws Exp $	*/
 
 /*
@@ -1063,33 +1063,6 @@ ppc_intr_setup(intr_establish_t *establish, intr_disestablish_t *disestablish)
 	intr_disestablish_func = disestablish;
 }
 
-/*
- * General functions to enable and disable interrupts
- * without having inlined assembly code in many functions,
- * should be moved into a header file for inlining the function
- * so it is faster
- */
-void
-ppc_intr_enable(int enable)
-{
-	u_int32_t emsr, dmsr;
-	if (enable != 0)  {
-		__asm__ volatile("mfmsr %0" : "=r"(emsr));
-		dmsr = emsr | PSL_EE;
-		__asm__ volatile("mtmsr %0" :: "r"(dmsr));
-	}
-}
-
-int
-ppc_intr_disable(void)
-{
-	u_int32_t emsr, dmsr;
-	__asm__ volatile("mfmsr %0" : "=r"(emsr));
-	dmsr = emsr & ~PSL_EE;
-	__asm__ volatile("mtmsr %0" :: "r"(dmsr));
-	return (emsr & PSL_EE);
-}
-
 /* BUS functions */
 int
 bus_space_map(t, bpa, size, cacheable, bshp)
diff --git a/sys/arch/powerpc/include/cpu.h b/sys/arch/powerpc/include/cpu.h
index d615387b78c..9d4e4705c61 100644
--- a/sys/arch/powerpc/include/cpu.h
+++ b/sys/arch/powerpc/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.13 2002/09/15 09:01:59 deraadt Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.14 2003/07/02 21:23:35 drahn Exp $	*/
 /*	$NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $	*/
 
 /*
@@ -100,4 +100,28 @@ invdcache(void *from, int len)
 	__asm__ __volatile__ ("sync");
 }
 
+/*
+ * General functions to enable and disable interrupts
+ * without having inlined assembly code in many functions.
+ */
+static __inline void
+ppc_intr_enable(int enable)
+{
+	u_int32_t msr;
+	if (enable != 0)  {
+		__asm__ volatile("mfmsr %0" : "=r"(msr));
+		msr |= PSL_EE;
+		__asm__ volatile("mtmsr %0" :: "r"(msr));
+	}
+}
+
+static __inline int
+ppc_intr_disable(void)
+{
+	u_int32_t emsr, dmsr;
+	__asm__ volatile("mfmsr %0" : "=r"(emsr));
+	dmsr = emsr & ~PSL_EE;
+	__asm__ volatile("mtmsr %0" :: "r"(dmsr));
+	return (emsr & PSL_EE);
+}
 #endif	/* _POWERPC_CPU_H_ */