diff options
| author | imp <imp@cvs.openbsd.org> | 1998-07-11 21:41:16 +0000 |
|---|---|---|
| committer | imp <imp@cvs.openbsd.org> | 1998-07-11 21:41:16 +0000 |
| commit | ac089744d73b9b400aef9aae55dd8cef1dd74468 (patch) | |
| tree | 7683af40802577cc62cf92ef9196cc2b2f14e5f5 /sys/arch | |
| parent | 8b7c048e3565e63dc40942f787048c8f4d38504d (diff) | |
Add detection of the Vr41xx.
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/mips/include/cpu.h | 4 | ||||
| -rw-r--r-- | sys/arch/mips/mips/cpu.c | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/sys/arch/mips/include/cpu.h b/sys/arch/mips/include/cpu.h index df86d6aaca0..385ea9f4451 100644 --- a/sys/arch/mips/include/cpu.h +++ b/sys/arch/mips/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.2 1998/03/16 09:03:04 pefo Exp $ */ +/* $OpenBSD: cpu.h,v 1.3 1998/07/11 21:40:59 imp Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -371,7 +371,7 @@ union cpuprid { #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ -#define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */ +#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ diff --git a/sys/arch/mips/mips/cpu.c b/sys/arch/mips/mips/cpu.c index 1fd8b1a08d7..afbcb3caa5d 100644 --- a/sys/arch/mips/mips/cpu.c +++ b/sys/arch/mips/mips/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.2 1998/03/16 09:03:23 pefo Exp $ */ +/* $OpenBSD: cpu.c,v 1.3 1998/07/11 21:41:15 imp Exp $ */ /* * Copyright (c) 1997 Per Fogelstrom @@ -113,6 +113,9 @@ cpuattach(parent, dev, aux) case MIPS_R4300: printf("NEC VR4300 CPU"); break; + case MIPS_R4100: + printf("NEC VR41xx CPU"); + break; case MIPS_R8000: printf("MIPS R8000 Blackbird/TFP CPU"); break; @@ -128,7 +131,6 @@ cpuattach(parent, dev, aux) case MIPS_RM52X0: printf("QED RM52X0 CPU"); break; - case MIPS_UNKC2: default: printf("Unknown CPU type (0x%x)",cpu_id.cpu.cp_imp); break; @@ -204,4 +206,3 @@ cpuattach(parent, dev, aux) else printf("No Snooping L2 cache!\n"); } - |