diff options
| author | Michael Shalayeff <mickey@cvs.openbsd.org> | 2000-06-15 17:00:38 +0000 |
|---|---|---|
| committer | Michael Shalayeff <mickey@cvs.openbsd.org> | 2000-06-15 17:00:38 +0000 |
| commit | b6db37d4f82be720722f923bd53a8014fa5b95ab (patch) | |
| tree | 66a082075fcf8669e26b8811835a262527dc2734 /sys/arch | |
| parent | c1c32eaefed9f1c8fe7be5ae7481e79b1d394890 (diff) | |
more dr0 definitions for pcxs/pcxt
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/hppa/include/asm.h | 12 | ||||
| -rw-r--r-- | sys/arch/hppa/include/reg.h | 25 |
2 files changed, 25 insertions, 12 deletions
diff --git a/sys/arch/hppa/include/asm.h b/sys/arch/hppa/include/asm.h index badda07d2f6..7fb5d1df944 100644 --- a/sys/arch/hppa/include/asm.h +++ b/sys/arch/hppa/include/asm.h @@ -1,4 +1,4 @@ -/* $OpenBSD: asm.h,v 1.10 2000/01/12 00:14:19 mickey Exp $ */ +/* $OpenBSD: asm.h,v 1.11 2000/06/15 17:00:37 mickey Exp $ */ /* * Copyright (c) 1990,1991,1994 The University of Utah and @@ -171,16 +171,6 @@ tr6 .reg %cr30 tr7 .reg %cr31 /* - * CPU-secific additional control registers - */ -#define dtlb_reg 8 -#define dtlb_size_even 26 -#define dtlb_size_odd 27 -#define itlb_reg 9 -#define itlb_size_even 24 -#define itlb_size_odd 25 - -/* * Calling Convention */ rp .reg %r2 diff --git a/sys/arch/hppa/include/reg.h b/sys/arch/hppa/include/reg.h index deecf1e9afd..cfc4e2fe27d 100644 --- a/sys/arch/hppa/include/reg.h +++ b/sys/arch/hppa/include/reg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: reg.h,v 1.6 2000/05/15 17:07:28 mickey Exp $ */ +/* $OpenBSD: reg.h,v 1.7 2000/06/15 17:00:37 mickey Exp $ */ /* * Copyright (c) 1998 Michael Shalayeff @@ -95,6 +95,19 @@ * Diagnostic registers and bit positions */ #define DR_CPUCFG 0 + +#define DR0_PCXS_DHPMC 10 /* r/c D-cache error flag */ +#define DR0_PCXS_ILPMC 14 /* r/c I-cache error flag */ +#define DR0_PCXS_EQWSTO 16 /* r/w enable quad-word stores */ +#define DR0_PCXS_IHE 18 /* r/w I-cache sid hash enable */ +#define DR0_PCXS_DOMAIN 19 +#define DR0_PCXS_DHE 20 /* r/w D-cache sid hash enable */ + +#define DR0_PCXT_DHPMC 10 /* r/c L1 D-cache error flag */ +#define DR0_PCXT_ILPMC 14 /* r/c L1 I-cache error flag */ +#define DR0_PCXT_IHE 18 /* r/w I-cache sid hash enable */ +#define DR0_PCXT_DHE 20 /* r/w D-cache sid hash enable */ + #define DR0_PCXL_L2IHPMC 6 /* r/c L2 I-cache error flag */ #define DR0_PCXL_L2IHPMC_DIS 7 /* r/w L2 I-cache hpmc disable mask */ #define DR0_PCXL_L2DHPMC 8 /* r/c L2 D-cache error flag */ @@ -136,6 +149,16 @@ #define DR0_PCXL2_RMIN_EN 28 /* r/w major ill insn traps on RIH */ #define DR0_PCXL2_L1CACHE_EN 29 /* r/w L1 I-cache enable */ +#define DR_DTLB 8 + +#define DR_ITLB 9 + +#define DR_ITLB_SIZE_1 24 +#define DR_ITLB_SIZE_0 25 + +#define DR_DTLB_SIZE_1 26 +#define DR_DTLB_SIZE_0 27 + #define CCR_MASK 0xff #define HPPA_NREGS (32) |