Preserve ATU translations instead of forcing the values to something.

Detect device type using some simple checks and use table driven
interrupt maps for known devices.
IO space appears to not want to be at 0, but at some bus offset (0x90000000)
so skew mappings into this io bus base.
Thecus N2100 and I/O Data Landisk (HDL-G) are now partially working.

4 files changed, 252 insertions, 175 deletions

diff --git a/sys/arch/armish/dev/i80321_mainbus.c b/sys/arch/armish/dev/i80321_mainbus.c
index 0aba92976f7..24f36dfb452 100644
--- a/sys/arch/armish/dev/i80321_mainbus.c
+++ b/sys/arch/armish/dev/i80321_mainbus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: i80321_mainbus.c,v 1.2 2006/05/29 17:30:26 drahn Exp $	*/
+/*	$OpenBSD: i80321_mainbus.c,v 1.3 2006/05/31 05:49:54 drahn Exp $	*/
 /*	$NetBSD: i80321_mainbus.c,v 1.16 2005/12/15 01:44:00 briggs Exp $	*/
 
 /*
@@ -116,7 +116,8 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 	pcireg_t b0u, b0l, b1u, b1l;
 	paddr_t memstart;
 	psize_t memsize;
-	pcireg_t foo;
+	pcireg_t atumembase;
+	pcireg_t atuiobase;
 
 	i80321_mainbus_found = 1;
 
@@ -149,9 +150,9 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 	    VERDE_OUT_XLATE_IO_WIN_SIZE, 0, &sc->sc_io_sh))
 		panic("%s: unable to map IOW registers", sc->sc_dev.dv_xname);
 
-	printf ("PIRSR %x\n", bus_space_read_4(sc->sc_st, sc->sc_sh, ICU_PIRSR));
+//	printf ("PIRSR %x\n", bus_space_read_4(sc->sc_st, sc->sc_sh, ICU_PIRSR));
 
-	printf("mapping bus io to %x - %x\n", sc->sc_io_sh, sc->sc_io_sh+VERDE_OUT_XLATE_IO_WIN_SIZE);
+//	printf("mapping bus io to %x - %x\n", sc->sc_io_sh, sc->sc_io_sh+VERDE_OUT_XLATE_IO_WIN_SIZE);
 
 	/*
 	 * Initialize the interrupt part of our PCI chipset tag.
@@ -161,9 +162,17 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 	/* Initialize the PCI chipset tag. */
 	i80321_pci_init(&sc->sc_pci_chipset, sc);
 
-	sc->sc_membus_space.bus_base = 0x40000000;
-	sc->sc_membus_space.bus_size = 0x10000000;
+	iq80321_pci_init2(&sc->sc_pci_chipset, sc);
 
+	atumembase = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
+	    PCI_MAPREG_START + 0x08);
+	atuiobase = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
+	    ATU_OIOWTVR);
+
+	sc->sc_membus_space.bus_base = PCI_MAPREG_MEM_ADDR(atumembase);
+	sc->sc_membus_space.bus_size = 0x04000000;
+	sc->sc_iobus_space.bus_base = PCI_MAPREG_IO_ADDR(atuiobase);
+	sc->sc_iobus_space.bus_size = 0x00010000;
 	pci_addr_fixup(sc, 2/*XXX*/);
 
 	/*
@@ -184,30 +193,6 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 	b1l &= PCI_MAPREG_MEM_ADDR_MASK;
 	b1u &= PCI_MAPREG_MEM_ADDR_MASK;
 
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0,
-	    0xffffffff);
-	foo = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0,
-	    b0l);
-
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4,
-	    0xffffffff);
-	foo = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4,
-	    b0u);
-	
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8,
-	    0xffffffff);
-	foo = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8,
-	    b1l);
-
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc,
-	    0xffffffff);
-	foo = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc,
-	    b1u);
-
 	printf(": i80321 I/O Processor\n");
 
 	i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
@@ -226,66 +211,119 @@ i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
 	 *
 	 * This chunk needs to be customized for each IOP321 application.
 	 */
-#if 0
-	sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
-	sc->sc_iwin[0].iwin_base_hi = 0;
-	sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
-	sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
-#else
-	sc->sc_iwin[0].iwin_base_lo = 0;
-	sc->sc_iwin[0].iwin_base_hi = 0;
-	sc->sc_iwin[0].iwin_xlate = 0;
-	sc->sc_iwin[0].iwin_size = 0;
-#endif
 
-	/* Map PCI:Local 1:1. */
-	sc->sc_iwin[1].iwin_base_lo = 0x40000000 |
-#if 0
-	    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
-	    PCI_MAPREG_MEM_TYPE_64BIT;
-#else
-	    0;
-#endif
-	sc->sc_iwin[1].iwin_base_hi = 0;
+	atumembase = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
+	    PCI_MAPREG_START + 0x08);
+	printf("atumembase %x\n", atumembase);
 
-	sc->sc_iwin[1].iwin_xlate = 0;
-	sc->sc_iwin[1].iwin_size = 0x08000000;
+	if (atumembase == 0x8000000c) {
+		/* iodata: intel std config */
 
-//	sc->sc_iwin[2].iwin_base_lo = memstart |
-	sc->sc_iwin[2].iwin_base_lo = 0 |
-	    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
-	    PCI_MAPREG_MEM_TYPE_64BIT;
-	sc->sc_iwin[2].iwin_base_hi = 0;
+		/* map device registers */
+		sc->sc_iwin[0].iwin_base_lo =	0x00000004;
+		sc->sc_iwin[0].iwin_base_hi =	0x00000000;
+		sc->sc_iwin[0].iwin_xlate = 	0xff000000;
+		sc->sc_iwin[0].iwin_size = 	0x01000000;
+		
+		/* Map PCI:Local 1:1. */
+		sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
+		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+		    PCI_MAPREG_MEM_TYPE_64BIT;
+		sc->sc_iwin[1].iwin_base_hi = 0;
 
-	sc->sc_iwin[2].iwin_xlate = memstart;
-	sc->sc_iwin[2].iwin_size = memsize;
+		sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
+		sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
 
-	sc->sc_iwin[3].iwin_base_lo = 0;
-	sc->sc_iwin[3].iwin_base_hi = 0;
-	sc->sc_iwin[3].iwin_xlate = 0;
-	sc->sc_iwin[3].iwin_size = 0;
 
-	/*
-	 * We set up the Outbound Windows as follows:
-	 *
-	 *	0	Access to private PCI space.
-	 *
-	 *	1	Unused.
-	 */
-	printf("setup outbound %x %x\n",
-	    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo),
-	    sc->sc_iwin[1].iwin_base_hi);
-	sc->sc_owin[0].owin_xlate_lo =
-	    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
-	sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
+		sc->sc_iwin[2].iwin_base_lo = memstart |
+		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+		    PCI_MAPREG_MEM_TYPE_64BIT;
+		sc->sc_iwin[2].iwin_base_hi = 0;
 
-	/*
-	 * Set the Secondary Outbound I/O window to map
-	 * to PCI address 0 for all 64K of the I/O space.
-	 */
-//	sc->sc_ioout_xlate = 0;
-	sc->sc_ioout_xlate = 0x90000000;
-	sc->sc_ioout_xlate_offset = 0x1000;
+		sc->sc_iwin[2].iwin_xlate = memstart;
+		sc->sc_iwin[2].iwin_size = memsize;
+
+		sc->sc_iwin[3].iwin_base_lo = 0;
+#if 0
+		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+		    PCI_MAPREG_MEM_TYPE_64BIT;
+#endif
+
+		sc->sc_iwin[3].iwin_base_hi = 0;
+		sc->sc_iwin[3].iwin_xlate = 0;
+		sc->sc_iwin[3].iwin_size = 0;
+
+		/*
+		 * We set up the Outbound Windows as follows:
+		 *
+		 *	0	Access to private PCI space.
+		 *
+		 *	1	Unused.
+		 */
+		sc->sc_owin[0].owin_xlate_lo =
+		    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
+		sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
+
+		/*
+		 * Set the Secondary Outbound I/O window to map
+		 * to PCI address 0 for all 64K of the I/O space.
+		 */
+		sc->sc_ioout_xlate = 0x90000000;
+		sc->sc_ioout_xlate_offset = 0x1000;
+	} else if (atumembase == 0x40000004) {
+		/* thecus */
+
+		/* dont map device registers */
+		sc->sc_iwin[0].iwin_base_lo = 0;
+		sc->sc_iwin[0].iwin_base_hi = 0;
+		sc->sc_iwin[0].iwin_xlate = 0;
+		sc->sc_iwin[0].iwin_size = 0;
+
+		/* Map PCI:Local 1:1. */
+		sc->sc_iwin[1].iwin_base_lo = 0x40000000 |
+	#if 0
+		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+		    PCI_MAPREG_MEM_TYPE_64BIT;
+	#else
+		    0;
+	#endif
+		sc->sc_iwin[1].iwin_base_hi = 0;
+
+		sc->sc_iwin[1].iwin_xlate = 0;
+		sc->sc_iwin[1].iwin_size = 0x08000000;
+
+		sc->sc_iwin[2].iwin_base_lo = 0 |
+		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+		    PCI_MAPREG_MEM_TYPE_64BIT;
+		sc->sc_iwin[2].iwin_base_hi = 0;
+
+		sc->sc_iwin[2].iwin_xlate = memstart;
+		sc->sc_iwin[2].iwin_size = memsize;
+
+		sc->sc_iwin[3].iwin_base_lo = 0;
+		sc->sc_iwin[3].iwin_base_hi = 0;
+		sc->sc_iwin[3].iwin_xlate = 0;
+		sc->sc_iwin[3].iwin_size = 0;
+
+		/*
+		 * We set up the Outbound Windows as follows:
+		 *
+		 *	0	Access to private PCI space.
+		 *
+		 *	1	Unused.
+		 */
+		sc->sc_owin[0].owin_xlate_lo =
+		    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
+		sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
+
+		/*
+		 * Set the Secondary Outbound I/O window to map
+		 * to PCI address 0 for all 64K of the I/O space.
+		 */
+		sc->sc_ioout_xlate = 0x90000000;
+		sc->sc_ioout_xlate_offset = 0x1000;
+
+	}
 
 	i80321_attach(sc);
 
diff --git a/sys/arch/armish/dev/iq80321_pci.c b/sys/arch/armish/dev/iq80321_pci.c
index a3433f55dac..e252ea0c4f9 100644
--- a/sys/arch/armish/dev/iq80321_pci.c
+++ b/sys/arch/armish/dev/iq80321_pci.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: iq80321_pci.c,v 1.2 2006/05/29 17:30:26 drahn Exp $	*/
+/*	$OpenBSD: iq80321_pci.c,v 1.3 2006/05/31 05:49:54 drahn Exp $	*/
 /*	$NetBSD: iq80321_pci.c,v 1.5 2005/12/11 12:17:09 christos Exp $	*/
 
 /*
@@ -62,15 +62,113 @@ void	*iq80321_pci_intr_establish(void *, pci_intr_handle_t,
 	    int, int (*func)(void *), void *, char *);
 void	iq80321_pci_intr_disestablish(void *, void *);
 
+struct irq_map {
+	uint8_t	dev;
+	uint8_t	intrpin;
+	uint8_t	irq;
+};
+
+
+struct pci_id_list {
+	uint8_t bus;
+	uint8_t dev;
+	pci_vendor_id_t	vend;
+	pci_product_id_t prod;
+};
+
+struct board_id {
+	char *name;
+	struct irq_map *irq_map;
+	struct pci_id_list list[]; 
+};
+
+struct irq_map *iq80321_irq_map;
+
+struct irq_map iq80321_thecus_irq_map[] = {
+	{ 1, 1, ICU_INT_XINT(2) }, /* thecus re0 29 ??? */
+	{ 2, 1, ICU_INT_XINT(2) }, /* thecus re1 29 ??? */
+	{ 3, 1, ICU_INT_XINT(2) }, /* thecus sata 29 */
+#if 0
+	{ 4, 1, ICU_INT_XINT(2) }, /* thecus uhci0 29 ??? */
+#endif
+	{ 4, 2, ICU_INT_XINT(2) }, /* thecus uhci1 29 ??? */
+	{ 4, 3, ICU_INT_XINT(2) }, /* thecus ehci0 29 */
+	{ 5, 1, ICU_INT_XINT(2) }, /* thecus minipci slot */
+
+	{ 0, 0, 255}
+};
+
+struct irq_map iq80321_hdlg_irq_map[] = {
+	{ 1, 1, ICU_INT_XINT(0) }, /* em0 27 ??? */
+	{ 2, 1, ICU_INT_XINT(1) }, /* wdc0 28 ??? */
+	{ 3, 1, ICU_INT_XINT(2) }, /* ochi0 29 */
+	{ 3, 2, ICU_INT_XINT(2) }, /* ochi0 29 */
+	{ 3, 3, ICU_INT_XINT(2) }, /* echi0 29 */
+
+	{ 0, 0, 255}
+};
+struct board_id thecus = {
+	"Thecus Nx100",
+	iq80321_thecus_irq_map,
+	{
+	{ 0, 	1,	PCI_VENDOR_REALTEK,	PCI_PRODUCT_REALTEK_RT8169 },
+	/* fill in the rest of the devices */
+	{ 0, 	0,	0,	0 }
+	}
+};
+struct board_id iodata = {
+	"I/O Data HDL-G",
+	iq80321_hdlg_irq_map,
+	{
+	{ 0, 	1,	PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI },
+	/* fill in the rest of the devices */
+	{ 0, 	0,	0,	0 }
+	}
+};
+
+struct board_id *systems[] = {
+	&thecus,
+	&iodata,
+	NULL
+};
+
 void
 iq80321_pci_init(pci_chipset_tag_t pc, void *cookie)
 {
-
 	pc->pc_intr_v = cookie;		/* the i80321 softc */
 	pc->pc_intr_map = iq80321_pci_intr_map;
 	pc->pc_intr_string = iq80321_pci_intr_string;
 	pc->pc_intr_establish = iq80321_pci_intr_establish;
 	pc->pc_intr_disestablish = iq80321_pci_intr_disestablish;
+
+}
+void
+iq80321_pci_init2(pci_chipset_tag_t pc, void *cookie)
+{
+	pcitag_t tag;
+	int i, j;
+	struct board_id *sys;
+
+	tag = pci_make_tag(pc, 0, 1, 0);
+
+	for (i = 0; systems[i] != NULL; i++) {
+		sys = systems[i];
+		for (j = 0; sys->list[j].vend != 0; j++) {
+			if ((sys->list[j].vend | sys->list[j].prod << 16)  !=
+			     pci_conf_read(pc, tag, 0 /* ID */)) {
+				sys = NULL;
+				break;
+			}
+		}
+		if (sys != NULL)
+			break;
+	}
+	if (sys == NULL)
+		printf("board id failed\n");
+	else
+		printf(": %s", sys->name);
+	iq80321_irq_map = sys->irq_map;
+
 }
 
 int
@@ -79,23 +177,12 @@ iq80321_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 	struct i80321_softc *sc = pa->pa_pc->pc_intr_v;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	pcitag_t tag = pa->pa_intrtag;
+	int i;
 
 	int b, d, f;
 	uint32_t busno;
 	uint32_t intr;
 
-	/*
-	 * The IQ80321's interrupts are routed like so:
-	 *
-	 *	XINT0	i82544 Gig-E
-	 *
-	 *	XINT1	UART
-	 *
-	 *	XINT2	INTA# from S-PCI-X slot
-	 *
-	 *	XINT3	INTB# from S-PCI-X slot
-	 */
-
 	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
 	busno = PCIXSR_BUSNO(busno);
 	if (busno == 0xff)
@@ -107,83 +194,26 @@ iq80321_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 	if (b != busno)
 		goto no_mapping;
 
-	switch (d) {
-#if 1
-	case 1:			/* theucs re(4) 0 */
-		if (pa->pa_intrpin == 1) {
-			*ihp = ICU_INT_XINT(2); /* 29 */
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-
-			return (0);
-		}
-		goto no_mapping;
-	case 2:			/* theucs re(4) 1 */
-		if (pa->pa_intrpin == 1) {
-			*ihp = ICU_INT_XINT(2); /* 30 */
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
+	for (i = 0; iq80321_irq_map[i].irq != 255; i++) {
+		if (d == iq80321_irq_map[i].dev &&
+		    pa->pa_intrpin == iq80321_irq_map[i].intrpin) {
+			*ihp = iq80321_irq_map[i].irq;
+			intr = pci_conf_read(pa->pa_pc, pa->pa_intrtag,
+			    PCI_INTERRUPT_REG);
+			intr = (intr & ~0xff) | iq80321_irq_map[i].irq;
+			pci_conf_write(pa->pa_pc, pa->pa_intrtag,
+			    PCI_INTERRUPT_REG, intr);
 			return (0);
 		}
-		goto no_mapping;
-#endif
-	case 3:			/* thecus sata */
-		if (pa->pa_intrpin == 1) {
-			*ihp = ICU_INT_XINT(2);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-		goto no_mapping;
-	case 4:			/* thecus */
-#if 0
-		if (pa->pa_intrpin == 1) {	/* thecus uhci1 */
-			*ihp = ICU_INT_XINT(2);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-#endif
-#if 0
-		if (pa->pa_intrpin == 2) {	/* thecus uhci1 */
-			*ihp = ICU_INT_XINT(2);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-#endif
-		if (pa->pa_intrpin == 3) {	/* thecus ehci1 */
-			*ihp = ICU_INT_XINT(2);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-		goto no_mapping;
-	case 5:			/* thecus minipci slot */
-		if (pa->pa_intrpin == 1) {
-			*ihp = ICU_INT_XINT(3);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-		goto no_mapping;
-	case 6:			/* S-PCI-X slot */
-		if (pa->pa_intrpin == 1) {
-			*ihp = ICU_INT_XINT(2);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-		if (pa->pa_intrpin == 2) {
-			*ihp = ICU_INT_XINT(3);
-			pci_conf_write(pc, tag, PCI_INTERRUPT_REG, *ihp);
-			return (0);
-		}
-		goto no_mapping;
+	}
 
-	default:
  no_mapping:
-		intr = pci_conf_read(pa->pa_pc, pa->pa_intrtag,
-		    PCI_INTERRUPT_REG);
-
-		printf("iq80321_pci_intr_map: no mapping for %d/%d/%d (%d, %d, %d)\n",
-		    pa->pa_bus, pa->pa_device, pa->pa_function, d, pa->pa_intrpin, intr);
-		return (1);
-	}
+	intr = pci_conf_read(pa->pa_pc, pa->pa_intrtag,
+	    PCI_INTERRUPT_REG);
 
-	return (0);
+	printf("iq80321_pci_intr_map: no mapping for %d/%d/%d (%d, %d, %d)\n",
+	    pa->pa_bus, pa->pa_device, pa->pa_function, d, pa->pa_intrpin, intr);
+	return (1);
 }
 
 const char *
diff --git a/sys/arch/armish/dev/iq80321var.h b/sys/arch/armish/dev/iq80321var.h
index b2282a9fd47..a45ef56f40b 100644
--- a/sys/arch/armish/dev/iq80321var.h
+++ b/sys/arch/armish/dev/iq80321var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: iq80321var.h,v 1.2 2006/05/29 17:30:26 drahn Exp $	*/
+/*	$OpenBSD: iq80321var.h,v 1.3 2006/05/31 05:49:54 drahn Exp $	*/
 /*	$NetBSD: iq80321var.h,v 1.1 2002/03/27 21:51:30 thorpej Exp $	*/
 
 /*
@@ -45,6 +45,7 @@ void	iq80321_7seg(char, char);
 void	iq80321_7seg_snake(void);
 
 void	iq80321_pci_init(pci_chipset_tag_t, void *);
+void	iq80321_pci_init2(pci_chipset_tag_t, void *);
 void	save_ref(void);
 void	check_ref(void);
 
diff --git a/sys/arch/armish/dev/pci_addr_fixup.c b/sys/arch/armish/dev/pci_addr_fixup.c
index 9b814994605..1049ae4f14f 100644
--- a/sys/arch/armish/dev/pci_addr_fixup.c
+++ b/sys/arch/armish/dev/pci_addr_fixup.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pci_addr_fixup.c,v 1.1 2006/05/29 17:13:19 drahn Exp $	*/
+/*	$OpenBSD: pci_addr_fixup.c,v 1.2 2006/05/31 05:49:54 drahn Exp $	*/
 /*	$NetBSD: pci_addr_fixup.c,v 1.7 2000/08/03 20:10:45 nathanw Exp $	*/
 
 /*-
@@ -73,7 +73,7 @@ void pci_device_foreach(struct i80321_softc *sc, pci_chipset_tag_t pc,
 #define PCIADDR_PORT_START	0x0
 #define PCIADDR_PORT_END	0xffff
 
-int pcibr_flags = 0;
+int pcibr_flags = 3;
 #define PCIBR_VERBOSE		1
 #define PCIBR_ADDR_FIXUP	2
 
@@ -99,7 +99,8 @@ pci_addr_fixup(void *v, int maxbus)
 	    M_DEVBUF, 0, 0, EX_NOWAIT);
 	KASSERT(sc->extent_mem);
 	sc->extent_port = extent_create("PCI I/O port space",
-	    PCIADDR_PORT_START, PCIADDR_PORT_END,
+            sc->sc_iobus_space.bus_base,
+            sc->sc_iobus_space.bus_base + sc->sc_iobus_space.bus_size,
 	    M_DEVBUF, 0, 0, EX_NOWAIT);
 	KASSERT(sc->extent_port);
 
@@ -218,7 +219,14 @@ pciaddr_resource_manage(struct i80321_softc *sc, pci_chipset_tag_t pc,
 			ex = sc->extent_mem;
 		} else {
 			/* XXX some devices give 32bit value */
-			addr = PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END;
+			addr = PCI_MAPREG_IO_ADDR(val);
+			if (sc->sc_iobus_space.bus_base != PCIADDR_PORT_START &&
+			    addr < sc->sc_iobus_space.bus_base) {
+				/* skew address to be in range */
+				addr = PCI_MAPREG_IO_ADDR(val) &
+				     PCIADDR_PORT_END;
+				addr |= sc->sc_iobus_space.bus_base;
+			}
 			size = PCI_MAPREG_IO_SIZE(mask);
 			ex = sc->extent_port;
 		}
@@ -322,7 +330,7 @@ pciaddr_ioaddr(u_int32_t val)
 {
 	return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM)
 		? PCI_MAPREG_MEM_ADDR(val)
-		: (PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END));
+		: (PCI_MAPREG_IO_ADDR(val)));
 }
 
 void