Initial checkin of the Amiga ISA-kit

13 files changed, 4235 insertions, 0 deletions

diff --git a/sys/arch/amiga/isa/cross.c b/sys/arch/amiga/isa/cross.c
new file mode 100644
index 00000000000..2b1422c2970
--- /dev/null
+++ b/sys/arch/amiga/isa/cross.c
@@ -0,0 +1,318 @@
+/*	$NetBSD: cross.c,v 1.0 1994/07/08 23:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1994 Niklas Hallqvist, Carsten Hammer
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christian E. Hopps.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/syslog.h>
+
+#include <machine/cpu.h>
+#include <machine/pio.h>
+
+#include <dev/isa/isavar.h>
+
+#include <amiga/amiga/custom.h>
+#include <amiga/amiga/device.h>
+#include <amiga/amiga/isr.h>
+#include <amiga/dev/zbusvar.h>
+#include <amiga/isa/isa_machdep.h>
+#include <amiga/isa/isa_intr.h>
+#include <amiga/isa/crossvar.h>
+#include <amiga/isa/crossreg.h>
+
+int crossdebug = 0;
+
+/* This static is OK because we only allow one ISA bus.  */
+struct cross_device *crossp;
+
+void crossattach __P((struct device *, struct device *, void *));
+int crossmatch __P((struct device *, void *, void *));
+int crossprint __P((void *auxp, char *));
+void crossstb __P((struct device *, int, u_char));
+u_char crossldb __P((struct device *, int));
+void crossstw __P((struct device *, int, u_short));
+u_short crossldw __P((struct device *, int));
+void    *cross_establish_intr __P((int intr, int type, int level,
+                                   int (*ih_fun) (void *), void *));
+void    cross_disestablish_intr __P((void *handler));
+
+struct isa_intr_fcns cross_intr_fcns = {
+        0 /* cross_intr_setup */,       cross_establish_intr,
+        cross_disestablish_intr,        0 /* cross_iointr */
+};
+
+struct cfdriver crosscd = {
+	NULL, "cross", crossmatch, crossattach, 
+	DV_DULL, sizeof(struct cross_device), 0
+};
+
+int
+crossmatch(parent, match, aux)
+	struct device *parent;
+	void *match, *aux;
+{
+	struct zbus_args *zap = aux;
+
+	/*
+	 * Check manufacturer and product id.
+	 */
+	if (zap->manid == 2011 && zap->prodid == 3)
+		return(1);
+	return(0);
+}
+
+void
+crossattach(pdp, dp, auxp)
+	struct device *pdp, *dp;
+	void *auxp;
+{
+	struct zbus_args *zap = auxp;
+	struct cross_device *cdp = (struct cross_device *)dp;
+
+	crossp = cdp;
+	bcopy(zap, &cdp->cd_zargs, sizeof(struct zbus_args));
+	cdp->cd_link.il_dev = dp;
+	cdp->cd_link.il_ldb = crossldb;
+	cdp->cd_link.il_stb = crossstb;
+	cdp->cd_link.il_ldw = crossldw;
+	cdp->cd_link.il_stw = crossstw;
+	cdp->cd_imask = 1 << CROSS_MASTER;
+
+	isa_intr_fcns = &cross_intr_fcns;
+        isa_pio_fcns = &cross_pio_fcns;
+
+	/* Enable interrupts lazily in crossaddint.  */
+	CROSS_ENABLE_INTS(zap->va, 0);
+	/* Default 16 bit tranfer  */
+	*(volatile u_short *)(cdp->cd_zargs.va + CROSS_XLP_LATCH) = CROSS_SBHE; 
+
+	printf(": pa 0x%08x va 0x%08x size 0x%x\n", zap->pa, zap->va,
+            zap->size);
+
+
+	/*
+	 * attempt to configure the board.
+	 */
+	config_found(dp, &cdp->cd_link, crossprint);
+}
+
+int
+crossprint(auxp, pnp)
+	void *auxp;
+	char *pnp;
+{
+	if (pnp == NULL)
+		return(QUIET);
+	return(UNCONF);
+}
+
+
+void
+crossstb(dev, ia, b)
+	struct device *dev;
+	int ia;
+	u_char b;
+{
+	/* generate A13-A19 for correct page */
+	u_short upper_addressbits = ia >> 13;
+	struct cross_device *cd = (struct cross_device *)dev;
+
+	*(volatile u_short *)(cd->cd_zargs.va + CROSS_XLP_LATCH) =
+	    upper_addressbits | CROSS_SBHE;
+	*(volatile u_char *)(cd->cd_zargs.va + CROSS_MEMORY_OFFSET + 2 * ia) =
+	    b;
+}
+
+u_char
+crossldb(dev, ia)
+	struct device *dev;
+	int ia;
+{
+	/* generate A13-A19 for correct page */
+	u_short upper_addressbits = ia >> 13;
+	struct cross_device *cd = (struct cross_device *)dev;
+
+	*(volatile u_short *)(cd->cd_zargs.va + CROSS_XLP_LATCH) =
+	    upper_addressbits | CROSS_SBHE;
+	return *(volatile u_char *)(cd->cd_zargs.va + CROSS_MEMORY_OFFSET +
+            2 * ia);
+}
+
+void
+crossstw(dev, ia, w)
+	struct device *dev;
+	int ia;
+	u_short w;
+{
+	/* generate A13-A19 for correct page */
+	u_short upper_addressbits = ia >> 13;
+	struct cross_device *cd = (struct cross_device *)dev;
+ 	
+	*(volatile u_short *)(cd->cd_zargs.va + CROSS_XLP_LATCH) =
+	    upper_addressbits | CROSS_SBHE;
+#ifdef DEBUG
+	if (crossdebug)
+		printf("outw 0x%x,0x%x\n", ia, w);
+#endif
+	*(volatile u_short *)(cd->cd_zargs.va + CROSS_MEMORY_OFFSET + 2 * ia) =
+	    w;
+}
+
+u_short
+crossldw(dev, ia)
+	struct device *dev;
+	int ia;
+{
+	/* generate A13-A19 for correct page */
+	u_short upper_addressbits = ia >> 13;
+	struct cross_device *cd = (struct cross_device *)dev;
+	u_short retval;
+
+	*(volatile u_short *)(cd->cd_zargs.va + CROSS_XLP_LATCH) =
+	    upper_addressbits | CROSS_SBHE;
+	retval = *(volatile u_short *)(cd->cd_zargs.va + CROSS_MEMORY_OFFSET +
+	    2 * ia);
+#ifdef DEBUG
+	if (crossdebug)
+		printf("ldw 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
+static cross_int_map[] = {
+    0, 0, 0, 0, CROSS_IRQ3, CROSS_IRQ4, CROSS_IRQ5, CROSS_IRQ6, CROSS_IRQ7, 0,
+    CROSS_IRQ9, CROSS_IRQ10, CROSS_IRQ11, CROSS_IRQ12, 0, CROSS_IRQ14,
+    CROSS_IRQ15
+};
+
+#if 0
+/* XXX We don't care about the priority yet, although we ought to.  */
+void
+crossaddint(dev, irq, func, arg, pri)
+	struct device *dev;
+	int irq;
+	int (*func)();
+	void *arg;
+	int pri;
+{
+	struct cross_device *cd = (struct cross_device *)dev;
+	int s = splhigh();
+	int bit = cross_int_map[irq + 1];
+
+	if (!bit) {
+		log(LOG_WARNING, "Registration of unknown ISA interrupt %d\n",
+		    irq);
+		goto out;
+	}
+	if (cd->cd_imask & 1 << bit) {
+		log(LOG_WARNING, "ISA interrupt %d already handled\n", irq);
+		goto out;
+	}
+	cd->cd_imask |= (1 << bit);
+        CROSS_ENABLE_INTS (cd->cd_zargs.va, cd->cd_imask);
+	cd->cd_ifunc[bit] = func;
+	cd->cd_ipri[bit] = pri;
+	cd->cd_iarg[bit] = arg;
+out:
+	splx(s);
+}
+
+void
+crossremint(dev, irq)
+	struct device *dev;
+	int irq;
+{
+	struct cross_device *cd = (struct cross_device *)dev;
+	int s = splhigh();
+	int bit = cross_int_map[irq + 1];
+
+	cd->cd_imask &= ~(1 << bit);
+        CROSS_ENABLE_INTS (cd->cd_zargs.va, cd->cd_imask);
+	splx(s);
+}
+#endif
+struct crossintr_desc {
+	struct	isr cid_isr;
+	int	cid_mask;
+        int     (*cid_fun)(void *);
+        void    *cid_arg;
+};
+
+static struct crossintr_desc *crid[16];	/* XXX */
+
+int
+crossintr(cid)
+	struct crossintr_desc *cid;
+{
+	return (CROSS_GET_STATUS (crossp->cd_zargs.va) & cid->cid_mask) ?
+	    (*cid->cid_fun)(cid->cid_arg) : 0;
+}
+
+void *
+cross_establish_intr(intr, type, level, ih_fun, ih_arg)
+        int intr;
+        int type;
+        int level;
+        int (*ih_fun)(void *);
+        void *ih_arg;
+{
+	if (crid[intr]) {
+		log(LOG_WARNING, "ISA interrupt %d already handled\n", intr);
+		return 0;
+	}
+	MALLOC(crid[intr], struct crossintr_desc *,
+	    sizeof(struct crossintr_desc), M_DEVBUF, M_WAITOK);
+	crid[intr]->cid_isr.isr_intr = crossintr;
+	crid[intr]->cid_isr.isr_arg = crid[intr];
+	crid[intr]->cid_isr.isr_ipl = 6;
+	crid[intr]->cid_isr.isr_mapped_ipl = level;
+	crid[intr]->cid_mask = 1 << cross_int_map[intr + 1];
+	crid[intr]->cid_fun = ih_fun;
+	crid[intr]->cid_arg = ih_arg;
+	add_isr (&crid[intr]->cid_isr);
+	crossp->cd_imask |= 1 << cross_int_map[intr + 1];
+        CROSS_ENABLE_INTS (crossp->cd_zargs.va, crossp->cd_imask);
+	return &crid[intr];
+}
+
+void
+cross_disestablish_intr(handler)
+        void  *handler;
+{
+        struct crossintr_desc **cid = handler;
+
+	remove_isr(&(*cid)->cid_isr);
+	crossp->cd_imask &= ~(*cid)->cid_mask;
+	FREE(*cid, M_DEVBUF);
+	*cid = 0;
+        CROSS_ENABLE_INTS (crossp->cd_zargs.va, crossp->cd_imask);
+}
diff --git a/sys/arch/amiga/isa/cross_pio.c b/sys/arch/amiga/isa/cross_pio.c
new file mode 100644
index 00000000000..c2e5ed41316
--- /dev/null
+++ b/sys/arch/amiga/isa/cross_pio.c
@@ -0,0 +1,114 @@
+/*	$NetBSD: cross_pio.c,v 1.1 1995/08/04 14:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1995 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/types.h>
+#include <sys/device.h>
+
+#include <machine/pio.h>
+
+#include <dev/isa/isavar.h>
+
+#include <amiga/amiga/isr.h>
+#include <amiga/dev/zbusvar.h>
+#include <amiga/isa/isa_machdep.h>
+#include <amiga/isa/crossreg.h>
+#include <amiga/isa/crossvar.h>
+
+extern struct cross_device *crossp;
+
+void		cross_outb __P((int, u_int8_t));
+u_int8_t	cross_inb __P((int));
+void		cross_outw __P((int, u_int16_t));
+u_int16_t	cross_inw __P((int));
+
+struct isa_pio_fcns cross_pio_fcns = {
+	cross_inb,	isa_insb,
+	cross_inw,	isa_insw,
+	0 /* cross_inl */,	0 /* cross_insl */,
+	cross_outb,	isa_outsb,
+	cross_outw,	isa_outsw,
+	0 /* cross_outl */,	0 /* cross_outsl */,
+};
+
+void
+cross_outb(ia, b)
+	int ia;
+	u_int8_t b;
+{
+#ifdef DEBUG
+	if (crossdebug)
+		printf("outb 0x%x,0x%x\n", ia, b);
+#endif
+	*(volatile u_int8_t *)(crossp->cd_zargs.va + 2 * ia) = b;
+}
+
+u_int8_t
+cross_inb(ia)
+	int ia;
+{
+	u_int8_t retval =
+	    *(volatile u_int8_t *)(crossp->cd_zargs.va + 2 * ia);
+
+
+#ifdef DEBUG
+	if (crossdebug)
+		printf("inb 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
+void
+cross_outw(ia, w)
+	int ia;
+	u_int16_t w;
+{
+#ifdef DEBUG
+	if (crossdebug)
+		printf("outw 0x%x,0x%x\n", ia, w);
+#endif
+	*(volatile u_int16_t *)(crossp->cd_zargs.va + 2 * ia) = w;
+}
+
+u_int16_t
+cross_inw(ia)
+	int ia;
+{
+	u_int16_t retval =
+            *(volatile u_int16_t *)(crossp->cd_zargs.va + 2 * ia);
+
+
+#ifdef DEBUG
+	if (crossdebug)
+		printf("inw 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
diff --git a/sys/arch/amiga/isa/crossreg.h b/sys/arch/amiga/isa/crossreg.h
new file mode 100644
index 00000000000..e348bd4bc1e
--- /dev/null
+++ b/sys/arch/amiga/isa/crossreg.h
@@ -0,0 +1,133 @@
+/*	$NetBSD: crossreg.h,v 1.1 1994/07/08 23:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1994 Niklas Hallqvist, Carsten Hammer
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christian E. Hopps.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _CROSSREG_H_
+#define _CROSSREG_H_
+/***
+* 
+*
+* Hardware description:
+*
+*  The CrossLink board is a 64K autoconfig device. The board address can be
+*  read from the xlink.resource structure instead of searching with the
+*  expansion library. In this way, the manufacturer ID is not required by
+*  the software developer.
+*
+*  Address mapping is as follows:
+*   XL_ROM     16K of byte wide ROM appearing at even locations.
+*              Used to hold the xlink.resource, and any autobooting
+*              devices.
+*   XL_MEM     Memory space. For 8 bit cards, bytes appear at even
+*              locations, (ie multiply address by 2). For 16 bit cards,
+*              words appear at long word boundaries (ie multiply by
+*              2). You can read bytes from 16 bit cards - odd bytes
+*              will appear at odd locations. SBHE must be set to the
+*              appropriate value for this. Multiple pages are accessible
+*              via the page register (see MemPage register).
+*   XL_IO      I/O space. 8K of I/O space is supported by the hardware,
+*              however only 1K is managed by this resource (as IBM's
+*              *never* have cards which decode more I/O space than this).
+*              You should AllocPortSpace() the area you want to use to
+*              get exclusive access before using the I/O. 8/16 bit cards
+*              read/write bytes/words at word boundaries. (You should know
+*              whether the port is 8 or 16 bits wide).
+*
+* Within the 1K I/O space, there are some 8 and 16 bit registers on the
+* xlink board itself. These registers are normally only accessed by
+* the xlink.resource, they are only described here for completeness.
+* Later revisions of the CrossLink board may move/change the meaning
+* of these registers. They are as follows:
+* (actual address = SBP_xxxx + SB_IO + board address)
+*
+*   XLP_LATCH  (Write Only) (offset = 2)
+*              Latches most significant address lines. D0-D6 contain the
+*              values for the most significant 7 address lines (A13-A19).
+*              D7 contains data for SBHE line (always 1 for 8 bit transfers
+*              on 8 bit boards, and 16 bit transfers on 16 bit boards.
+*              Set SBHE to 0 to perform 8 bit transfers on 16 bit boards).
+*
+*   XLP_INTABLE (Write Only) (offset = 0)
+*              Interrupt Enable & Disable. Bits map to the interrupts in
+*              the following manner:
+*                Data   Interrupt          Data   Interrupt
+*                 2        10               10       2
+*                 3        11               11       3
+*                 4        12               12       4
+*                 5        Master           13       5
+*                 6        14               14       6
+*                 7        15               15       7
+*              Unused bits should not be interpreted in any way. When
+*              writing to this register, unused bits should be zero. This
+*              register should only be used by the xlink.resource.
+*
+*   XLP_INTSTAT (Read Only) (offset = 0)
+*              Interrupt Status. Bit mapping is the same as the
+*              XLP_INTABLE location. Normally you only need to add your
+*              interrupt handler to the appropriate port, and not worry
+*              about this register. However, it can be also used to
+*              determine which interrupt a board is connected to. 
+**/
+/* hardware offsets from config address */
+
+#define CROSS_XL_ROM          0x8000
+#define CROSS_XL_MEM          0x4000
+#define CROSS_XL_IO           0x0000
+
+#define CROSS_XLP_INTSTAT 0
+#define CROSS_XLP_INTABLE 0
+#define CROSS_XLP_LATCH 2
+
+#define CROSS_MEMORY_OFFSET (CROSS_XL_MEM - 2 * 0x90000)
+#define CROSS_SBHE 0x40
+
+#define CROSS_GET_STATUS(va) \
+    (*(volatile u_short *)((va) + CROSS_XLP_INTSTAT))
+
+#define CROSS_MASTER 5
+/* From what I understand IRQ2 is really IRQ9 -NH */
+#define CROSS_IRQ9 10
+#define CROSS_IRQ3 11
+#define CROSS_IRQ4 12
+#define CROSS_IRQ5 13
+#define CROSS_IRQ6 14
+#define CROSS_IRQ7 15
+#define CROSS_IRQ10 2
+#define CROSS_IRQ11 3
+#define CROSS_IRQ12 4
+#define CROSS_IRQ14 6
+#define CROSS_IRQ15 7
+#define CROSS_IRQMASK 0xfcdc
+#define CROSS_GET_INT_STATUS(va) (CROSS_GET_STATUS(va) & CROSS_IRQMASK)
+
+#define CROSS_ENABLE_INTS(va, ints) \
+    (*(volatile u_short *)((va) + CROSS_XLP_INTABLE) = ints) 
+
+#endif
diff --git a/sys/arch/amiga/isa/crossvar.h b/sys/arch/amiga/isa/crossvar.h
new file mode 100644
index 00000000000..0ef789c47d4
--- /dev/null
+++ b/sys/arch/amiga/isa/crossvar.h
@@ -0,0 +1,48 @@
+/*	$NetBSD: crossvar.h,v 1.1 1994/07/08 23:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1994 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christian E. Hopps.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _CROSSVAR_H_
+#define _CROSSVAR_H_
+
+struct cross_device {
+	struct	device cd_dev;
+	struct	zbus_args cd_zargs;
+	struct	isa_link cd_link;
+	int	(*cd_ifunc[16])();
+	void	*cd_iarg[16];
+	int	cd_ipri[16];
+	int	cd_imask;
+	struct	isr cd_isr;
+};
+
+extern int crossdebug;
+
+#endif
diff --git a/sys/arch/amiga/isa/ggbus.c b/sys/arch/amiga/isa/ggbus.c
new file mode 100644
index 00000000000..40a1fd91df9
--- /dev/null
+++ b/sys/arch/amiga/isa/ggbus.c
@@ -0,0 +1,260 @@
+/*	$NetBSD: ggbus.c,v 1.1 1994/07/08 23:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1994, 1995 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/syslog.h>
+
+#include <machine/cpu.h>
+#include <machine/pio.h>
+
+#include <dev/isa/isavar.h>
+
+#include <amiga/amiga/custom.h>
+#include <amiga/amiga/device.h>
+#include <amiga/amiga/isr.h>
+#include <amiga/dev/zbusvar.h>
+#include <amiga/isa/isa_machdep.h>
+#include <amiga/isa/isa_intr.h>
+#include <amiga/isa/ggbusvar.h>
+#include <amiga/isa/ggbusreg.h>
+
+int ggdebug = 0;
+int ggstrayints = 0;
+
+/* This is OK because we only allow one ISA bus.  */
+struct ggbus_device *ggbusp;
+
+void	ggbusattach __P((struct device *, struct device *, void *));
+int	ggbusmatch __P((struct device *, void *, void *));
+int	ggbusprint __P((void *auxp, char *));
+void	ggbusstb __P((struct device *, int, u_char));
+u_char	ggbusldb __P((struct device *, int));
+void	ggbusstw __P((struct device *, int, u_short));
+u_short ggbusldw __P((struct device *, int));
+void	*ggbus_establish_intr __P((int intr, int type, int level,
+				   int (*ih_fun) (void *), void *));
+void	ggbus_disestablish_intr __P((void *handler));
+
+struct isa_intr_fcns ggbus_intr_fcns = {
+	0 /* ggbus_intr_setup */,	ggbus_establish_intr,
+	ggbus_disestablish_intr,	0 /* ggbus_iointr */
+};
+
+struct cfdriver ggbuscd = {
+	NULL, "ggbus", ggbusmatch, ggbusattach, 
+	DV_DULL, sizeof(struct ggbus_device), 0
+};
+
+int
+ggbusmatch(parent, match, aux)
+	struct device *parent;
+	void *match, *aux;
+{
+	struct zbus_args *zap = aux;
+
+	/*
+	 * Check manufacturer and product id.
+	 */
+	if (zap->manid == 2150 && zap->prodid == 1)
+		return(1);
+	return(0);
+}
+
+void
+ggbusattach(pdp, dp, auxp)
+	struct device *pdp, *dp;
+	void *auxp;
+{
+	struct zbus_args *zap = auxp;
+	struct ggbus_device *gdp = (struct ggbus_device *)dp;
+
+	ggbusp = gdp;
+	bcopy(zap, &gdp->gd_zargs, sizeof(struct zbus_args));
+	gdp->gd_link.il_dev = dp;
+	if (gdp->gd_zargs.serno >= 2)
+	  {
+	    gdp->gd_link.il_ldb = ggbusldb;
+	    gdp->gd_link.il_stb = ggbusstb;
+	    gdp->gd_link.il_ldw = ggbusldw;
+	    gdp->gd_link.il_stw = ggbusstw;
+	  }
+	else
+	  {
+	    gdp->gd_link.il_ldb = 0;
+	    gdp->gd_link.il_stb = 0;
+	    gdp->gd_link.il_ldw = 0;
+	    gdp->gd_link.il_stw = 0;
+	  }
+	gdp->gd_imask = 0;
+
+	isa_intr_fcns = &ggbus_intr_fcns;
+	isa_pio_fcns = &ggbus_pio_fcns;
+
+	if (gdp->gd_zargs.serno >= 2)
+	  {
+	    /* XXX turn on wait states unconditionally for now. */
+	    GG2_ENABLE_WAIT(zap->va);
+	    GG2_ENABLE_INTS(zap->va);
+	  }
+
+	printf(": pa 0x%08x va 0x%08x size 0x%x\n", zap->pa, zap->va, zap->size);
+
+	/*
+	 * attempt to configure the board.
+	 */
+	config_found(dp, &gdp->gd_link, ggbusprint);
+}
+
+int
+ggbusprint(auxp, pnp)
+	void *auxp;
+	char *pnp;
+{
+	if (pnp == NULL)
+		return(QUIET);
+	return(UNCONF);
+}
+
+
+void
+ggbusstb(dev, ia, b)
+	struct device *dev;
+	int ia;
+	u_char b;
+{
+	struct ggbus_device *gd = (struct ggbus_device *)dev;
+
+	*(volatile u_char *)(gd->gd_zargs.va + GG2_MEMORY_OFFSET + 2 * ia + 1) = b;
+}
+
+u_char
+ggbusldb(dev, ia)
+	struct device *dev;
+	int ia;
+{
+	struct ggbus_device *gd = (struct ggbus_device *)dev;
+	u_char retval =
+	    *(volatile u_char *)(gd->gd_zargs.va + GG2_MEMORY_OFFSET + 2 * ia + 1);
+
+#ifdef DEBUG
+	if (ggdebug)
+		printf("ldb 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
+void
+ggbusstw(dev, ia, w)
+	struct device *dev;
+	int ia;
+	u_short w;
+{
+	struct ggbus_device *gd = (struct ggbus_device *)dev;
+
+	*(volatile u_short *)(gd->gd_zargs.va + GG2_MEMORY_OFFSET + 2 * ia) = swap(w);
+}
+
+u_short
+ggbusldw(dev, ia)
+	struct device *dev;
+	int ia;
+{
+	struct ggbus_device *gd = (struct ggbus_device *)dev;
+	u_short retval =
+	    swap(*(volatile u_short *)(gd->gd_zargs.va + GG2_MEMORY_OFFSET + 2 * ia));
+
+#ifdef DEBUG
+	if (ggdebug)
+		printf("ldw 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
+static ggbus_int_map[] = {
+    0, 0, 0, 0, GG2_IRQ3, GG2_IRQ4, GG2_IRQ5, GG2_IRQ6, GG2_IRQ7, 0,
+    GG2_IRQ9, GG2_IRQ10, GG2_IRQ11, GG2_IRQ12, 0, GG2_IRQ14, GG2_IRQ15
+};
+
+struct ggintr_desc {
+	struct	isr gid_isr;
+	int	gid_mask;
+	int	(*gid_fun)(void *);
+	void	*gid_arg;
+};
+
+static struct ggintr_desc *ggid[16];	/* XXX */
+
+int
+ggbusintr(gid)
+	struct ggintr_desc *gid;
+{
+	return (GG2_GET_STATUS (ggbusp->gd_zargs.va) & gid->gid_mask) ?
+	    (*gid->gid_fun)(gid->gid_arg) : 0;
+}
+
+void *
+ggbus_establish_intr(intr, type, level, ih_fun, ih_arg)
+	int intr;
+	int type;
+	int level;
+	int (*ih_fun)(void *);
+	void *ih_arg;
+{
+	if (ggid[intr]) {
+		log(LOG_WARNING, "ISA interrupt %d already handled\n", intr);
+		return 0;
+	}
+	MALLOC(ggid[intr], struct ggintr_desc *, sizeof(struct ggintr_desc),
+	    M_DEVBUF, M_WAITOK);
+	ggid[intr]->gid_isr.isr_intr = ggbusintr;
+	ggid[intr]->gid_isr.isr_arg = ggid[intr];
+	ggid[intr]->gid_isr.isr_ipl = 6;
+	ggid[intr]->gid_isr.isr_mapped_ipl = level;
+	ggid[intr]->gid_mask = 1 << ggbus_int_map[intr + 1];
+	ggid[intr]->gid_fun = ih_fun;
+	ggid[intr]->gid_arg = ih_arg;
+	add_isr(&ggid[intr]->gid_isr);
+	return &ggid[intr];
+}
+
+void
+ggbus_disestablish_intr(handler)
+	void  *handler;
+{
+	struct ggintr_desc **gid = handler;
+
+	remove_isr(&(*gid)->gid_isr);
+	FREE(*gid, M_DEVBUF);
+	*gid = 0;
+}
diff --git a/sys/arch/amiga/isa/ggbus_pio.c b/sys/arch/amiga/isa/ggbus_pio.c
new file mode 100644
index 00000000000..c1079be64ea
--- /dev/null
+++ b/sys/arch/amiga/isa/ggbus_pio.c
@@ -0,0 +1,114 @@
+/*	$NetBSD: ggbus_pio.c,v 1.1 1995/08/04 14:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1995 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/types.h>
+#include <sys/device.h>
+
+#include <machine/pio.h>
+
+#include <dev/isa/isavar.h>
+
+#include <amiga/amiga/isr.h>
+#include <amiga/dev/zbusvar.h>
+#include <amiga/isa/isa_machdep.h>
+#include <amiga/isa/ggbusreg.h>
+#include <amiga/isa/ggbusvar.h>
+
+extern struct ggbus_device *ggbusp;
+
+void		ggbus_outb __P((int, u_int8_t));
+u_int8_t	ggbus_inb __P((int));
+void		ggbus_outw __P((int, u_int16_t));
+u_int16_t	ggbus_inw __P((int));
+
+struct isa_pio_fcns ggbus_pio_fcns = {
+	ggbus_inb,	isa_insb,
+	ggbus_inw,	isa_insw,
+	0 /* ggbus_inl */,	0 /* ggbus_insl */,
+	ggbus_outb,	isa_outsb,
+	ggbus_outw,	isa_outsw,
+	0 /* ggbus_outl */,	0 /* ggbus_outsl */,
+};
+
+void
+ggbus_outb(ia, b)
+	int ia;
+	u_int8_t b;
+{
+#ifdef DEBUG
+	if (ggdebug)
+		printf("outb 0x%x,0x%x\n", ia, b);
+#endif
+	*(volatile u_int8_t *)(ggbusp->gd_zargs.va + 2 * ia + 1) = b;
+}
+
+u_int8_t
+ggbus_inb(ia)
+	int ia;
+{
+	u_int8_t retval =
+	    *(volatile u_int8_t *)(ggbusp->gd_zargs.va + 2 * ia + 1);
+
+
+#ifdef DEBUG
+	if (ggdebug)
+		printf("inb 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
+void
+ggbus_outw(ia, w)
+	int ia;
+	u_int16_t w;
+{
+#ifdef DEBUG
+	if (ggdebug)
+		printf("outw 0x%x,0x%x\n", ia, w);
+#endif
+	*(volatile u_int16_t *)(ggbusp->gd_zargs.va + 2 * ia) = swap (w);
+}
+
+u_int16_t
+ggbus_inw(ia)
+	int ia;
+{
+	u_int16_t retval =
+            swap(*(volatile u_int16_t *)(ggbusp->gd_zargs.va + 2 * ia));
+
+
+#ifdef DEBUG
+	if (ggdebug)
+		printf("inw 0x%x => 0x%x\n", ia, retval);
+#endif
+	return retval;
+}
+
diff --git a/sys/arch/amiga/isa/ggbusreg.h b/sys/arch/amiga/isa/ggbusreg.h
new file mode 100644
index 00000000000..d835dca389c
--- /dev/null
+++ b/sys/arch/amiga/isa/ggbusreg.h
@@ -0,0 +1,67 @@
+/*	$NetBSD: ggbusreg.h,v 1.1 1994/07/08 23:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1994 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _GGBUSREG_H_
+#define _GGBUSREG_H_
+
+#define GG2_MEMORY_OFFSET (0x20000 - 2 * 0x90000)
+
+#define GG2_STATUS 0x18000
+#define GG2_GET_STATUS(va) (*(volatile u_short *)((va) + GG2_STATUS))
+
+#define GG2_MASTER 0
+#define GG2_WAIT 1
+#define GG2_IRQ3 2
+#define GG2_IRQ4 3
+#define GG2_IRQ5 4
+#define GG2_IRQ6 5
+#define GG2_IRQ7 6
+#define GG2_IRQ9 7
+#define GG2_IRQ10 8
+#define GG2_IRQ11 9
+#define GG2_IRQ12 10
+#define GG2_IRQ14 11
+#define GG2_IRQ15 12
+#define GG2_IRQ_MASK 0x1ffc
+#define GG2_GET_INT_STATUS(va) (GG2_GET_STATUS(va) & GG2_IRQ_MASK)
+
+#define GG2_INT_CTRL 0x18002
+#define GG2_DISABLE_INTS(va) (*(volatile u_short *)((va) + GG2_INT_CTRL))
+#define GG2_ENABLE_INTS(va) (*(volatile u_short *)((va) + GG2_INT_CTRL) = 0)
+
+#define GG2_WAIT_CTRL 0x18004
+#define GG2_TOGGLE_WAIT(va) (*(volatile u_char *)((va) + GG2_WAIT_CTRL))
+#define GG2_ENABLE_WAIT(va) \
+    while ((GG2_GET_STATUS(va) & 1 << GG2_WAIT) == 0) GG2_TOGGLE_WAIT(va)
+#define GG2_DISABLE_WAIT(va) \
+    while (GG2_GET_STATUS(va) & 1 << GG2_WAIT) GG2_TOGGLE_WAIT(va)
+
+#endif
diff --git a/sys/arch/amiga/isa/ggbusvar.h b/sys/arch/amiga/isa/ggbusvar.h
new file mode 100644
index 00000000000..1036b58411b
--- /dev/null
+++ b/sys/arch/amiga/isa/ggbusvar.h
@@ -0,0 +1,50 @@
+/*	$NetBSD: ggbusvar.h,v 1.1 1994/07/08 23:32:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1994, 1995 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _GGBUSVAR_H_
+#define _GGBUSVAR_H_
+
+struct ggbus_device {
+	struct	device gd_dev;
+	struct	zbus_args gd_zargs;
+	struct	isa_link gd_link;
+	int	(*gd_ifunc[16])();
+	void	*gd_iarg[16];
+	int	gd_ipri[16];
+	int	gd_imask;
+	struct	isr gd_isr;
+};
+
+extern int ggdebug;
+
+#endif
+
+
diff --git a/sys/arch/amiga/isa/if_isaed.c b/sys/arch/amiga/isa/if_isaed.c
new file mode 100644
index 00000000000..a97e746edac
--- /dev/null
+++ b/sys/arch/amiga/isa/if_isaed.c
@@ -0,0 +1,2321 @@
+/*	$NetBSD: if_isaed.c,v 1.7 1994/11/28 21:47:38 root Exp $	*/
+
+/*
+ * Copyright (c) 1994, 1995 Niklas Hallqvist.
+ * All rights reserved.
+ *
+ * Amiga adaptation based on:
+ *
+ * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
+ * adapters.
+ *
+ * Copyright (c) 1994, 1995 Charles Hannum.
+ * All rights reserved.
+ *
+ * Copyright (C) 1993, David Greenman.  This software may be used, modified,
+ * copied, distributed, and sold, in both source and binary form provided that
+ * the above copyright and these terms are retained.  Under no circumstances is
+ * the author responsible for the proper functioning of this software, nor does
+ * the author assume any responsibility for damages incurred with its use.
+ *
+ * Currently supports the Western Digital/SMC 8003 and 8013 series, the SMC
+ * Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, and a variety of
+ * similar clones.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+#include <net/netisr.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#ifdef NS
+#include <netns/ns.h>
+#include <netns/ns_if.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+#endif
+
+#include <machine/cpu.h>
+#include <machine/pio.h>
+
+#include <dev/isa/isareg.h>
+#include <dev/isa/isavar.h>
+#include <dev/isa/if_edreg.h>
+
+#define ED_BYTE_ORDER LITTLE_ENDIAN
+#include <dev/ic/dp8390reg.h>
+
+#include <amiga/isa/isa_machdep.h>	/* XXX USES ISA HOLE DIRECTLY */
+
+/*
+ * isaed_softc: per line info and status
+ */
+struct isaed_softc {
+	struct	device sc_dev;
+	void *sc_ih;
+
+	struct	arpcom sc_arpcom;	/* ethernet common */
+
+	char	*type_str;	/* pointer to type string */
+	u_char	vendor;		/* interface vendor */
+	u_char	type;		/* interface type code */
+
+	int	asic_addr;	/* ASIC I/O bus address */
+	int	nic_addr;	/* NIC (DS8390) I/O bus address */
+
+/*
+ * The following 'proto' variable is part of a work-around for 8013EBT asics
+ * being write-only.  It's sort of a prototype/shadow of the real thing.
+ */
+	u_char	wd_laar_proto;
+/*
+ * This `proto' variable is so we can turn MENB on and off without reading
+ * the value back from the card all the time.
+ */
+	u_char	wd_msr_proto;
+	u_char	cr_proto;	/* values always set in CR */
+	u_char	isa16bit;	/* width of access to card 0=8 or 1=16 */
+	u_char	is790;		/* set by probe if NIC is a 790 */
+
+	caddr_t	mem_start;	/* NIC memory start address */
+	caddr_t	mem_end;	/* NIC memory end address */
+	u_long	mem_size;	/* total NIC memory size */
+	caddr_t	mem_ring;	/* start of RX ring-buffer (in NIC mem) */
+
+	u_char	mem_shared;	/* NIC memory is shared with host */
+	u_char	txb_cnt;	/* number of transmit buffers */
+	u_char	txb_inuse;	/* number of transmit buffers active */
+
+	u_char 	txb_new;	/* pointer to where new buffer will be added */
+	u_char	txb_next_tx;	/* pointer to next buffer ready to xmit */
+	u_short	txb_len[8];	/* buffered xmit buffer lengths */
+	u_char	tx_page_start;	/* first page of TX buffer area */
+	u_char	rec_page_start;	/* first page of RX ring-buffer */
+	u_char	rec_page_stop;	/* last page of RX ring-buffer */
+	u_char	next_packet;	/* pointer to next unread RX packet */
+};
+
+int isaedprobe __P((struct device *, void *, void *));
+void isaedattach __P((struct device *, struct device *, void *));
+int isaedintr __P((void *));
+int isaedioctl __P((struct ifnet *, u_long, caddr_t));
+void isaedstart __P((struct ifnet *));
+void isaedwatchdog __P((int));
+void isaedreset __P((struct isaed_softc *));
+void isaedinit __P((struct isaed_softc *));
+void isaedstop __P((struct isaed_softc *));
+
+#define inline	/* XXX for debugging porpoises */
+
+void isaed_getmcaf __P((struct arpcom *, u_long *));
+void isaedread __P((struct isaed_softc *, caddr_t, int));
+struct mbuf *isaedget __P((struct isaed_softc *, caddr_t, int));
+static inline void isaed_rint __P((struct isaed_softc *));
+static inline void isaed_xmit __P((struct isaed_softc *));
+static inline caddr_t isaed_ring_copy __P((struct isaed_softc *, caddr_t,
+					   caddr_t, u_short));
+
+void isaed_pio_readmem __P((struct isaed_softc *, u_short, caddr_t, u_short));
+void isaed_pio_writemem __P((struct isaed_softc *, caddr_t, u_short, u_short));
+u_short isaed_pio_write_mbufs __P((struct isaed_softc *, struct mbuf *, u_short));
+
+#ifdef ISAED_DEBUG
+int isaeddebug = 0;
+#endif
+int isaedprobes = 7;
+
+struct cfdriver isaedcd = {
+	NULL, "isaed", isaedprobe, isaedattach, DV_IFNET, sizeof(struct isaed_softc)
+};
+
+#define	ETHER_MIN_LEN	64
+#define ETHER_MAX_LEN	1518
+#define	ETHER_ADDR_LEN	6
+
+#define	NIC_PUT(sc, off, val)	outb(sc->nic_addr + off, val)
+#define	NIC_GET(sc, off)	inb(sc->nic_addr + off)
+
+/*
+ * Determine if the device is present.
+ */
+int
+isaedprobe(parent, match, aux)
+	struct device *parent;
+	void *match, *aux;
+{
+	struct isaed_softc *sc = match;
+	struct cfdata *cf = sc->sc_dev.dv_cfdata;
+	struct isa_attach_args *ia = aux;
+
+	if ((isaedprobes & 1) && isaed_probe_WD80x3(sc, cf, ia))
+		return (1);
+	if ((isaedprobes & 2) && isaed_probe_3Com(sc, cf, ia))
+		return (1);
+	if ((isaedprobes & 4) && isaed_probe_Novell(sc, cf, ia))
+		return (1);
+	return (0);
+}
+
+/*
+ * Generic probe routine for testing for the existance of a DS8390.  Must be
+ * called after the NIC has just been reset.  This routine works by looking at
+ * certain register values that are guaranteed to be initialized a certain way
+ * after power-up or reset.  Seems not to currently work on the 83C690.
+ *
+ * Specifically:
+ *
+ *	Register			reset bits	set bits
+ *	Command Register (CR)		TXP, STA	RD2, STP
+ *	Interrupt Status (ISR)				RST
+ *	Interrupt Mask (IMR)		All bits
+ *	Data Control (DCR)				LAS
+ *	Transmit Config. (TCR)		LB1, LB0
+ *
+ * We only look at the CR and ISR registers, however, because looking at the
+ * others would require changing register pages (which would be intrusive if
+ * this isn't an 8390).
+ *
+ * Return 1 if 8390 was found, 0 if not.
+ */
+int
+isaed_probe_generic8390(sc)
+	struct isaed_softc *sc;
+{
+
+	if ((NIC_GET(sc, ED_P0_CR) &
+	     (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
+	    (ED_CR_RD2 | ED_CR_STP))
+		return (0);
+	if ((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
+		return (0);
+
+	return (1);
+}
+
+int isaed_wd584_irq[] = { 9, 3, 5, 7, 10, 11, 15, 4 };
+int isaed_wd790_irq[] = { IRQUNK, 9, 3, 5, 7, 10, 11, 15 };
+
+/*
+ * Probe and vendor-specific initialization routine for SMC/WD80x3 boards.
+ */
+int
+isaed_probe_WD80x3(sc, cf, ia)
+	struct isaed_softc *sc;
+	struct cfdata *cf;
+	struct isa_attach_args *ia;
+{
+	int i;
+	u_int memsize;
+	u_char iptr, isa16bit, sum;
+
+	sc->asic_addr = ia->ia_iobase;
+	sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
+	sc->is790 = 0;
+
+#ifdef TOSH_ETHER
+	outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
+	delay(10000);
+#endif
+
+	/*
+	 * Attempt to do a checksum over the station address PROM.  If it
+	 * fails, it's probably not a SMC/WD board.  There is a problem with
+	 * this, though: some clone WD boards don't pass the checksum test.
+	 * Danpex boards for one.
+	 */
+	for (sum = 0, i = 0; i < 8; ++i) {
+		u_char c = inb(sc->asic_addr + ED_WD_PROM + i);
+
+		sum += c;
+#ifdef ISAED_DEBUG
+		if (isaeddebug)
+			printf("inb(0x%x) = 0x%02x -> sum = %d\n",
+			    sc->asic_addr + ED_WD_PROM + i, c, sum);
+#endif
+	}
+
+	if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
+		/*
+		 * Checksum is invalid.  This often happens with cheap WD8003E
+		 * clones.  In this case, the checksum byte (the eighth byte)
+		 * seems to always be zero.
+		 */
+		if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
+		    inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
+			return (0);
+	}
+
+	/* Reset card to force it into a known state. */
+#ifdef TOSH_ETHER
+	outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
+#else
+	outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
+#endif
+	delay(100);
+	outb(sc->asic_addr + ED_WD_MSR,
+	    inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
+	/* Wait in the case this card is reading it's EEROM. */
+	delay(5000);
+
+	sc->vendor = ED_VENDOR_WD_SMC;
+	sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
+
+	/* Set initial values for width/size. */
+	memsize = 8192;
+	isa16bit = 0;
+	switch (sc->type) {
+	case ED_TYPE_WD8003S:
+		sc->type_str = "WD8003S";
+		break;
+	case ED_TYPE_WD8003E:
+		sc->type_str = "WD8003E";
+		break;
+	case ED_TYPE_WD8003EB:
+		sc->type_str = "WD8003EB";
+		break;
+	case ED_TYPE_WD8003W:
+		sc->type_str = "WD8003W";
+		break;
+	case ED_TYPE_WD8013EBT:
+		sc->type_str = "WD8013EBT";
+		memsize = 16384;
+		isa16bit = 1;
+		break;
+	case ED_TYPE_WD8013W:
+		sc->type_str = "WD8013W";
+		memsize = 16384;
+		isa16bit = 1;
+		break;
+	case ED_TYPE_WD8013EP:		/* also WD8003EP */
+		if (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) {
+			isa16bit = 1;
+			memsize = 16384;
+			sc->type_str = "WD8013EP";
+		} else
+			sc->type_str = "WD8003EP";
+		break;
+	case ED_TYPE_WD8013WC:
+		sc->type_str = "WD8013WC";
+		memsize = 16384;
+		isa16bit = 1;
+		break;
+	case ED_TYPE_WD8013EBP:
+		sc->type_str = "WD8013EBP";
+		memsize = 16384;
+		isa16bit = 1;
+		break;
+	case ED_TYPE_WD8013EPC:
+		sc->type_str = "WD8013EPC";
+		memsize = 16384;
+		isa16bit = 1;
+		break;
+	case ED_TYPE_SMC8216C:
+		sc->type_str = "SMC8216/SMC8216C";
+		memsize = 16384;
+		isa16bit = 1;
+		sc->is790 = 1;
+		break;
+	case ED_TYPE_SMC8216T:
+		sc->type_str = "SMC8216T";
+		memsize = 16384;
+		isa16bit = 1;
+		sc->is790 = 1;
+		break;
+#ifdef TOSH_ETHER
+	case ED_TYPE_TOSHIBA1:
+		sc->type_str = "Toshiba1";
+		memsize = 32768;
+		isa16bit = 1;
+		break;
+	case ED_TYPE_TOSHIBA4:
+		sc->type_str = "Toshiba4";
+		memsize = 32768;
+		isa16bit = 1;
+		break;
+#endif
+	default:
+		sc->type_str = NULL;
+		break;
+	}
+	/*
+	 * Make some adjustments to initial values depending on what is found
+	 * in the ICR.
+	 */
+	if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) &&
+#ifdef TOSH_ETHER
+	    (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) &&
+#endif
+	    ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
+		isa16bit = 0;
+		memsize = 8192;
+	}
+
+#ifdef ISAED_DEBUG
+	if (isaeddebug) {
+		printf("type=%x type_str=%s isa16bit=%d memsize=%d ia_msize=%d\n",
+		    sc->type, sc->type_str ?: "unknown", isa16bit, memsize,
+		    ia->ia_msize);
+		for (i = 0; i < 8; i++)
+			printf("%x -> %x\n", i, inb(sc->asic_addr + i));
+	}
+#endif
+	/* Allow the user to override the autoconfiguration. */
+	if (ia->ia_msize)
+		memsize = ia->ia_msize;
+	/*
+	 * (Note that if the user specifies both of the following flags that
+	 * '8-bit' mode intentionally has precedence.)
+	 */
+	if (cf->cf_flags & ED_FLAGS_FORCE_16BIT_MODE)
+		isa16bit = 1;
+	if (cf->cf_flags & ED_FLAGS_FORCE_8BIT_MODE)
+		isa16bit = 0;
+
+	/*
+	 * If possible, get the assigned interrupt number from the card and
+	 * use it.
+	 */
+	if (sc->is790) {
+		u_char x;
+		/* Assemble together the encoded interrupt number. */
+		outb(ia->ia_iobase + ED_WD790_HWR,
+		    inb(ia->ia_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
+		x = inb(ia->ia_iobase + ED_WD790_GCR);
+		iptr = ((x & ED_WD790_GCR_IR2) >> 4) |
+		    ((x & (ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2);
+		outb(ia->ia_iobase + ED_WD790_HWR,
+		    inb(ia->ia_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+		/*
+		 * Translate it using translation table, and check for
+		 * correctness.
+		 */
+		if (ia->ia_irq != IRQUNK) {
+			if (ia->ia_irq != isaed_wd790_irq[iptr]) {
+				printf("%s: irq mismatch; kernel configured %d != board configured %d\n",
+				    sc->sc_dev.dv_xname, ia->ia_irq,
+				    isaed_wd790_irq[iptr]);
+				return (0);
+			}
+		} else
+			ia->ia_irq = isaed_wd790_irq[iptr];
+		/* Enable the interrupt. */
+		outb(ia->ia_iobase + ED_WD790_ICR,
+		    inb(ia->ia_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
+	} else if (sc->type & ED_WD_SOFTCONFIG) {
+		/* Assemble together the encoded interrupt number. */
+		iptr = (inb(ia->ia_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
+		    ((inb(ia->ia_iobase + ED_WD_IRR) &
+		      (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
+		/*
+		 * Translate it using translation table, and check for
+		 * correctness.
+		 */
+		if (ia->ia_irq != IRQUNK) {
+			if (ia->ia_irq != isaed_wd584_irq[iptr]) {
+				printf("%s: irq mismatch; kernel configured %d != board configured %d\n",
+				    sc->sc_dev.dv_xname, ia->ia_irq,
+				    isaed_wd584_irq[iptr]);
+				return (0);
+			}
+		} else
+			ia->ia_irq = isaed_wd584_irq[iptr];
+		/* Enable the interrupt. */
+		outb(ia->ia_iobase + ED_WD_IRR,
+		    inb(ia->ia_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
+	} else {
+		if (ia->ia_irq == IRQUNK) {
+			printf("%s: %s does not have soft configuration\n",
+			    sc->sc_dev.dv_xname, sc->type_str);
+			return (0);
+		}
+	}
+
+	/* XXX Figure out the shared memory address. */
+
+	sc->isa16bit = isa16bit;
+	sc->mem_shared = 1;
+	ia->ia_msize = memsize;
+	sc->mem_start = ISA_HOLE_VADDR(ia->ia_maddr);
+
+	/* Allocate one xmit buffer if < 16k, two buffers otherwise. */
+	if ((memsize < 16384) || (cf->cf_flags & ED_FLAGS_NO_MULTI_BUFFERING))
+		sc->txb_cnt = 1;
+	else
+		sc->txb_cnt = 2;
+
+	sc->tx_page_start = ED_WD_PAGE_OFFSET;
+	sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
+	sc->rec_page_stop = sc->tx_page_start + (memsize >> ED_PAGE_SHIFT);
+	sc->mem_ring = sc->mem_start + (sc->rec_page_start << ED_PAGE_SHIFT);
+	sc->mem_size = memsize;
+	sc->mem_end = sc->mem_start + memsize;
+
+	/* Get station address from on-board ROM. */
+	for (i = 0; i < ETHER_ADDR_LEN; ++i)
+		sc->sc_arpcom.ac_enaddr[i] =
+		    inb(sc->asic_addr + ED_WD_PROM + i);
+
+	/*
+	 * Set upper address bits and 8/16 bit access to shared memory.
+	 */
+	if (isa16bit) {
+		if (sc->is790) {
+			sc->wd_laar_proto =
+			    inb(sc->asic_addr + ED_WD_LAAR) &
+			    ~ED_WD_LAAR_M16EN;
+		} else {
+			sc->wd_laar_proto =
+			    ED_WD_LAAR_L16EN |
+			    ((kvtop(sc->mem_start) >> 19) &
+			    ED_WD_LAAR_ADDRHI);
+		}
+		outb(sc->asic_addr + ED_WD_LAAR,
+		    sc->wd_laar_proto | ED_WD_LAAR_M16EN);
+	} else  {
+		if ((sc->type & ED_WD_SOFTCONFIG) ||
+#ifdef TOSH_ETHER
+		    (sc->type == ED_TYPE_TOSHIBA1) ||
+		    (sc->type == ED_TYPE_TOSHIBA4) ||
+#endif
+		    (sc->type == ED_TYPE_WD8013EBT) && !sc->is790) {
+			sc->wd_laar_proto =
+			    ((kvtop(sc->mem_start) >> 19) &
+			    ED_WD_LAAR_ADDRHI);
+			outb(sc->asic_addr + ED_WD_LAAR,
+			    sc->wd_laar_proto);
+		}
+	}
+
+	/*
+	 * Set address and enable interface shared memory.
+	 */
+	if (!sc->is790) {
+#ifdef TOSH_ETHER
+		outb(sc->asic_addr + ED_WD_MSR + 1,
+		    ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
+		outb(sc->asic_addr + ED_WD_MSR + 2,
+		    ((kvtop(sc->mem_start) >> 16) & 0x0f));
+		sc->wd_msr_proto = ED_WD_MSR_POW;
+#else
+		sc->wd_msr_proto =
+		    (kvtop(sc->mem_start) >> 13) & ED_WD_MSR_ADDR;
+#endif
+		sc->cr_proto = ED_CR_RD2;
+	} else {
+		outb(sc->asic_addr + 0x04,
+		    inb(sc->asic_addr + 0x04) | 0x80);
+		outb(sc->asic_addr + 0x0b,
+		    ((kvtop(sc->mem_start) >> 13) & 0x0f) |
+		    ((kvtop(sc->mem_start) >> 11) & 0x40) |
+		    (inb(sc->asic_addr + 0x0b) & 0xb0));
+		outb(sc->asic_addr + 0x04,
+		    inb(sc->asic_addr + 0x04) & ~0x80);
+		sc->wd_msr_proto = 0x00;
+		sc->cr_proto = 0;
+	}
+	outb(sc->asic_addr + ED_WD_MSR,
+	    sc->wd_msr_proto | ED_WD_MSR_MENB);
+
+	(void) inb(0x84);
+	(void) inb(0x84);
+
+	/* Now zero memory and verify that it is clear. */
+	bzero(sc->mem_start, memsize);
+
+	for (i = 0; i < memsize; ++i)
+		if (sc->mem_start[i]) {
+			printf("%s: failed to clear shared memory at %x - check configuration\n",
+			    sc->sc_dev.dv_xname,
+			    kvtop(sc->mem_start + i));
+
+			/* Disable 16 bit access to shared memory. */
+			outb(sc->asic_addr + ED_WD_MSR,
+			    sc->wd_msr_proto);
+			if (isa16bit)
+				outb(sc->asic_addr + ED_WD_LAAR,
+				    sc->wd_laar_proto);
+			(void) inb(0x84);
+			(void) inb(0x84);
+			return (0);
+		}
+
+	/*
+	 * Disable 16bit access to shared memory - we leave it disabled
+	 * so that 1) machines reboot properly when the board is set 16
+	 * 16 bit mode and there are conflicting 8bit devices/ROMS in
+	 * the same 128k address space as this boards shared memory,
+	 * and 2) so that other 8 bit devices with shared memory can be
+	 * used in this 128k region, too.
+	 */
+	outb(sc->asic_addr + ED_WD_MSR, sc->wd_msr_proto);
+	if (isa16bit)
+		outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
+	(void) inb(0x84);
+	(void) inb(0x84);
+
+	ia->ia_iosize = ED_WD_IO_PORTS;
+	return (1);
+}
+
+int isaed_3com_iobase[] = {0x2e0, 0x2a0, 0x280, 0x250, 0x350, 0x330, 0x310, 0x300};
+int isaed_3com_maddr[] = {MADDRUNK, MADDRUNK, MADDRUNK, MADDRUNK, 0xc8000, 0xcc000, 0xd8000, 0xdc000};
+#if 0
+int isaed_3com_irq[] = {IRQUNK, IRQUNK, IRQUNK, IRQUNK, 9, 3, 4, 5};
+#endif
+
+/*
+ * Probe and vendor-specific initialization routine for 3Com 3c503 boards.
+ */
+int
+isaed_probe_3Com(sc, cf, ia)
+	struct isaed_softc *sc;
+	struct cfdata *cf;
+	struct isa_attach_args *ia;
+{
+	int i;
+	u_int memsize;
+	u_char isa16bit, sum, x;
+	int ptr;
+
+	sc->asic_addr = ia->ia_iobase + ED_3COM_ASIC_OFFSET;
+	sc->nic_addr = ia->ia_iobase + ED_3COM_NIC_OFFSET;
+
+	/*
+	 * Verify that the kernel configured I/O address matches the board
+	 * configured address.
+	 *
+	 * This is really only useful to see if something that looks like the
+	 * board is there; after all, we are already talking it at that
+	 * address.
+	 */
+	x = inb(sc->asic_addr + ED_3COM_BCFR);
+	if (x == 0 || (x & (x - 1)) != 0)
+		return (0);
+	ptr = ffs(x) - 1;
+	if (ia->ia_iobase != IOBASEUNK) {
+		if (ia->ia_iobase != isaed_3com_iobase[ptr]) {
+			printf("%s: %s mismatch; kernel configured %x != board configured %x\n",
+			    "iobase", sc->sc_dev.dv_xname, ia->ia_iobase,
+			    isaed_3com_iobase[ptr]);
+			return (0);
+		}
+	} else
+		ia->ia_iobase = isaed_3com_iobase[ptr];
+
+	x = inb(sc->asic_addr + ED_3COM_PCFR);
+	if (x == 0 || (x & (x - 1)) != 0)
+		return (0);
+	ptr = ffs(x) - 1;
+	if (ia->ia_maddr != MADDRUNK) {
+		if (ia->ia_maddr != isaed_3com_maddr[ptr]) {
+			printf("%s: %s mismatch; kernel configured %x != board configured %x\n",
+			    "maddr", sc->sc_dev.dv_xname, ia->ia_maddr,
+			    isaed_3com_maddr[ptr]);
+			return (0);
+		}
+	} else
+		ia->ia_maddr = isaed_3com_maddr[ptr];
+
+#if 0
+	x = inb(sc->asic_addr + ED_3COM_IDCFR) & ED_3COM_IDCFR_IRQ;
+	if (x == 0 || (x & (x - 1)) != 0)
+		return (0);
+	ptr = ffs(x) - 1;
+	if (ia->ia_irq != IRQUNK) {
+		if (ia->ia_irq != isaed_3com_irq[ptr]) {
+			printf("%s: irq mismatch; kernel configured %d != board configured %d\n",
+			    sc->sc_dev.dv_xname, ia->ia_irq,
+			    isaed_3com_irq[ptr]);
+			return (0);
+		}
+	} else
+		ia->ia_irq = isaed_3com_irq[ptr];
+#endif
+
+	/*
+	 * Reset NIC and ASIC.  Enable on-board transceiver throughout reset
+	 * sequence because it'll lock up if the cable isn't connected if we
+	 * don't.
+	 */
+	outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
+
+	/* Wait for a while, then un-reset it. */
+	delay(50);
+
+	/*
+	 * The 3Com ASIC defaults to rather strange settings for the CR after a
+	 * reset - it's important to set it again after the following outb
+	 * (this is done when we map the PROM below).
+	 */
+	outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
+
+	/* Wait a bit for the NIC to recover from the reset. */
+	delay(5000);
+
+	sc->vendor = ED_VENDOR_3COM;
+	sc->type_str = "3c503";
+	sc->mem_shared = 1;
+	sc->cr_proto = ED_CR_RD2;
+
+	/*
+	 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
+	 * to it.
+	 */
+	memsize = 8192;
+
+	/*
+	 * Get station address from on-board ROM.
+	 *
+	 * First, map ethernet address PROM over the top of where the NIC
+	 * registers normally appear.
+	 */
+	outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
+
+	for (i = 0; i < ETHER_ADDR_LEN; ++i)
+		sc->sc_arpcom.ac_enaddr[i] = NIC_GET(sc, i);
+
+	/*
+	 * Unmap PROM - select NIC registers.  The proper setting of the
+	 * tranceiver is set in isaedinit so that the attach code is given a
+	 * chance to set the default based on a compile-time config option.
+	 */
+	outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
+
+	/* Determine if this is an 8bit or 16bit board. */
+
+	/* Select page 0 registers. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
+
+	/*
+	 * Attempt to clear WTS bit.  If it doesn't clear, then this is a
+	 * 16-bit board.
+	 */
+	NIC_PUT(sc, ED_P0_DCR, 0);
+
+	/* Select page 2 registers. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_2 | ED_CR_STP);
+
+	/* The 3c503 forces the WTS bit to a one if this is a 16bit board. */
+	if (NIC_GET(sc, ED_P2_DCR) & ED_DCR_WTS)
+		isa16bit = 1;
+	else
+		isa16bit = 0;
+
+	/* Select page 0 registers. */
+	NIC_PUT(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
+
+	sc->mem_start = ISA_HOLE_VADDR(ia->ia_maddr);
+	sc->mem_size = memsize;
+	sc->mem_end = sc->mem_start + memsize;
+
+	/*
+	 * We have an entire 8k window to put the transmit buffers on the
+	 * 16-bit boards.  But since the 16bit 3c503's shared memory is only
+	 * fast enough to overlap the loading of one full-size packet, trying
+	 * to load more than 2 buffers can actually leave the transmitter idle
+	 * during the load.  So 2 seems the best value.  (Although a mix of
+	 * variable-sized packets might change this assumption.  Nonetheless,
+	 * we optimize for linear transfers of same-size packets.)
+	 */
+	if (isa16bit) {
+ 		if (cf->cf_flags & ED_FLAGS_NO_MULTI_BUFFERING)
+			sc->txb_cnt = 1;
+		else
+			sc->txb_cnt = 2;
+
+		sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
+		sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
+		sc->rec_page_stop =
+		    (memsize >> ED_PAGE_SHIFT) + ED_3COM_RX_PAGE_OFFSET_16BIT;
+		sc->mem_ring = sc->mem_start;
+	} else {
+		sc->txb_cnt = 1;
+		sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
+		sc->rec_page_start =
+		    ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
+		sc->rec_page_stop =
+		    (memsize >> ED_PAGE_SHIFT) + ED_3COM_TX_PAGE_OFFSET_8BIT;
+		sc->mem_ring =
+		    sc->mem_start + (ED_TXBUF_SIZE << ED_PAGE_SHIFT);
+	}
+
+	sc->isa16bit = isa16bit;
+
+	/*
+	 * Initialize GA page start/stop registers.  Probably only needed if
+	 * doing DMA, but what the Hell.
+	 */
+	outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
+	outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
+
+	/* Set IRQ.  3c503 only allows a choice of irq 3-5 or 9. */
+	switch (ia->ia_irq) {
+	case 9:
+		outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
+		break;
+	case 3:
+		outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
+		break;
+	case 4:
+		outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
+		break;
+	case 5:
+		outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
+		break;
+	default:
+		printf("%s: invalid irq configuration (%d) must be 3-5 or 9 for 3c503\n",
+		    sc->sc_dev.dv_xname, ia->ia_irq);
+		return (0);
+	}
+
+	/*
+	 * Initialize GA configuration register.  Set bank and enable shared
+	 * mem.
+	 */
+	outb(sc->asic_addr + ED_3COM_GACFR,
+	    ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
+
+	/*
+	 * Initialize "Vector Pointer" registers. These gawd-awful things are
+	 * compared to 20 bits of the address on ISA, and if they match, the
+	 * shared memory is disabled. We set them to 0xffff0...allegedly the
+	 * reset vector.
+	 */
+	outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
+	outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
+	outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
+
+	/* Zero memory and verify that it is clear. */
+	zero_isa(sc->mem_start, memsize);
+
+	for (i = 0; i < memsize; ++i)
+		if (ldb(sc->mem_start + i)) {
+			printf("%s: failed to clear shared memory at %x - check configuration\n",
+			    sc->sc_dev.dv_xname, (int)(sc->mem_start + i));
+			return (0);
+		}
+
+	ia->ia_msize = memsize;
+	ia->ia_iosize = ED_3COM_IO_PORTS;
+	return (1);
+}
+
+/*
+ * Probe and vendor-specific initialization routine for NE1000/2000 boards.
+ */
+int
+isaed_probe_Novell(sc, cf, ia)
+	struct isaed_softc *sc;
+	struct cfdata *cf;
+	struct isa_attach_args *ia;
+{
+	u_int memsize, n;
+	u_char romdata[16], isa16bit = 0, tmp;
+	static u_char test_pattern[32] = "THIS is A memory TEST pattern";
+	u_char test_buffer[32];
+
+	sc->asic_addr = ia->ia_iobase + ED_NOVELL_ASIC_OFFSET;
+	sc->nic_addr = ia->ia_iobase + ED_NOVELL_NIC_OFFSET;
+
+	/* XXX - do Novell-specific probe here */
+
+	/* Reset the board. */
+#ifdef GWETHER
+	outb(sc->asic_addr + ED_NOVELL_RESET, 0);
+	delay(200);
+#endif /* GWETHER */
+	tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
+
+	/*
+	 * I don't know if this is necessary; probably cruft leftover from
+	 * Clarkson packet driver code. Doesn't do a thing on the boards I've
+	 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
+	 * non-invasive...but some boards don't seem to reset and I don't have
+	 * complete documentation on what the 'right' thing to do is...so we do
+	 * the invasive thing for now.  Yuck.]
+	 */
+	outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
+	delay(5000);
+
+	/*
+	 * This is needed because some NE clones apparently don't reset the NIC
+	 * properly (or the NIC chip doesn't reset fully on power-up)
+	 * XXX - this makes the probe invasive! ...Done against my better
+	 * judgement.  -DLG
+	 */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
+
+	delay(5000);
+
+	/* Make sure that we really have an 8390 based board. */
+	if (!isaed_probe_generic8390(sc))
+		return (0);
+
+	sc->vendor = ED_VENDOR_NOVELL;
+	sc->mem_shared = 0;
+	sc->cr_proto = ED_CR_RD2;
+	ia->ia_msize = 0;
+
+	/*
+	 * Test the ability to read and write to the NIC memory.  This has the
+	 * side affect of determining if this is an NE1000 or an NE2000.
+	 */
+
+	/*
+	 * This prevents packets from being stored in the NIC memory when the
+	 * readmem routine turns on the start bit in the CR.
+	 */
+	NIC_PUT(sc, ED_P0_RCR, ED_RCR_MON);
+
+	/* Temporarily initialize DCR for byte operations. */
+	NIC_PUT(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+
+	NIC_PUT(sc, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
+	NIC_PUT(sc, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
+
+	sc->isa16bit = 0;
+
+	/*
+	 * Write a test pattern in byte mode.  If this fails, then there
+	 * probably isn't any memory at 8k - which likely means that the board
+	 * is an NE2000.
+	 */
+	isaed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
+	isaed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
+
+	if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
+		/* not an NE1000 - try NE2000 */
+
+		NIC_PUT(sc, ED_P0_DCR,
+		    ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
+		NIC_PUT(sc, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
+		NIC_PUT(sc, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
+
+		sc->isa16bit = 1;
+
+		/*
+		 * Write a test pattern in word mode.  If this also fails, then
+		 * we don't know what this board is.
+		 */
+		isaed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
+		isaed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
+
+		if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
+			return (0); /* not an NE2000 either */
+
+		sc->type = ED_TYPE_NE2000;
+		sc->type_str = "NE2000";
+	} else {
+		sc->type = ED_TYPE_NE1000;
+		sc->type_str = "NE1000";
+	}
+
+	if (ia->ia_irq == IRQUNK) {
+		printf("%s: %s does not have soft configuration\n",
+		    sc->sc_dev.dv_xname, sc->type_str);
+		return (0);
+	}
+
+	/* 8k of memory plus an additional 8k if 16-bit. */
+	memsize = 8192 + sc->isa16bit * 8192;
+
+#if 0 /* probably not useful - NE boards only come two ways */
+	/* Allow kernel config file overrides. */
+	if (ia->ia_msize)
+		memsize = ia->ia_msize;
+#endif
+
+	/* NIC memory doesn't start at zero on an NE board. */
+	/* The start address is tied to the bus width. */
+	sc->mem_start = (caddr_t)(8192 + sc->isa16bit * 8192);
+	sc->tx_page_start = memsize >> ED_PAGE_SHIFT;
+
+#ifdef GWETHER
+	{
+		int x, i, mstart = 0;
+		char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
+
+		for (i = 0; i < ED_PAGE_SIZE; i++)
+			pbuf0[i] = 0;
+
+		/* Search for the start of RAM. */
+		for (x = 1; x < 256; x++) {
+			ed_pio_writemem(sc, pbuf0, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
+			ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
+			if (!bcmp(pbuf0, tbuf, ED_PAGE_SIZE)) {
+				for (i = 0; i < ED_PAGE_SIZE; i++)
+					pbuf[i] = 255 - x;
+				ed_pio_writemem(sc, pbuf, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
+				ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
+				if (!bcmp(pbuf, tbuf, ED_PAGE_SIZE)) {
+					mstart = x << ED_PAGE_SHIFT;
+					memsize = ED_PAGE_SIZE;
+					break;
+				}
+			}
+		}
+
+		if (mstart == 0) {
+			printf("%s: cannot find start of RAM\n",
+			    sc->sc_dev.dv_xname);
+			return (0);
+		}
+
+		/* Search for the end of RAM. */
+		for (++x; x < 256; x++) {
+			ed_pio_writemem(sc, pbuf0, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
+			ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
+			if (!bcmp(pbuf0, tbuf, ED_PAGE_SIZE)) {
+				for (i = 0; i < ED_PAGE_SIZE; i++)
+					pbuf[i] = 255 - x;
+				ed_pio_writemem(sc, pbuf, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
+				ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
+				if (!bcmp(pbuf, tbuf, ED_PAGE_SIZE))
+					memsize += ED_PAGE_SIZE;
+				else
+					break;
+			} else
+				break;
+		}
+
+		printf("%s: RAM start %x, size %d\n",
+		    sc->sc_dev.dv_xname, mstart, memsize);
+
+		sc->mem_start = (caddr_t)mstart;
+		sc->tx_page_start = mstart >> ED_PAGE_SHIFT;
+	}
+#endif /* GWETHER */
+
+	sc->mem_size = memsize;
+	sc->mem_end = sc->mem_start + memsize;
+
+	/*
+	 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
+	 * otherwise).
+	 */
+	if ((memsize < 16384) || (cf->cf_flags & ED_FLAGS_NO_MULTI_BUFFERING))
+		sc->txb_cnt = 1;
+	else
+		sc->txb_cnt = 2;
+
+	sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
+	sc->rec_page_stop = sc->tx_page_start + (memsize >> ED_PAGE_SHIFT);
+
+	sc->mem_ring =
+	    sc->mem_start + ((sc->txb_cnt * ED_TXBUF_SIZE) << ED_PAGE_SHIFT);
+
+	isaed_pio_readmem(sc, 0, romdata, 16);
+	for (n = 0; n < ETHER_ADDR_LEN; n++)
+		sc->sc_arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
+
+#ifdef GWETHER
+	if (sc->arpcom.ac_enaddr[2] == 0x86)
+		sc->type_str = "Gateway AT";
+#endif /* GWETHER */
+
+	/* Clear any pending interrupts that might have occurred above. */
+	NIC_PUT(sc, ED_P0_ISR, 0xff);
+
+	ia->ia_iosize = ED_NOVELL_IO_PORTS;
+	return (1);
+}
+
+/*
+ * Install interface into kernel networking data structures.
+ */
+void
+isaedattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct isaed_softc *sc = (void *)self;
+	struct isa_attach_args *ia = aux;
+	struct cfdata *cf = sc->sc_dev.dv_cfdata;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+
+	/* Set interface to stopped condition (reset). */
+	isaedstop(sc);
+
+	/* Initialize ifnet structure. */
+	ifp->if_unit = sc->sc_dev.dv_unit;
+	ifp->if_name = isaedcd.cd_name;
+	ifp->if_start = isaedstart;
+	ifp->if_ioctl = isaedioctl;
+	ifp->if_watchdog = isaedwatchdog;
+	ifp->if_flags =
+	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
+
+	/*
+	 * Set default state for LINK0 flag (used to disable the tranceiver
+	 * for AUI operation), based on compile-time config option.
+	 */
+	switch (sc->vendor) {
+	case ED_VENDOR_3COM:
+		if (cf->cf_flags & ED_FLAGS_DISABLE_TRANCEIVER)
+			ifp->if_flags |= IFF_LINK0;
+		break;
+	case ED_VENDOR_WD_SMC:
+		if ((sc->type & ED_WD_SOFTCONFIG) == 0)
+			break;
+		if ((inb(sc->asic_addr + ED_WD_IRR) & ED_WD_IRR_OUT2) == 0)
+			ifp->if_flags |= IFF_LINK0;
+		break;
+	}
+
+	/* Attach the interface. */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+	/* Print additional info when attached. */
+	printf(": address %s, ", ether_sprintf(sc->sc_arpcom.ac_enaddr));
+
+	if (sc->type_str)
+		printf("type %s ", sc->type_str);
+	else
+		printf("type unknown (0x%x) ", sc->type);
+
+	printf("%s", sc->isa16bit ? "(16-bit)" : "(8-bit)");
+
+	switch (sc->vendor) {
+	case ED_VENDOR_WD_SMC:
+		if ((sc->type & ED_WD_SOFTCONFIG) == 0)
+			break;
+	case ED_VENDOR_3COM:
+		if (ifp->if_flags & IFF_LINK0)
+			printf(" aui");
+		else
+			printf(" bnc");
+		break;
+	}
+
+	printf("\n");
+
+#if NBPFILTER > 0
+	bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+
+	sc->sc_ih = isa_intr_establish(ia->ia_irq, IST_EDGE, IPL_NET,
+	    isaedintr, sc);
+}
+
+/*
+ * Reset interface.
+ */
+void
+isaedreset(sc)
+	struct isaed_softc *sc;
+{
+	int s;
+
+	s = splimp();
+	isaedstop(sc);
+	isaedinit(sc);
+	splx(s);
+}
+
+/*
+ * Take interface offline.
+ */
+void
+isaedstop(sc)
+	struct isaed_softc *sc;
+{
+	int n = 5000;
+
+	/* Stop everything on the interface, and select page 0 registers. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
+
+	/*
+	 * Wait for interface to enter stopped state, but limit # of checks to
+	 * 'n' (about 5ms).  It shouldn't even take 5us on modern DS8390's, but
+	 * just in case it's an old one.
+	 */
+	while (((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
+}
+
+/*
+ * Device timeout/watchdog routine.  Entered if the device neglects to generate
+ * an interrupt after a transmit has been started on it.
+ */
+void
+isaedwatchdog(unit)
+	int unit;
+{
+	struct isaed_softc *sc = isaedcd.cd_devs[unit];
+
+	log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
+	++sc->sc_arpcom.ac_if.if_oerrors;
+
+	isaedreset(sc);
+}
+
+/*
+ * Initialize device.
+ */
+void
+isaedinit(sc)
+	struct isaed_softc *sc;
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	int i;
+	u_char command;
+	u_long mcaf[2];
+
+	/*
+	 * Initialize the NIC in the exact order outlined in the NS manual.
+	 * This init procedure is "mandatory"...don't change what or when
+	 * things happen.
+	 */
+
+	/* Reset transmitter flags. */
+	ifp->if_timer = 0;
+
+	sc->txb_inuse = 0;
+	sc->txb_new = 0;
+	sc->txb_next_tx = 0;
+
+	/* Set interface for page 0, remote DMA complete, stopped. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
+
+	if (sc->isa16bit) {
+		/*
+		 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
+		 * order=80x86, word-wide DMA xfers,
+		 */
+		NIC_PUT(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
+	} else {
+		/* Same as above, but byte-wide DMA xfers. */
+		NIC_PUT(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+	}
+
+	/* Clear remote byte count registers. */
+	NIC_PUT(sc, ED_P0_RBCR0, 0);
+	NIC_PUT(sc, ED_P0_RBCR1, 0);
+
+	/* Tell RCR to do nothing for now. */
+	NIC_PUT(sc, ED_P0_RCR, ED_RCR_MON);
+
+	/* Place NIC in internal loopback mode. */
+	NIC_PUT(sc, ED_P0_TCR, ED_TCR_LB0);
+
+	/* Set lower bits of byte addressable framing to 0. */
+	if (sc->is790)
+		NIC_PUT(sc, 0x09, 0);
+
+	/* Initialize receive buffer ring. */
+	NIC_PUT(sc, ED_P0_BNRY, sc->rec_page_start);
+	NIC_PUT(sc, ED_P0_PSTART, sc->rec_page_start);
+	NIC_PUT(sc, ED_P0_PSTOP, sc->rec_page_stop);
+
+	/*
+	 * Clear all interrupts.  A '1' in each bit position clears the
+	 * corresponding flag.
+	 */
+	NIC_PUT(sc, ED_P0_ISR, 0xff);
+
+	/*
+	 * Enable the following interrupts: receive/transmit complete,
+	 * receive/transmit error, and Receiver OverWrite.
+	 *
+	 * Counter overflow and Remote DMA complete are *not* enabled.
+	 */
+	NIC_PUT(sc, ED_P0_IMR,
+	    ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE |
+	    ED_IMR_OVWE);
+
+	/* Program command register for page 1. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
+
+	/* Copy out our station address. */
+	for (i = 0; i < ETHER_ADDR_LEN; ++i)
+		NIC_PUT(sc, ED_P1_PAR0 + i, sc->sc_arpcom.ac_enaddr[i]);
+
+	/* Set multicast filter on chip. */
+	isaed_getmcaf(&sc->sc_arpcom, mcaf);
+	for (i = 0; i < 8; i++)
+		NIC_PUT(sc, ED_P1_MAR0 + i, ((u_char *)mcaf)[i]);
+
+	/*
+	 * Set current page pointer to one page after the boundary pointer, as
+	 * recommended in the National manual.
+	 */
+	sc->next_packet = sc->rec_page_start + 1;
+	NIC_PUT(sc, ED_P1_CURR, sc->next_packet);
+
+	/* Program command register for page 0. */
+	NIC_PUT(sc, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
+
+	i = ED_RCR_AB | ED_RCR_AM;
+	if (ifp->if_flags & IFF_PROMISC) {
+		/*
+		 * Set promiscuous mode.  Multicast filter was set earlier so
+		 * that we should receive all multicast packets.
+		 */
+		i |= ED_RCR_PRO | ED_RCR_AR | ED_RCR_SEP;
+	}
+	NIC_PUT(sc, ED_P0_RCR, i);
+
+	/* Take interface out of loopback. */
+	NIC_PUT(sc, ED_P0_TCR, 0);
+
+	/*
+	 * If this is a 3Com board, the tranceiver must be software enabled
+	 * (there is no settable hardware default).
+	 */
+	switch (sc->vendor) {
+		u_char x;
+	case ED_VENDOR_3COM:
+		if (ifp->if_flags & IFF_LINK0)
+			outb(sc->asic_addr + ED_3COM_CR, 0);
+		else
+			outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
+		break;
+	case ED_VENDOR_WD_SMC:
+		if ((sc->type & ED_WD_SOFTCONFIG) == 0)
+			break;
+		x = inb(sc->asic_addr + ED_WD_IRR);
+		if (ifp->if_flags & IFF_LINK0)
+			x &= ~ED_WD_IRR_OUT2;
+		else
+			x |= ED_WD_IRR_OUT2;
+		outb(sc->asic_addr + ED_WD_IRR, x);
+		break;
+	}
+
+	/* Fire up the interface. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+
+	/* Set 'running' flag, and clear output active flag. */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	/* ...and attempt to start output. */
+	isaedstart(ifp);
+}
+
+/*
+ * This routine actually starts the transmission on the interface.
+ */
+static inline void
+isaed_xmit(sc)
+	struct isaed_softc *sc;
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	u_short len;
+
+	len = sc->txb_len[sc->txb_next_tx];
+
+	/* Set NIC for page 0 register access. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+
+	/* Set TX buffer start page. */
+	NIC_PUT(sc, ED_P0_TPSR, sc->tx_page_start +
+	    sc->txb_next_tx * ED_TXBUF_SIZE);
+
+	/* Set TX length. */
+	NIC_PUT(sc, ED_P0_TBCR0, len);
+	NIC_PUT(sc, ED_P0_TBCR1, len >> 8);
+
+	/* Set page 0, remote DMA complete, transmit packet, and *start*. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA);
+
+	/* Point to next transmit buffer slot and wrap if necessary. */
+	sc->txb_next_tx++;
+	if (sc->txb_next_tx == sc->txb_cnt)
+		sc->txb_next_tx = 0;
+
+	/* Set a timer just in case we never hear from the board again. */
+	ifp->if_timer = 2;
+}
+
+/*
+ * Start output on interface.
+ * We make two assumptions here:
+ *  1) that the current priority is set to splimp _before_ this code
+ *     is called *and* is returned to the appropriate priority after
+ *     return
+ *  2) that the IFF_OACTIVE flag is checked before this code is called
+ *     (i.e. that the output part of the interface is idle)
+ */
+void
+isaedstart(ifp)
+	struct ifnet *ifp;
+{
+	struct isaed_softc *sc = isaedcd.cd_devs[ifp->if_unit];
+	struct mbuf *m0, *m;
+	caddr_t buffer;
+	int len;
+
+	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+		return;
+
+outloop:
+	/* See if there is room to put another packet in the buffer. */
+	if (sc->txb_inuse == sc->txb_cnt) {
+		/* No room.  Indicate this to the outside world and exit. */
+		ifp->if_flags |= IFF_OACTIVE;
+		return;
+	}
+
+	IF_DEQUEUE(&ifp->if_snd, m0);
+	if (m0 == 0)
+		return;
+
+	/* We need to use m->m_pkthdr.len, so require the header */
+	if ((m0->m_flags & M_PKTHDR) == 0)
+		panic("edstart: no header mbuf");
+
+#if NBPFILTER > 0
+	/* Tap off here if there is a BPF listener. */
+	if (ifp->if_bpf)
+		bpf_mtap(ifp->if_bpf, m0);
+#endif
+
+	/* txb_new points to next open buffer slot. */
+	buffer = sc->mem_start + ((sc->txb_new * ED_TXBUF_SIZE) << ED_PAGE_SHIFT);
+
+	if (sc->mem_shared) {
+		/* Special case setup for 16 bit boards... */
+		switch (sc->vendor) {
+		/*
+		 * For 16bit 3Com boards (which have 16k of memory), we
+		 * have the xmit buffers in a different page of memory
+		 * ('page 0') - so change pages.
+		 */
+		case ED_VENDOR_3COM:
+			if (sc->isa16bit)
+				outb(sc->asic_addr + ED_3COM_GACFR,
+				    ED_3COM_GACFR_RSEL);
+			break;
+		/*
+		 * Enable 16bit access to shared memory on WD/SMC
+		 * boards.
+		 */
+		case ED_VENDOR_WD_SMC:
+			if (sc->isa16bit)
+				outb(sc->asic_addr + ED_WD_LAAR,
+				    sc->wd_laar_proto | ED_WD_LAAR_M16EN);
+			outb(sc->asic_addr + ED_WD_MSR,
+			    sc->wd_msr_proto | ED_WD_MSR_MENB);
+			(void) inb(0x84);
+			(void) inb(0x84);
+			break;
+		}
+
+		for (len = 0; m; m = m->m_next) {
+			copy_to_isa(mtod(m, caddr_t), buffer, m->m_len);
+			buffer += m->m_len;
+      	 		len += m->m_len;
+		}
+
+		/* Restore previous shared memory access. */
+		switch (sc->vendor) {
+		case ED_VENDOR_3COM:
+			if (sc->isa16bit)
+				outb(sc->asic_addr + ED_3COM_GACFR,
+				    ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
+			break;
+		case ED_VENDOR_WD_SMC:
+			outb(sc->asic_addr + ED_WD_MSR,
+			    sc->wd_msr_proto);
+			if (sc->isa16bit)
+				outb(sc->asic_addr + ED_WD_LAAR,
+				    sc->wd_laar_proto);
+			(void) inb(0x84);
+			(void) inb(0x84);
+			break;
+		}
+	} else
+		len = isaed_pio_write_mbufs(sc, m0, (long)buffer);
+
+	m_freem(m0);
+	sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN);
+#ifdef DDB
+		if (sc->next_packet < sc->rec_page_start || sc->next_packet >= sc->rec_page_stop)
+			Debugger();
+#endif
+
+	/* Start the first packet transmitting. */
+	if (sc->txb_inuse == 0)
+		isaed_xmit(sc);
+
+	/* Point to next buffer slot and wrap if necessary. */
+	if (++sc->txb_new == sc->txb_cnt)
+		sc->txb_new = 0;
+	sc->txb_inuse++;
+
+	/* Loop back to the top to possibly buffer more packets. */
+	goto outloop;
+}
+
+/*
+ * Ethernet interface receiver interrupt.
+ */
+static inline void
+isaed_rint(sc)
+	struct isaed_softc *sc;
+{
+	u_char boundary, current;
+	u_short len;
+	u_char nlen;
+	struct ed_ring packet_hdr;
+	caddr_t packet_ptr;
+
+loop:
+#ifdef DDB
+		if (sc->next_packet < sc->rec_page_start || sc->next_packet >= sc->rec_page_stop)
+			Debugger();
+#endif
+	/* Set NIC to page 1 registers to get 'current' pointer. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
+
+	/*
+	 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
+	 * it points to where new data has been buffered.  The 'CURR' (current)
+	 * register points to the logical end of the ring-buffer - i.e. it
+	 * points to where additional new data will be added.  We loop here
+	 * until the logical beginning equals the logical end (or in other
+	 * words, until the ring-buffer is empty).
+	 */
+	current = NIC_GET(sc, ED_P1_CURR);
+	if (sc->next_packet == current)
+		return;
+
+	/* Set NIC to page 0 registers to update boundary register. */
+	NIC_PUT(sc, ED_P1_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+
+	do {
+		/* Get pointer to this buffer's header structure. */
+		packet_ptr = sc->mem_ring +
+		    ((sc->next_packet - sc->rec_page_start) << ED_PAGE_SHIFT);
+
+		/*
+		 * The byte count includes a 4 byte header that was added by
+		 * the NIC.
+		 */
+		if (sc->mem_shared)
+			copy_from_isa(packet_ptr, &packet_hdr,
+			    sizeof(packet_hdr));
+		else
+			isaed_pio_readmem(sc, (long)packet_ptr,
+			    (caddr_t) &packet_hdr, sizeof(packet_hdr));
+		len = itohs(packet_hdr.count);
+#ifdef ISAED_DEBUG
+		if (isaeddebug) {
+			int i;
+			u_char buf[64];
+
+			if (sc->mem_shared)
+				copy_from_isa(((u_char *)packet_ptr + sizeof(struct ed_ring)), buf, 64);
+			else
+				isaed_pio_readmem(sc, (long)packet_ptr + sizeof(struct ed_ring),
+				    (caddr_t) buf, 64);
+			printf("pkt hdr len %d hdr %02x %02x %02x %02x pkt len %d\n",
+			    sizeof(packet_hdr), ((u_char *)&packet_hdr)[0],
+			    ((u_char *)&packet_hdr)[1], ((u_char *)&packet_hdr)[2],
+			    ((u_char *)&packet_hdr)[3], len);
+			for (i = 0; i < 64; i++)
+				printf("%02x%c", buf[i], i % 16 == 15 ? '\n' : ' ');
+		}
+#endif
+
+		/*
+		 * Try do deal with old, buggy chips that sometimes duplicate
+		 * the low byte of the length into the high byte.  We do this
+		 * by simply ignoring the high byte of the length and always
+		 * recalculating it.
+		 *
+		 * NOTE: sc->next_packet is pointing at the current packet.
+		 */
+		if (packet_hdr.next_packet >= sc->next_packet)
+			nlen = (packet_hdr.next_packet - sc->next_packet);
+		else
+			nlen = ((packet_hdr.next_packet - sc->rec_page_start) +
+				(sc->rec_page_stop - sc->next_packet));
+		--nlen;
+		if ((len & ED_PAGE_MASK) + sizeof(packet_hdr) > ED_PAGE_SIZE)
+			--nlen;
+		len = (len & ED_PAGE_MASK) | (nlen << ED_PAGE_SHIFT);
+#ifdef DIAGNOSTIC
+		if (len != itohs(packet_hdr.count)) {
+			printf("%s: length does not match next packet pointer\n",
+			    sc->sc_dev.dv_xname);
+			printf("%s: len %04x nlen %04x start %02x first %02x curr %02x next %02x stop %02x\n",
+			    sc->sc_dev.dv_xname, itohs(packet_hdr.count), len,
+			    sc->rec_page_start, sc->next_packet, current,
+			    packet_hdr.next_packet, sc->rec_page_stop);
+		}
+#endif
+
+		/*
+		 * Be fairly liberal about what we allow as a "reasonable"
+		 * length so that a [crufty] packet will make it to BPF (and
+		 * can thus be analyzed).  Note that all that is really
+		 * important is that we have a length that will fit into one
+		 * mbuf cluster or less; the upper layer protocols can then
+		 * figure out the length from their own length field(s).
+		 */
+		if (len <= (MCLBYTES > ETHER_MAX_LEN ?
+			    MCLBYTES : ETHER_MAX_LEN) &&
+		    packet_hdr.next_packet >= sc->rec_page_start &&
+		    packet_hdr.next_packet < sc->rec_page_stop) {
+			/* Go get packet. */
+			isaedread(sc, packet_ptr + sizeof(struct ed_ring),
+			    len - sizeof(struct ed_ring));
+		} else {
+			/* Really BAD.  The ring pointers are corrupted. */
+			log(LOG_ERR,
+			    "%s: NIC memory corrupt - invalid packet length %d or pkt link %d [%d-%d)\n",
+			    sc->sc_dev.dv_xname, len, packet_hdr.next_packet,
+			    sc->rec_page_start, sc->rec_page_stop);
+			++sc->sc_arpcom.ac_if.if_ierrors;
+			isaedreset(sc);
+			return;
+		}
+
+
+		sc->next_packet = packet_hdr.next_packet;
+#ifdef DDB
+		if (sc->next_packet < sc->rec_page_start || sc->next_packet >= sc->rec_page_stop)
+			Debugger();
+#endif
+
+		/*
+		 * Update NIC boundary pointer - being careful to keep it one
+		 * buffer behind (as recommended by NS databook).
+		 */
+		boundary = sc->next_packet - 1;
+		if (boundary < sc->rec_page_start)
+			boundary = sc->rec_page_stop - 1;
+		NIC_PUT(sc, ED_P0_BNRY, boundary);
+	} while (sc->next_packet != current);
+
+	goto loop;
+}
+
+/* Ethernet interface interrupt processor. */
+int
+isaedintr(arg)
+	void *arg;
+{
+	struct isaed_softc *sc = arg;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	u_char isr;
+
+	/* Set NIC to page 0 registers. */
+	NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+
+	isr = NIC_GET(sc, ED_P0_ISR);
+	if (!isr)
+		return (0);
+	/* Loop until there are no more new interrupts. */
+	for (;;) {
+#ifdef DDB
+		if (sc->next_packet < sc->rec_page_start || sc->next_packet >= sc->rec_page_stop)
+			Debugger();
+#endif
+		/*
+		 * Reset all the bits that we are 'acknowledging' by writing a
+		 * '1' to each bit position that was set.
+		 * (Writing a '1' *clears* the bit.)
+		 */
+		NIC_PUT(sc, ED_P0_ISR, isr);
+
+		/*
+		 * Handle transmitter interrupts.  Handle these first because
+		 * the receiver will reset the board under some conditions.
+		 */
+		if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
+			u_char collisions = NIC_GET(sc, ED_P0_NCR) & 0x0f;
+
+			/*
+			 * Check for transmit error.  If a TX completed with an
+			 * error, we end up throwing the packet away.  Really
+			 * the only error that is possible is excessive
+			 * collisions, and in this case it is best to allow the
+			 * automatic mechanisms of TCP to backoff the flow.  Of
+			 * course, with UDP we're screwed, but this is expected
+			 * when a network is heavily loaded.
+			 */
+			(void) NIC_GET(sc, ED_P0_TSR);
+			if (isr & ED_ISR_TXE) {
+				/*
+				 * Excessive collisions (16).
+				 */
+				if ((NIC_GET(sc, ED_P0_TSR) & ED_TSR_ABT)
+				    && (collisions == 0)) {
+					/*
+					 * When collisions total 16, the P0_NCR
+					 * will indicate 0, and the TSR_ABT is
+					 * set.
+					 */
+					collisions = 16;
+				}
+
+				/* Update output errors counter. */
+				++ifp->if_oerrors;
+			} else {
+				/*
+				 * Update total number of successfully
+				 * transmitted packets.
+				 */
+				++ifp->if_opackets;
+			}
+
+			/* Done with the buffer. */
+			sc->txb_inuse--;
+
+			/* Clear watchdog timer. */
+			ifp->if_timer = 0;
+			ifp->if_flags &= ~IFF_OACTIVE;
+
+			/*
+			 * Add in total number of collisions on last
+			 * transmission.
+			 */
+			ifp->if_collisions += collisions;
+
+			/*
+			 * Decrement buffer in-use count if not zero (can only
+			 * be zero if a transmitter interrupt occured while not
+			 * actually transmitting).
+			 * If data is ready to transmit, start it transmitting,
+			 * otherwise defer until after handling receiver.
+			 */
+			if (sc->txb_inuse > 0)
+				isaed_xmit(sc);
+		}
+
+		/* Handle receiver interrupts. */
+		if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
+			/*
+			 * Overwrite warning.  In order to make sure that a
+			 * lockup of the local DMA hasn't occurred, we reset
+			 * and re-init the NIC.  The NSC manual suggests only a
+			 * partial reset/re-init is necessary - but some chips
+			 * seem to want more.  The DMA lockup has been seen
+			 * only with early rev chips - Methinks this bug was
+			 * fixed in later revs.  -DG
+			 */
+			if (isr & ED_ISR_OVW) {
+				++ifp->if_ierrors;
+#ifdef DIAGNOSTIC
+				log(LOG_WARNING,
+				    "%s: warning - receiver ring buffer overrun\n",
+				    sc->sc_dev.dv_xname);
+#endif
+				/* Stop/reset/re-init NIC. */
+				isaedreset(sc);
+			} else {
+				/*
+				 * Receiver Error.  One or more of: CRC error,
+				 * frame alignment error FIFO overrun, or
+				 * missed packet.
+				 */
+				if (isr & ED_ISR_RXE) {
+					++ifp->if_ierrors;
+#ifdef ISAED_DEBUG
+					if (isaeddebug)
+						printf("%s: receive error %x\n",
+						    sc->sc_dev.dv_xname,
+						    NIC_GET(sc, ED_P0_RSR));
+#endif
+				}
+
+				/*
+				 * Go get the packet(s).
+				 * XXX - Doing this on an error is dubious
+				 * because there shouldn't be any data to get
+				 * (we've configured the interface to not
+				 * accept packets with errors).
+				 */
+
+				/*
+				 * Enable 16bit access to shared memory first
+				 * on WD/SMC boards.
+				 */
+				if (sc->vendor == ED_VENDOR_WD_SMC) {
+					if (sc->isa16bit)
+						outb(sc->asic_addr + ED_WD_LAAR,
+						    sc->wd_laar_proto | ED_WD_LAAR_M16EN);
+					outb(sc->asic_addr + ED_WD_MSR,
+					    sc->wd_msr_proto | ED_WD_MSR_MENB);
+					(void) inb(0x84);
+					(void) inb(0x84);
+				}
+
+				isaed_rint(sc);
+
+				/* Disable 16-bit access. */
+				if (sc->vendor == ED_VENDOR_WD_SMC) {
+					outb(sc->asic_addr + ED_WD_MSR,
+					    sc->wd_msr_proto);
+					if (sc->isa16bit)
+						outb(sc->asic_addr + ED_WD_LAAR,
+						    sc->wd_laar_proto);
+					(void) inb(0x84);
+					(void) inb(0x84);
+				}
+			}
+		}
+
+		/*
+		 * If it looks like the transmitter can take more data,	attempt
+		 * to start output on the interface.  This is done after
+		 * handling the receiver to give the receiver priority.
+		 */
+		isaedstart(ifp);
+
+		/*
+		 * Return NIC CR to standard state: page 0, remote DMA
+		 * complete, start (toggling the TXP bit off, even if was just
+		 * set in the transmit routine, is *okay* - it is 'edge'
+		 * triggered from low to high).
+		 */
+		NIC_PUT(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
+
+		/*
+		 * If the Network Talley Counters overflow, read them to reset
+		 * them.  It appears that old 8390's won't clear the ISR flag
+		 * otherwise - resulting in an infinite loop.
+		 */
+		if (isr & ED_ISR_CNT) {
+			(void) NIC_GET(sc, ED_P0_CNTR0);
+			(void) NIC_GET(sc, ED_P0_CNTR1);
+			(void) NIC_GET(sc, ED_P0_CNTR2);
+		}
+
+		isr = NIC_GET(sc, ED_P0_ISR);
+		if (!isr)
+			return (1);
+	}
+}
+
+/*
+ * Process an ioctl request.  This code needs some work - it looks pretty ugly.
+ */
+int
+isaedioctl(ifp, cmd, data)
+	register struct ifnet *ifp;
+	u_long cmd;
+	caddr_t data;
+{
+	struct isaed_softc *sc = isaedcd.cd_devs[ifp->if_unit];
+	register struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ifreq *ifr = (struct ifreq *)data;
+	int s, error = 0;
+
+	s = splimp();
+
+	switch (cmd) {
+
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			isaedinit(sc);
+			arp_ifinit(&sc->sc_arpcom, ifa);
+			break;
+#endif
+#ifdef NS
+		/* XXX - This code is probably wrong. */
+		case AF_NS:
+		    {
+			register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
+
+			if (ns_nullhost(*ina))
+				ina->x_host =
+				    *(union ns_host *)(sc->sc_arpcom.ac_enaddr);
+			else
+				copy(ina->x_host.c_host,
+				    sc->sc_arpcom.ac_enaddr,
+				    sizeof(sc->sc_arpcom.ac_enaddr));
+			/* Set new address. */
+			isaedinit(sc);
+			break;
+		    }
+#endif
+		default:
+			isaedinit(sc);
+			break;
+		}
+		break;
+
+	case SIOCSIFFLAGS:
+		if ((ifp->if_flags & IFF_UP) == 0 &&
+		    (ifp->if_flags & IFF_RUNNING) != 0) {
+			/*
+			 * If interface is marked down and it is running, then
+			 * stop it.
+			 */
+			isaedstop(sc);
+			ifp->if_flags &= ~IFF_RUNNING;
+		} else if ((ifp->if_flags & IFF_UP) != 0 &&
+		    	   (ifp->if_flags & IFF_RUNNING) == 0) {
+			/*
+			 * If interface is marked up and it is stopped, then
+			 * start it.
+			 */
+			isaedinit(sc);
+		} else {
+			/*
+			 * Reset the interface to pick up changes in any other
+			 * flags that affect hardware registers.
+			 */
+			isaedstop(sc);
+			isaedinit(sc);
+		}
+		break;
+
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		/* Update our multicast list. */
+		error = (cmd == SIOCADDMULTI) ?
+		    ether_addmulti(ifr, &sc->sc_arpcom) :
+		    ether_delmulti(ifr, &sc->sc_arpcom);
+
+		if (error == ENETRESET) {
+			/*
+			 * Multicast list has changed; set the hardware filter
+			 * accordingly.
+			 */
+			isaedstop(sc); /* XXX for ds_setmcaf? */
+			isaedinit(sc);
+			error = 0;
+		}
+		break;
+
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	splx(s);
+	return (error);
+}
+
+/*
+ * Retreive packet from shared memory and send to the next level up via
+ * ether_input().  If there is a BPF listener, give a copy to BPF, too.
+ */
+void
+isaedread(sc, buf, len)
+	struct isaed_softc *sc;
+	caddr_t buf;
+	int len;
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+    	struct mbuf *m;
+	struct ether_header *eh;
+
+	/* Pull packet off interface. */
+	m = isaedget(sc, buf, len);
+	if (m == 0) {
+		ifp->if_ierrors++;
+		return;
+	}
+
+	ifp->if_ipackets++;
+
+	/* We assume that the header fit entirely in one mbuf. */
+	eh = mtod(m, struct ether_header *);
+
+#if NBPFILTER > 0
+	/*
+	 * Check if there's a BPF listener on this interface.
+	 * If so, hand off the raw packet to BPF.
+	 */
+	if (ifp->if_bpf) {
+		bpf_mtap(ifp->if_bpf, m);
+
+		/*
+		 * Note that the interface cannot be in promiscuous mode if
+		 * there are no BPF listeners.  And if we are in promiscuous
+		 * mode, we have to check if this packet is really ours.
+		 */
+		if ((ifp->if_flags & IFF_PROMISC) &&
+		    (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */
+		    bcmp(eh->ether_dhost, sc->sc_arpcom.ac_enaddr,
+			    sizeof(eh->ether_dhost)) != 0) {
+			m_freem(m);
+			return;
+		}
+	}
+#endif
+
+	/* We assume that the header fit entirely in one mbuf. */
+	m_adj(m, sizeof(struct ether_header));
+	ether_input(ifp, eh, m);
+}
+
+/*
+ * Supporting routines.
+ */
+
+/*
+ * Given a NIC memory source address and a host memory destination address,
+ * copy 'amount' from NIC to host using Programmed I/O.  The 'amount' is
+ * rounded up to a word - okay as long as mbufs are word sized.
+ * This routine is currently Novell-specific.
+ */
+void
+isaed_pio_readmem(sc, src, dst, amount)
+	struct isaed_softc *sc;
+	u_short src;
+	caddr_t dst;
+	u_short amount;
+{
+	/* Select page 0 registers. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
+
+	/* Round up to a word. */
+	if (amount & 1)
+		++amount;
+
+	/* Set up DMA byte count. */
+	NIC_PUT(sc, ED_P0_RBCR0, amount);
+	NIC_PUT(sc, ED_P0_RBCR1, amount >> 8);
+
+	/* Set up source address in NIC mem. */
+	NIC_PUT(sc, ED_P0_RSAR0, src);
+	NIC_PUT(sc, ED_P0_RSAR1, src >> 8);
+
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
+
+	if (sc->isa16bit)
+		insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
+	else
+		insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
+}
+
+/*
+ * Stripped down routine for writing a linear buffer to NIC memory.  Only used
+ * in the probe routine to test the memory.  'len' must be even.
+ */
+void
+isaed_pio_writemem(sc, src, dst, len)
+	struct isaed_softc *sc;
+	caddr_t src;
+	u_short dst;
+	u_short len;
+{
+	int maxwait = 100; /* about 120us */
+
+	/* Select page 0 registers. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
+
+	/* Reset remote DMA complete flag. */
+	NIC_PUT(sc, ED_P0_ISR, ED_ISR_RDC);
+
+	/* Set up DMA byte count. */
+	NIC_PUT(sc, ED_P0_RBCR0, len);
+	NIC_PUT(sc, ED_P0_RBCR1, len >> 8);
+
+	/* Set up destination address in NIC mem. */
+	NIC_PUT(sc, ED_P0_RSAR0, dst);
+	NIC_PUT(sc, ED_P0_RSAR1, dst >> 8);
+
+	/* Set remote DMA write. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
+
+	if (sc->isa16bit)
+		outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
+	else
+		outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
+
+	/*
+	 * Wait for remote DMA complete.  This is necessary because on the
+	 * transmit side, data is handled internally by the NIC in bursts and
+	 * we can't start another remote DMA until this one completes.  Not
+	 * waiting causes really bad things to happen - like the NIC
+	 * irrecoverably jamming the ISA bus.
+	 */
+	while (((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
+}
+
+/*
+ * Write an mbuf chain to the destination NIC memory address using programmed
+ * I/O.
+ */
+u_short
+isaed_pio_write_mbufs(sc, m, dst)
+	struct isaed_softc *sc;
+	struct mbuf *m;
+	u_short dst;
+{
+	u_short len;
+	struct mbuf *mp;
+	int maxwait = 100; /* about 120us */
+
+	len = m->m_pkthdr.len;
+
+	/* Select page 0 registers. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
+
+	/* Reset remote DMA complete flag. */
+	NIC_PUT(sc, ED_P0_ISR, ED_ISR_RDC);
+
+	/* Set up DMA byte count. */
+	NIC_PUT(sc, ED_P0_RBCR0, len);
+	NIC_PUT(sc, ED_P0_RBCR1, len >> 8);
+
+	/* Set up destination address in NIC mem. */
+	NIC_PUT(sc, ED_P0_RSAR0, dst);
+	NIC_PUT(sc, ED_P0_RSAR1, dst >> 8);
+
+	/* Set remote DMA write. */
+	NIC_PUT(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
+
+	/*
+	 * Transfer the mbuf chain to the NIC memory.
+	 * 16-bit cards require that data be transferred as words, and only
+	 * words, so that case requires some extra code to patch over
+	 * odd-length mbufs.
+	 */
+	if (!sc->isa16bit) {
+		/* NE1000s are easy. */
+		for (; m != 0; m = m->m_next) {
+			if (m->m_len) {
+				outsb(sc->asic_addr + ED_NOVELL_DATA,
+				    mtod(m, u_char *), m->m_len);
+			}
+		}
+	} else {
+		/* NE2000s are a bit trickier. */
+		u_char *data, savebyte[2];
+		int len, wantbyte;
+
+		wantbyte = 0;
+		for (; m != 0; m = m->m_next) {
+			len = m->m_len;
+			if (len == 0)
+				continue;
+			data = mtod(m, u_char *);
+			/* Finish the last word. */
+			if (wantbyte) {
+				savebyte[1] = *data;
+				outw(sc->asic_addr + ED_NOVELL_DATA,
+				    *(u_short *)savebyte);
+				data++;
+				len--;
+				wantbyte = 0;
+			}
+			/* Output contiguous words. */
+			if (len > 1)
+				outsw(sc->asic_addr + ED_NOVELL_DATA,
+				    data, len >> 1);
+			/* Save last byte, if necessary. */
+			if (len & 1) {
+				data += len & ~1;
+				savebyte[0] = *data;
+				wantbyte = 1;
+			}
+		}
+
+		if (wantbyte) {
+			savebyte[1] = 0;
+			outw(sc->asic_addr + ED_NOVELL_DATA,
+			    *(u_short *)savebyte);
+		}
+	}
+
+	/*
+	 * Wait for remote DMA complete.  This is necessary because on the
+	 * transmit side, data is handled internally by the NIC in bursts and
+	 * we can't start another remote DMA until this one completes. 	Not
+	 * waiting causes really bad things to happen - like the NIC
+	 * irrecoverably jamming the ISA bus.
+	 */
+	while (((NIC_GET(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
+
+	if (!maxwait) {
+		log(LOG_WARNING,
+		    "%s: remote transmit DMA failed to complete\n",
+		    sc->sc_dev.dv_xname);
+		isaedreset(sc);
+	}
+
+	return (len);
+}
+
+/*
+ * Given a source and destination address, copy 'amount' of a packet from the
+ * ring buffer into a linear destination buffer.  Takes into account ring-wrap.
+ */
+static inline caddr_t
+isaed_ring_copy(sc, src, dst, amount)
+	struct isaed_softc *sc;
+	caddr_t src, dst;
+	u_short	amount;
+{
+	u_short	tmp_amount;
+
+	/* Does copy wrap to lower addr in ring buffer? */
+	if (src + amount > sc->mem_end) {
+		tmp_amount = sc->mem_end - src;
+
+		/* Copy amount up to end of NIC memory. */
+		if (sc->mem_shared)
+			copy_from_isa(src, dst, tmp_amount);
+		else
+			isaed_pio_readmem(sc, (long)src, dst, tmp_amount);
+
+		amount -= tmp_amount;
+		src = sc->mem_ring;
+		dst += tmp_amount;
+	}
+
+	if (sc->mem_shared)
+		copy_from_isa(src, dst, amount);
+	else
+		isaed_pio_readmem(sc, (long)src, dst, amount);
+
+	return (src + amount);
+}
+
+/*
+ * Copy data from receive buffer to end of mbuf chain allocate additional mbufs
+ * as needed.  Return pointer to last mbuf in chain.
+ * sc = isaed info (softc)
+ * src = pointer in isaed ring buffer
+ * dst = pointer to last mbuf in mbuf chain to copy to
+ * amount = amount of data to copy
+ */
+struct mbuf *
+isaedget(sc, src, total_len)
+	struct isaed_softc *sc;
+	caddr_t src;
+	u_short total_len;
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct mbuf *top, **mp, *m;
+	int len;
+
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m == 0)
+		return 0;
+	m->m_pkthdr.rcvif = ifp;
+	m->m_pkthdr.len = total_len;
+	len = MHLEN;
+	top = 0;
+	mp = &top;
+
+	while (total_len > 0) {
+		if (top) {
+			MGET(m, M_DONTWAIT, MT_DATA);
+			if (m == 0) {
+				m_freem(top);
+				return 0;
+			}
+			len = MLEN;
+		}
+		if (total_len >= MINCLSIZE) {
+			MCLGET(m, M_DONTWAIT);
+			if (m->m_flags & M_EXT)
+				len = MCLBYTES;
+		}
+		m->m_len = len = min(total_len, len);
+		src = isaed_ring_copy(sc, src, mtod(m, caddr_t), len);
+		total_len -= len;
+		*mp = m;
+		mp = &m->m_next;
+	}
+
+	return top;
+}
+
+/*
+ * Compute the multicast address filter from the list of multicast addresses we
+ * need to listen to.
+ */
+void
+isaed_getmcaf(ac, af)
+	struct arpcom *ac;
+	u_long *af;
+{
+	struct ifnet *ifp = &ac->ac_if;
+	struct ether_multi *enm;
+	register u_char *cp, c;
+	register u_long crc;
+	register int i, len;
+	struct ether_multistep step;
+
+	/*
+	 * Set up multicast address filter by passing all multicast addresses
+	 * through a crc generator, and then using the high order 6 bits as an
+	 * index into the 64 bit logical address filter.  The high order bit
+	 * selects the word, while the rest of the bits select the bit within
+	 * the word.
+	 */
+
+	if (ifp->if_flags & IFF_PROMISC) {
+		ifp->if_flags |= IFF_ALLMULTI;
+		af[0] = af[1] = 0xffffffff;
+		return;
+	}
+
+	af[0] = af[1] = 0;
+	ETHER_FIRST_MULTI(step, ac, enm);
+	while (enm != NULL) {
+		if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
+		    sizeof(enm->enm_addrlo)) != 0) {
+			/*
+			 * We must listen to a range of multicast addresses.
+			 * For now, just accept all multicasts, rather than
+			 * trying to set only those filter bits needed to match
+			 * the range.  (At this time, the only use of address
+			 * ranges is for IP multicast routing, for which the
+			 * range is big enough to require all bits set.)
+			 */
+			ifp->if_flags |= IFF_ALLMULTI;
+			af[0] = af[1] = 0xffffffff;
+			return;
+		}
+
+		cp = enm->enm_addrlo;
+		crc = 0xffffffff;
+		for (len = sizeof(enm->enm_addrlo); --len >= 0;) {
+			c = *cp++;
+			for (i = 8; --i >= 0;) {
+				if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) {
+					crc <<= 1;
+					crc ^= 0x04c11db6 | 1;
+				} else
+					crc <<= 1;
+				c >>= 1;
+			}
+		}
+		/* Just want the 6 most significant bits. */
+		crc >>= 26;
+
+		/* Turn on the corresponding bit in the filter. */
+		af[crc >> 5] |= 1 << ((crc & 0x1f) ^ 0);
+
+		ETHER_NEXT_MULTI(step, enm);
+	}
+	ifp->if_flags &= ~IFF_ALLMULTI;
+}
diff --git a/sys/arch/amiga/isa/if_isaedreg.h b/sys/arch/amiga/isa/if_isaedreg.h
new file mode 100644
index 00000000000..53d4005b7da
--- /dev/null
+++ b/sys/arch/amiga/isa/if_isaedreg.h
@@ -0,0 +1,398 @@
+/*	$NetBSD: if_isaedreg.h,v 1.12 1994/10/27 04:17:23 cgd Exp $	*/
+
+/*
+ * National Semiconductor DS8390 NIC register definitions.
+ *
+ * Copyright (C) 1993, David Greenman.  This software may be used, modified,
+ * copied, distributed, and sold, in both source and binary form provided that
+ * the above copyright and these terms are retained.  Under no circumstances is
+ * the author responsible for the proper functioning of this software, nor does
+ * the author assume any responsibility for damages incurred with its use.
+ */
+
+/*
+ * Vendor types
+ */
+#define ED_VENDOR_WD_SMC	0x00	/* Western Digital/SMC */
+#define ED_VENDOR_3COM		0x01	/* 3Com */
+#define ED_VENDOR_NOVELL	0x02	/* Novell */
+
+/*
+ * Compile-time config flags
+ */
+/*
+ * This sets the default for enabling/disablng the tranceiver.
+ */
+#define ED_FLAGS_DISABLE_TRANCEIVER	0x0001
+
+/*
+ * This forces the board to be used in 8/16-bit mode even if it autoconfigs
+ * differently.
+ */
+#define ED_FLAGS_FORCE_8BIT_MODE	0x0002
+#define ED_FLAGS_FORCE_16BIT_MODE	0x0004
+
+/*
+ * This disables the use of double transmit buffers.
+ */
+#define ED_FLAGS_NO_MULTI_BUFFERING	0x0008
+
+/*
+ * This forces all operations with the NIC memory to use Programmed I/O (i.e.
+ * not via shared memory).
+ */
+#define ED_FLAGS_FORCE_PIO		0x0010
+
+/*
+ *		Definitions for Western digital/SMC WD80x3 series ASIC
+ */
+/*
+ * Memory Select Register (MSR)
+ */
+#define ED_WD_MSR	0
+
+/* next three definitions for Toshiba */
+#define	ED_WD_MSR_POW	0x02	/* 0 = power save, 1 = normal (R/W) */
+#define	ED_WD_MSR_BSY	0x04	/* gate array busy (R) */
+#define	ED_WD_MSR_LEN	0x20	/* 0 = 16-bit, 1 = 8-bit (R/W) */
+
+#define ED_WD_MSR_ADDR	0x3f	/* Memory decode bits 18-13 */
+#define ED_WD_MSR_MENB	0x40	/* Memory enable */
+#define ED_WD_MSR_RST	0x80	/* Reset board */
+
+/*
+ * Interface Configuration Register (ICR)
+ */
+#define ED_WD_ICR	1
+
+#define ED_WD_ICR_16BIT	0x01	/* 16-bit interface */
+#define ED_WD_ICR_OAR	0x02	/* select register (0=BIO 1=EAR) */
+#define ED_WD_ICR_IR2	0x04	/* high order bit of encoded IRQ */
+#define ED_WD_ICR_MSZ	0x08	/* memory size (0=8k 1=32k) */
+#define ED_WD_ICR_RLA	0x10	/* recall LAN address */
+#define ED_WD_ICR_RX7	0x20	/* recall all but i/o and LAN address */
+#define	ED_WD_ICR_RIO	0x40	/* recall i/o address */
+#define ED_WD_ICR_STO	0x80	/* store to non-volatile memory */
+#ifdef TOSH_ETHER
+#define	ED_WD_ICR_MEM	0xe0	/* shared mem address A15-A13 (R/W) */
+#define	ED_WD_ICR_MSZ1	0x0f	/* memory size, 0x08 = 64K, 0x04 = 32K,
+				   0x02 = 16K, 0x01 = 8K */
+				/* 64K can only be used if mem address
+				   above 1MB */
+				/* IAR holds address A23-A16 (R/W) */
+#endif
+
+/*
+ * IO Address Register (IAR)
+ */
+#define ED_WD_IAR	2
+
+/*
+ * EEROM Address Register
+ */
+#define ED_WD_EAR	3
+
+/*
+ * Interrupt Request Register (IRR)
+ */
+#define ED_WD_IRR	4
+
+#define	ED_WD_IRR_0WS	0x01	/* use 0 wait-states on 8 bit bus */
+#define ED_WD_IRR_OUT1	0x02	/* WD83C584 pin 1 output */
+#define ED_WD_IRR_OUT2	0x04	/* WD83C584 pin 2 output */
+#define ED_WD_IRR_OUT3	0x08	/* WD83C584 pin 3 output */
+#define ED_WD_IRR_FLASH	0x10	/* Flash RAM is in the ROM socket */
+
+/*
+ * The three bits of the encoded IRQ are decoded as follows:
+ *
+ * IR2 IR1 IR0  IRQ
+ *  0   0   0   2/9
+ *  0   0   1   3
+ *  0   1   0   5
+ *  0   1   1   7
+ *  1   0   0   10
+ *  1   0   1   11
+ *  1   1   0   15
+ *  1   1   1   4
+ */
+#define ED_WD_IRR_IR0	0x20	/* bit 0 of encoded IRQ */
+#define ED_WD_IRR_IR1	0x40	/* bit 1 of encoded IRQ */
+#define ED_WD_IRR_IEN	0x80	/* Interrupt enable */
+
+/*
+ * LA Address Register (LAAR)
+ */
+#define ED_WD_LAAR	5
+
+#define ED_WD_LAAR_ADDRHI	0x1f	/* bits 23-19 of RAM address */
+#define ED_WD_LAAR_0WS16	0x20	/* enable 0 wait-states on 16 bit bus */
+#define ED_WD_LAAR_L16EN	0x40	/* enable 16-bit operation */
+#define ED_WD_LAAR_M16EN	0x80	/* enable 16-bit memory access */
+
+/* i/o base offset to station address/card-ID PROM */
+#define ED_WD_PROM	8
+
+/*
+ *	83C790 specific registers
+ */
+/*
+ * Hardware Support Register (HWR) ('790)
+ */
+#define	ED_WD790_HWR	4
+
+#define	ED_WD790_HWR_RST	0x10	/* hardware reset */
+#define	ED_WD790_HWR_LPRM	0x40	/* LAN PROM select */
+#define	ED_WD790_HWR_SWH	0x80	/* switch register set */
+
+/*
+ * ICR790 Interrupt Control Register for the 83C790
+ */
+#define	ED_WD790_ICR	6
+
+#define	ED_WD790_ICR_EIL	0x01	/* enable interrupts */
+
+/*
+ * General Control Register (GCR)
+ * Eanbled with SWH bit == 1 in HWR register
+ */
+#define	ED_WD790_GCR	0x0d
+
+#define	ED_WD790_GCR_IR0	0x04	/* bit 0 of encoded IRQ */
+#define	ED_WD790_GCR_IR1	0x08	/* bit 1 of encoded IRQ */
+#define	ED_WD790_GCR_ZWSEN	0x20	/* zero wait state enable */
+#define	ED_WD790_GCR_IR2	0x40	/* bit 2 of encoded IRQ */
+/*
+ * The three bits of the encoded IRQ are decoded as follows:
+ *
+ * IR2 IR1 IR0  IRQ
+ *  0   0   0   none
+ *  0   0   1   9
+ *  0   1   0   3
+ *  0   1   1   5
+ *  1   0   0   7
+ *  1   0   1   10
+ *  1   1   0   11
+ *  1   1   1   15
+ */
+
+/* i/o base offset to CARD ID */
+#define ED_WD_CARD_ID	ED_WD_PROM+6
+
+/* Board type codes in card ID */
+#define ED_TYPE_WD8003S		0x02
+#define ED_TYPE_WD8003E		0x03
+#define ED_TYPE_WD8013EBT	0x05
+#define	ED_TYPE_TOSHIBA1	0x11	/* named PCETA1 */
+#define	ED_TYPE_TOSHIBA2	0x12	/* named PCETA2 */
+#define	ED_TYPE_TOSHIBA3	0x13	/* named PCETB */
+#define	ED_TYPE_TOSHIBA4	0x14	/* named PCETC */
+#define	ED_TYPE_WD8003W		0x24
+#define	ED_TYPE_WD8003EB	0x25
+#define	ED_TYPE_WD8013W		0x26
+#define ED_TYPE_WD8013EP	0x27
+#define ED_TYPE_WD8013WC	0x28
+#define ED_TYPE_WD8013EPC	0x29
+#define	ED_TYPE_SMC8216T	0x2a
+#define	ED_TYPE_SMC8216C	0x2b
+#define ED_TYPE_WD8013EBP	0x2c
+
+/* Bit definitions in card ID */
+#define	ED_WD_REV_MASK		0x1f	/* Revision mask */
+#define	ED_WD_SOFTCONFIG	0x20	/* Soft config */
+#define	ED_WD_LARGERAM		0x40	/* Large RAM */
+#define	ED_MICROCHANEL		0x80	/* Microchannel bus (vs. isa) */
+
+/*
+ * Checksum total.  All 8 bytes in station address PROM will add up to this.
+ */
+#ifdef TOSH_ETHER
+#define ED_WD_ROM_CHECKSUM_TOTAL	0xA5
+#else
+#define ED_WD_ROM_CHECKSUM_TOTAL	0xFF
+#endif
+
+#define ED_WD_NIC_OFFSET	0x10	/* I/O base offset to NIC */
+#define ED_WD_ASIC_OFFSET	0	/* I/O base offset to ASIC */
+#define ED_WD_IO_PORTS		32	/* # of i/o addresses used */
+
+#define ED_WD_PAGE_OFFSET	0	/* page offset for NIC access to mem */
+
+/*
+ *			Definitions for 3Com 3c503
+ */
+#define ED_3COM_NIC_OFFSET	0
+#define ED_3COM_ASIC_OFFSET	0x400	/* offset to nic i/o regs */
+
+/*
+ * XXX - The I/O address range is fragmented in the 3c503; this is the
+ *	number of regs at iobase.
+ */
+#define ED_3COM_IO_PORTS	16	/* # of i/o addresses used */
+
+/* tx memory starts in second bank on 8bit cards */
+#define ED_3COM_TX_PAGE_OFFSET_8BIT	0x20
+
+/* tx memory starts in first bank on 16bit cards */
+#define ED_3COM_TX_PAGE_OFFSET_16BIT	0x0
+
+/* ...and rx memory starts in second bank */
+#define ED_3COM_RX_PAGE_OFFSET_16BIT	0x20
+
+
+/*
+ * Page Start Register.  Must match PSTART in NIC.
+ */
+#define ED_3COM_PSTR		0
+
+/*
+ * Page Stop Register.  Must match PSTOP in NIC.
+ */
+#define ED_3COM_PSPR		1
+
+/*
+ * DrQ Timer Register.  Determines number of bytes to be transfered during a
+ * DMA burst.
+ */
+#define ED_3COM_DQTR		2
+
+/*
+ * Base Configuration Register.  Read-only register which contains the
+ * board-configured I/O base address of the adapter.  Bit encoded.
+ */
+#define ED_3COM_BCFR		3
+
+/*
+ * EPROM Configuration Register.  Read-only register which contains the
+ * board-configured memory base address.  Bit encoded.
+ */
+#define ED_3COM_PCFR		4
+
+/*
+ * GA Configuration Register.  Gate-Array Configuration Register.
+ *
+ * mbs2  mbs1  mbs0	start address
+ *  0     0     0	0x0000
+ *  0     0     1	0x2000
+ *  0     1     0	0x4000
+ *  0     1     1	0x6000
+ *
+ * Note that with adapters with only 8K, the setting for 0x2000 must always be
+ * used.
+ */
+#define ED_3COM_GACFR		5
+
+#define ED_3COM_GACFR_MBS0	0x01
+#define ED_3COM_GACFR_MBS1	0x02
+#define ED_3COM_GACFR_MBS2	0x04
+
+#define ED_3COM_GACFR_RSEL	0x08	/* enable shared memory */
+#define ED_3COM_GACFR_TEST	0x10	/* for GA testing */
+#define ED_3COM_GACFR_OWS	0x20	/* select 0WS access to GA */
+#define ED_3COM_GACFR_TCM	0x40	/* Mask DMA interrupts */
+#define ED_3COM_GACFR_NIM	0x80	/* Mask NIC interrupts */
+
+/*
+ * Control Register.  Miscellaneous control functions.
+ */
+#define ED_3COM_CR		6
+
+#define ED_3COM_CR_RST		0x01	/* Reset GA and NIC */
+#define ED_3COM_CR_XSEL		0x02	/* Transceiver select.  BNC=1(def) AUI=0 */
+#define ED_3COM_CR_EALO		0x04	/* window EA PROM 0-15 to I/O base */
+#define ED_3COM_CR_EAHI		0x08	/* window EA PROM 16-31 to I/O base */
+#define ED_3COM_CR_SHARE	0x10	/* select interrupt sharing option */
+#define ED_3COM_CR_DBSEL	0x20	/* Double buffer select */
+#define ED_3COM_CR_DDIR		0x40	/* DMA direction select */
+#define ED_3COM_CR_START	0x80	/* Start DMA controller */
+
+/*
+ * Status Register.  Miscellaneous status information.
+ */
+#define ED_3COM_STREG		7
+
+#define ED_3COM_STREG_REV	0x07	/* GA revision */
+#define ED_3COM_STREG_DIP	0x08	/* DMA in progress */
+#define ED_3COM_STREG_DTC	0x10	/* DMA terminal count */
+#define ED_3COM_STREG_OFLW	0x20	/* Overflow */
+#define ED_3COM_STREG_UFLW	0x40	/* Underflow */
+#define ED_3COM_STREG_DPRDY	0x80	/* Data port ready */
+
+/*
+ * Interrupt/DMA Configuration Register
+ */
+#define ED_3COM_IDCFR		8
+
+#define ED_3COM_IDCFR_DRQ	0x07	/* DMA request */
+#define ED_3COM_IDCFR_UNUSED	0x08	/* not used */
+#if 0
+#define ED_3COM_IDCFR_IRQ	0xF0	/* Interrupt request */
+#else
+#define ED_3COM_IDCFR_IRQ2	0x10	/* Interrupt request 2 select */
+#define ED_3COM_IDCFR_IRQ3	0x20	/* Interrupt request 3 select */
+#define ED_3COM_IDCFR_IRQ4	0x40	/* Interrupt request 4 select */
+#define ED_3COM_IDCFR_IRQ5	0x80	/* Interrupt request 5 select */
+#endif
+
+/*
+ * DMA Address Register MSB
+ */
+#define ED_3COM_DAMSB		9
+
+/*
+ * DMA Address Register LSB
+ */
+#define ED_3COM_DALSB		0x0a
+
+/*
+ * Vector Pointer Register 2
+ */
+#define ED_3COM_VPTR2		0x0b
+
+/*
+ * Vector Pointer Register 1
+ */
+#define ED_3COM_VPTR1		0x0c
+
+/*
+ * Vector Pointer Register 0
+ */
+#define ED_3COM_VPTR0		0x0d
+
+/*
+ * Register File Access MSB
+ */
+#define ED_3COM_RFMSB		0x0e
+
+/*
+ * Register File Access LSB
+ */
+#define ED_3COM_RFLSB		0x0f
+
+/*
+ *		 Definitions for Novell NE1000/2000 boards
+ */
+
+/*
+ * Board type codes
+ */
+#define ED_TYPE_NE1000		0x01
+#define ED_TYPE_NE2000		0x02
+
+/*
+ * Register offsets/total
+ */
+#define ED_NOVELL_NIC_OFFSET	0x00
+#define ED_NOVELL_ASIC_OFFSET	0x10
+#define ED_NOVELL_IO_PORTS	32
+
+/*
+ * Remote DMA data register; for reading or writing to the NIC mem via
+ * programmed I/O (offset from ASIC base).
+ */
+#define ED_NOVELL_DATA		0x00
+
+/*
+ * Reset register; reading from this register causes a board reset.
+ */
+#define ED_NOVELL_RESET		0x0f
diff --git a/sys/arch/amiga/isa/isa_intr.h b/sys/arch/amiga/isa/isa_intr.h
new file mode 100644
index 00000000000..265506ab9cd
--- /dev/null
+++ b/sys/arch/amiga/isa/isa_intr.h
@@ -0,0 +1,58 @@
+/*	$NetBSD: isa_intr.h,v 1.1 1995/08/02 14:44:57 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1995 Niklas Hallqvist.
+ * All rights reserved.
+ *
+ * Copyright (c) 1995 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Authors: Chris G. Demetriou, Niklas Hallqvist.
+ * 
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+/* Prototypes for ISA-ish I/O interrupt functions. */
+
+/*
+ * XXX
+ * XXX THIS WILL LIKELY HAVE TO BE COMPLETELY CHANGED.
+ * XXX
+ */
+
+struct	isa_intr_fcns {
+	void	(*isa_intr_setup) __P((void));
+
+	void	*(*isa_intr_establish) __P((int irq, int type, int level,
+	    int (*ih_fun)(void *), void *ih_arg));
+	void	(*isa_intr_disestablish) __P((void *handler));
+
+	void	(*isa_iointr) __P((void *framep, int vec));
+};
+
+/*
+ * Global which tells which set of functions are correct
+ * for this machine.
+ */
+struct	isa_intr_fcns *isa_intr_fcns;
+
+extern struct isa_intr_fcns ggbus_intr_fcns;
+extern struct isa_intr_fcns cross_intr_fcns;
diff --git a/sys/arch/amiga/isa/isa_machdep.c b/sys/arch/amiga/isa/isa_machdep.c
new file mode 100644
index 00000000000..5a35142c5ce
--- /dev/null
+++ b/sys/arch/amiga/isa/isa_machdep.c
@@ -0,0 +1,162 @@
+/*	$NetBSD: isa_machdep.c,v 1.1 1995/08/02 14:10:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1995 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <dev/isa/isavar.h>
+
+#include <machine/pio.h>
+
+#include <amiga/amiga/device.h>
+#include <amiga/isa/isa_intr.h>
+
+void	isaattach __P((struct device *, struct device *, void *));
+int	isamatch __P((struct device *, void *, void *));
+
+/*
+ * After careful thought about this issue I decided that allowing only
+ * one isabus configured into a system would be sufficient.  I'm not
+ * lazy, I did the original design with possibilities of multiple ISA
+ * busses, but that made porting of existing drivers a bit harder and
+ * error-prone, as well as I had to write obfuscated code.  This
+ * solution is more in the spirit of KISS.  --niklas@appli.se
+ */
+struct isa_link *isa;
+int isadebug = 0;
+
+struct cfdriver isacd = {
+	NULL, "isa", isamatch, isaattach,
+	DV_DULL, sizeof(struct device), 1
+};
+
+int
+isamatch(parent, cfdata, aux)
+	struct device *parent;
+	void *cfdata, *aux;
+{
+	struct cfdata *cf = cfdata;
+
+#ifdef DEBUG
+	if (isadebug)
+		printf(" isamatch");
+#endif
+
+	/* See if the unit number is valid. */
+	if (cf->cf_unit > 0)
+		return (0);
+
+	return (1);
+}
+
+void
+isaattach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct isa_softc *sc = (struct isa_softc *)self;
+
+	isa = (struct isa_link *)aux;
+
+	printf("\n");
+
+	TAILQ_INIT (&sc->sc_subdevs);
+
+	config_scan(isascan, self);
+}
+
+void *
+isa_intr_establish(intr, type, level, ih_fun, ih_arg)
+	int intr;
+	int type;
+	int level;
+	int (*ih_fun)(void *);
+	void *ih_arg;
+{
+	return (*isa_intr_fcns->isa_intr_establish)(intr, type, level,
+	    ih_fun, ih_arg);
+}
+
+void
+isa_intr_disestablish(handler)
+	void *handler;
+{
+	(*isa_intr_fcns->isa_intr_disestablish)(handler);
+}
+
+void
+isa_outsb(port, addr, cnt)
+	int port;
+	void *addr;
+	int cnt;
+{
+	u_int8_t *p = addr;
+
+	while (cnt--)
+		outb(port, *p++);
+}
+
+void
+isa_insb(port, addr, cnt)
+	int port;
+	void *addr;
+	int cnt;
+{
+	u_int8_t *p = addr;
+
+	while (cnt--)
+		*p++ = inb(port);
+}
+
+void
+isa_outsw(port, addr, cnt)
+	int port;
+	void *addr;
+	int cnt;
+{
+	u_int16_t *p = addr;
+
+	while (cnt--)
+		outw(port, *p++);
+}
+
+void
+isa_insw(port, addr, cnt)
+	int port;
+	void *addr;
+	int cnt;
+{
+	u_int16_t *p = addr;
+
+	while (cnt--)
+		*p++ = inw(port);
+}
diff --git a/sys/arch/amiga/isa/isa_machdep.h b/sys/arch/amiga/isa/isa_machdep.h
new file mode 100644
index 00000000000..9fabef0dfe9
--- /dev/null
+++ b/sys/arch/amiga/isa/isa_machdep.h
@@ -0,0 +1,192 @@
+/*	$NetBSD: isa_machdep.h,v 1.1 1995/07/21 23:07:17 niklas Exp $	*/
+
+/*
+ * Copyright (c) 1995 Niklas Hallqvist
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ISA_MACHDEP_H_
+#define _ISA_MACHDEP_H_
+
+#include <machine/endian.h>
+
+void	isa_insb __P((int port, void *addr, int));
+void	isa_outsb __P((int port, void *addr, int));
+void	isa_insw __P((int port, void *addr, int));
+void	isa_outsw __P((int port, void *addr, int));
+
+/*
+ * The link between the ISA device drivers and the bridgecard used.
+ */
+struct isa_link {
+	struct	device *il_dev;
+	void	(*il_stb)(struct device *, int, u_char);
+	u_char	(*il_ldb)(struct device *, int);
+	void	(*il_stw)(struct device *, int, u_short);
+	u_short	(*il_ldw)(struct device *, int);
+};
+
+extern struct isa_link *isa;
+extern struct cfdriver isacd;
+
+static __inline void
+stb(addr, val)
+	int addr;
+	u_char val;
+{
+	(*isa->il_stb)(isa->il_dev, addr, val);
+}
+
+static __inline u_char
+ldb(addr)
+	int addr;
+{
+	return (*isa->il_ldb)(isa->il_dev, addr);
+}
+
+static __inline void
+stw(addr, val)
+	int addr;
+	u_short val;
+{
+	(*isa->il_stw)(isa->il_dev, addr, val);
+}
+
+static __inline u_short
+ldw(addr)
+	int addr;
+{
+	return (*isa->il_ldw)(isa->il_dev, addr);
+}
+
+/*
+ * Should these be out-of-line instead?  If so, move them to isa.c!
+ * How about unaligned word accesses?  Does the '020 allow them?  If not
+ * we have to do odd to even moves and vice versa bytewise instead of
+ * wordwise.
+ */
+static __inline void
+copy_from_isa (void *from, void *to, int cnt)
+{
+	int a = (int)from;
+
+	if (a & 1 && cnt) {
+		*(u_char *)to = ldb(a++);
+		to = ((u_char *)to) + 1;
+		cnt--;
+	}
+	/* Maybe use Duff's device here... */
+	while (cnt > 1) {
+		*(u_short *)to = ldw(a);
+		a += sizeof(u_short);
+		to = ((u_short *)to) + 1;
+		cnt -= 2;
+	}
+	if (cnt)
+		*(u_char *)to = ldb(a);
+}
+
+static __inline void
+copy_to_isa (const void *from, void *to, int cnt)
+{
+	int a = (int)to;
+
+	if (a & 1 && cnt) {
+		stb(a++, *(u_char *)from);
+		from = ((u_char *)from) + 1;
+		cnt--;
+	}
+	/* Maybe use Duff's device here... */
+	while (cnt > 1) {
+		stw(a, *(u_short *)from);
+		a += sizeof(u_short);
+		from = ((u_short *)from) + 1;
+		cnt -= 2;
+	}
+	if (cnt)
+		stb(a, *(u_char *)from);
+}
+
+static __inline void
+zero_isa (void *addr, int cnt)
+{
+	int a = (int)addr;
+
+	if (a & 1 && cnt) {
+		stb(a++, 0);
+		cnt--;
+	}
+	/* Maybe use Duff's device here... */
+	while (cnt > 1) {
+		stw(a, 0);
+		a += sizeof(u_short);
+		cnt -= 2;
+	}
+	if (cnt)
+		stb(a, 0);
+}
+
+/*
+ * These inlines convert shorts from/to isa (intel) byte order to host
+ * byte-order.  I know both are exactly equal, but I think it make code
+ * more readable to have separate names for them as they indeed have
+ * distinctive functionalities.
+ */
+static __inline u_short
+swap(u_short x)
+{
+	__asm("rolw #8,%0" : "=r" (x) : "0" (x));
+	return x;
+}
+
+static __inline u_short
+itohs(u_short x)
+{
+#if BYTE_ORDER == LITTLE_ENDIAN
+	return x;
+#else
+	return swap(x);
+#endif
+}
+
+static __inline u_short
+htois(u_short x)
+{
+#if BYTE_ORDER == LITTLE_ENDIAN
+	return x;
+#else
+	return swap(x);
+#endif
+}
+
+/*
+ * Given a physical address in the "hole",
+ * return a kernel virtual address.
+ */
+#define	ISA_HOLE_VADDR(p)  ((caddr_t)p)
+
+#endif