Initial effort on a port to the omap35xx platform specifically beagleboard,

however other omap system may be supportable. Not functional until armv7
core changes are complete.

69 files changed, 6771 insertions, 0 deletions

diff --git a/sys/arch/beagle/beagle/ahb.c b/sys/arch/beagle/beagle/ahb.c
new file mode 100644
index 00000000000..a5bb6060a49
--- /dev/null
+++ b/sys/arch/beagle/beagle/ahb.c
@@ -0,0 +1,134 @@
+/* $OpenBSD: ahb.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2005,2008 Dale Rahn <drahn@openbsd.com>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/reboot.h>
+#define _ARM32_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+#include <arch/beagle/beagle/ahb.h>
+#include <arch/arm/armv7/armv7var.h>
+
+struct ahb_softc {
+	struct device sc_dv;
+
+};
+
+int	ahbmatch(struct device *, void *, void *);
+void	ahbattach(struct device *, struct device *, void *);
+int	ahbprint(void *, const char *);
+void	ahbscan(struct device *, void *);
+
+struct arm32_bus_dma_tag ahb_bus_dma_tag = {
+	0,
+	0,
+	NULL,
+	_bus_dmamap_create,
+	_bus_dmamap_destroy,
+	_bus_dmamap_load,
+	_bus_dmamap_load_mbuf,
+	_bus_dmamap_load_uio,
+	_bus_dmamap_load_raw,
+	_bus_dmamap_unload,
+	_bus_dmamap_sync,
+	_bus_dmamem_alloc,
+	_bus_dmamem_free,
+	_bus_dmamem_map,
+	_bus_dmamem_unmap,
+	_bus_dmamem_mmap,
+};
+
+
+struct cfattach ahb_ca = {
+	sizeof(struct ahb_softc), ahbmatch, ahbattach
+};
+
+struct cfdriver ahb_cd = {
+	NULL, "ahb", DV_DULL, 1
+};
+
+int
+ahbmatch(struct device *parent, void *cfdata, void *aux)
+{
+	return (1);
+}
+
+void
+ahbattach(struct device *parent, struct device *self, void *aux)
+{
+	/*
+	struct ahb_softc *sc = (struct ahb_softc *)self; 
+	*/
+
+	printf("\n");
+
+	config_scan(ahbscan, self);
+}
+
+void
+ahbscan(struct device *parent, void *match)
+{
+	/*
+	struct ahb_softc *sc = (struct ahb_softc *)parent;
+	*/
+	struct device *dev = match;
+	struct cfdata *cf = dev->dv_cfdata;
+	struct ahb_attach_args aa;
+
+	if (cf->cf_fstate == FSTATE_STAR) {
+		printf("ahb does not deal with dev* entries\n");
+		free(dev, M_DEVBUF);
+		return;
+	}
+
+        if (autoconf_verbose)
+		printf(">>> probing for %s%d\n", cf->cf_driver->cd_name,
+		    cf->cf_unit);
+
+	aa.aa_addr = cf->cf_loc[0];
+	aa.aa_size = cf->cf_loc[1];
+	aa.aa_intr = cf->cf_loc[2];
+	aa.aa_iot = &armv7_bs_tag;
+	aa.aa_dmat = &ahb_bus_dma_tag;
+	if ((*cf->cf_attach->ca_match)(parent, dev, &aa) > 0) {
+		if (autoconf_verbose)
+			printf(">>> probing for %s%d succeeded\n",
+			    cf->cf_driver->cd_name, cf->cf_unit);
+		config_attach(parent, dev, &aa, ahbprint);
+	} else {
+		if (autoconf_verbose)
+			printf(">>> probing for %s%d failed\n",
+			    cf->cf_driver->cd_name, cf->cf_unit);
+		free(dev, M_DEVBUF);
+	}
+}
+
+int
+ahbprint(void *aux, const char *str)
+{
+	struct ahb_attach_args *aa = aux;
+
+	if (aa->aa_addr != -1)
+		printf(" addr 0x%x", aa->aa_addr);
+	if (aa->aa_size != 0)
+		printf(" size 0x%x", aa->aa_size);
+	if (aa->aa_intr != -1)
+		printf(" intr %d", aa->aa_intr);
+	return (QUIET);
+}
diff --git a/sys/arch/beagle/beagle/ahb.h b/sys/arch/beagle/beagle/ahb.h
new file mode 100644
index 00000000000..960420f4cf2
--- /dev/null
+++ b/sys/arch/beagle/beagle/ahb.h
@@ -0,0 +1,29 @@
+/* $OpenBSD: ahb.h,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2005,2008 Dale Rahn <drahn@drahn.com>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+struct ahb_attach_args {
+	int	aa_addr;
+	int	aa_size;
+	int	aa_intr;
+	bus_space_tag_t	aa_iot;
+	bus_dma_tag_t aa_dmat;
+	char	*aa_name;
+};
+
+/* XXX */
+void *avic_intr_establish(int irqno, int level, int (*func)(void *),
+    void *arg, char *name);
diff --git a/sys/arch/beagle/beagle/autoconf.c b/sys/arch/beagle/beagle/autoconf.c
new file mode 100644
index 00000000000..47f6f688050
--- /dev/null
+++ b/sys/arch/beagle/beagle/autoconf.c
@@ -0,0 +1,148 @@
+/*	$OpenBSD: autoconf.c,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: autoconf.c,v 1.2 2001/09/05 16:17:36 matt Exp $	*/
+
+/*
+ * Copyright (c) 1994-1998 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe for
+ *      the NetBSD project.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RiscBSD kernel project
+ *
+ * autoconf.c
+ *
+ * Autoconfiguration functions
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/reboot.h>
+#include <sys/disklabel.h>
+#include <sys/device.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <machine/bootconfig.h>
+#include <machine/intr.h>
+
+struct device *booted_device;
+int booted_partition;
+struct device *bootdv = NULL;
+extern char *boot_file;
+
+void dumpconf(void);
+
+void
+device_register(struct device *dev, void *aux)
+{
+}
+
+/*
+ * void cpu_configure()
+ *
+ * Configure all the root devices
+ * The root devices are expected to configure their own children
+ */
+void
+cpu_configure(void)
+{
+	softintr_init();
+
+	/*
+	 * Since various PCI interrupts could be routed via the ICU
+	 * (for PCI devices in the bridge) we need to set up the ICU
+	 * now so that these interrupts can be established correctly
+	 * i.e. This is a hack.
+	 */
+
+	config_rootfound("mainbus", NULL);
+
+	/*
+	 * We can not know which is our root disk, defer
+	 * until we can checksum blocks to figure it out.
+	 */
+	cold = 0;
+
+	/* Time to start taking interrupts so lets open the flood gates .... */
+	(void)spl0();
+
+}
+
+/*
+ * Now that we are fully operational, we can checksum the
+ * disks, and using some heuristics, hopefully are able to
+ * always determine the correct root disk.
+ */
+void
+diskconf(void)
+{
+	dev_t tmpdev;
+
+#if 0
+	/*
+	 * Configure root, swap, and dump area.  This is
+	 * currently done by running the same checksum
+	 * algorithm over all known disks, as was done in
+	 * /boot.  Then we basically fixup the *dev vars
+	 * from the info we gleaned from this.
+	 */
+	dkcsumattach();
+#endif
+
+	/* Lookup boot device from boot if not set by configuration */
+	if (bootdv == NULL) {
+		int len;
+		char *p;
+
+		/* boot_file is of the form wd0a:/bsd, we want 'wd0a' */
+		if ((p = strchr(boot_file, ':')) != NULL)
+			len = p - boot_file;
+		else
+			len = strlen(boot_file);
+		
+		bootdv = parsedisk(boot_file, len, 0, &tmpdev);
+	}
+	if (bootdv == NULL)
+		printf("boot device: lookup '%s' failed.\n", boot_file);
+	else
+		printf("boot device: %s\n", bootdv->dv_xname);
+	setroot(bootdv, 0, RB_USERREQ);
+	dumpconf();
+}
+
+struct nam2blk nam2blk[] = {
+	{ "wd",		16 },
+	{ "sd",		24 },
+	{ "cd",		26 },
+	{ "rd",		18 },
+	{ "raid",	71 },
+	{ NULL,		-1 }
+};
+
diff --git a/sys/arch/beagle/beagle/beagle_machdep.c b/sys/arch/beagle/beagle/beagle_machdep.c
new file mode 100644
index 00000000000..732343d24a9
--- /dev/null
+++ b/sys/arch/beagle/beagle/beagle_machdep.c
@@ -0,0 +1,999 @@
+/*	$OpenBSD: beagle_machdep.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*	$NetBSD: lubbock_machdep.c,v 1.2 2003/07/15 00:25:06 lukem Exp $ */
+
+/*
+ * Copyright (c) 2002, 2003  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of Genetec Corporation may not be used to endorse or 
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Machine dependant functions for kernel setup for 
+ * Intel DBPXA250 evaluation board (a.k.a. Lubbock).
+ * Based on iq80310_machhdep.c
+ */
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1997,1998 Mark Brinicombe.
+ * Copyright (c) 1997,1998 Causality Limited.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe
+ *	for the NetBSD Project.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Machine dependant functions for kernel setup for Intel IQ80310 evaluation
+ * boards using RedBoot firmware.
+ */
+
+/*
+ * DIP switches:
+ *
+ * S19: no-dot: set RB_KDB.  enter kgdb session.
+ * S20: no-dot: set RB_SINGLE. don't go multi user mode.
+ */
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/exec.h>
+#include <sys/proc.h>
+#include <sys/msgbuf.h>
+#include <sys/reboot.h>
+#include <sys/termios.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <sys/conf.h>
+#include <sys/queue.h>
+#include <sys/device.h>
+#include <dev/cons.h>
+#include <dev/ic/smc91cxxreg.h>
+
+#include <machine/db_machdep.h>
+#include <ddb/db_sym.h>
+#include <ddb/db_extern.h>
+
+#include <machine/bootconfig.h>
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/frame.h>
+#include <arm/undefined.h>
+#include <arm/machdep.h>
+
+#include <arm/armv7/armv7reg.h>
+#include <arm/armv7/armv7var.h>
+
+#include <machine/machine_reg.h>
+
+
+#include "wsdisplay.h"
+
+/* Kernel text starts 2MB in from the bottom of the kernel address space. */
+#define	KERNEL_TEXT_BASE	(KERNEL_BASE + 0x00000000)
+#define	KERNEL_VM_BASE		(KERNEL_BASE + 0x04000000)
+
+/*
+ * The range 0xc1000000 - 0xccffffff is available for kernel VM space
+ * Core-logic registers and I/O mappings occupy 0xfd000000 - 0xffffffff
+ */
+/*
+#define KERNEL_VM_SIZE		0x0C000000
+*/
+#define KERNEL_VM_SIZE		0x10000000
+
+
+/*
+ * Address to call from cpu_reset() to reset the machine.
+ * This is machine architecture dependant as it varies depending
+ * on where the ROM appears when you turn the MMU off.
+ */
+
+u_int cpu_reset_address = 0;
+
+/* Define various stack sizes in pages */
+#define IRQ_STACK_SIZE	1
+#define ABT_STACK_SIZE	1
+#ifdef IPKDB
+#define UND_STACK_SIZE	2
+#else
+#define UND_STACK_SIZE	1
+#endif
+
+BootConfig bootconfig;		/* Boot config storage */
+char *boot_args = NULL;
+char *boot_file = "";
+
+vaddr_t physical_start;
+vaddr_t physical_freestart;
+vaddr_t physical_freeend;
+vaddr_t physical_end;
+u_int free_pages;
+vaddr_t pagetables_start;
+int physmem = 0;
+
+/*int debug_flags;*/
+#ifndef PMAP_STATIC_L1S
+int max_processes = 64;			/* Default number */
+#endif	/* !PMAP_STATIC_L1S */
+
+/* Physical and virtual addresses for some global pages */
+pv_addr_t systempage;
+pv_addr_t irqstack;
+pv_addr_t undstack;
+pv_addr_t abtstack;
+extern pv_addr_t kernelstack;
+pv_addr_t minidataclean;
+
+vaddr_t msgbufphys;
+
+extern u_int data_abort_handler_address;
+extern u_int prefetch_abort_handler_address;
+extern u_int undefined_handler_address;
+
+#ifdef PMAP_DEBUG
+extern int pmap_debug_level;
+#endif
+
+#define KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
+#define KERNEL_PT_KERNEL	1	/* Page table for mapping kernel */
+#define	KERNEL_PT_KERNEL_NUM	32
+#define KERNEL_PT_VMDATA	(KERNEL_PT_KERNEL+KERNEL_PT_KERNEL_NUM)
+				        /* Page tables for mapping kernel VM */
+#define	KERNEL_PT_VMDATA_NUM	8	/* start with 16MB of KVM */
+#define NUM_KERNEL_PTS		(KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
+
+pv_addr_t kernel_pt_table[NUM_KERNEL_PTS];
+
+extern struct user *proc0paddr;
+
+/* Prototypes */
+
+void	omdog_reset(void);
+void	beagle_powerdown(void);
+
+#define	BOOT_STRING_MAGIC 0x4f425344
+
+char	bootargs[MAX_BOOT_STRING];
+void	process_kernel_args(char *);
+
+void	consinit(void);
+void	early_clkman(u_int, int);
+void	kgdb_port_init(void);
+void	change_clock(uint32_t v);
+
+bs_protos(bs_notimpl);
+
+#include "com.h"
+#if NCOM > 0
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+#endif
+
+#ifndef CONSPEED
+#define CONSPEED B115200	/* What u-boot */
+#endif
+#ifndef CONMODE
+#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
+#endif
+
+int comcnspeed = CONSPEED;
+int comcnmode = CONMODE;
+
+
+/*
+ *
+ */
+void
+beagle_powerdown(void)
+{
+
+	/*
+	pxa2x0_watchdog_boot();
+	*/
+}
+
+/*
+ * void boot(int howto, char *bootstr)
+ *
+ * Reboots the system
+ *
+ * Deal with any syncing, unmounting, dumping and shutdown hooks,
+ * then reset the CPU.
+ */
+void
+boot(int howto)
+{
+#ifdef DIAGNOSTIC
+	/* info */
+	printf("boot: howto=%08x curproc=%p\n", howto, curproc);
+#endif
+
+	/*
+	 * If we are still cold then hit the air brakes
+	 * and crash to earth fast
+	 */
+	if (cold) {
+		doshutdownhooks();
+		if ((howto & (RB_HALT | RB_USERREQ)) != RB_USERREQ) {
+			printf("The operating system has halted.\n");
+			printf("Please press any key to reboot.\n\n");
+			cngetc();
+		}
+		printf("rebooting...\n");
+		delay(500000);
+		omdog_reset();
+		printf("reboot failed; spinning\n");
+		while(1);
+		/*NOTREACHED*/
+	}
+
+	/* Disable console buffering */
+/*	cnpollc(1);*/
+
+	/*
+	 * If RB_NOSYNC was not specified sync the discs.
+	 * Note: Unless cold is set to 1 here, syslogd will die during the
+	 * unmount.  It looks like syslogd is getting woken up only to find
+	 * that it cannot page part of the binary in as the filesystem has
+	 * been unmounted.
+	 */
+	if (!(howto & RB_NOSYNC))
+		bootsync(howto);
+
+	/* Say NO to interrupts */
+	splhigh();
+
+	/* Do a dump if requested. */
+	if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
+		dumpsys();
+	
+	/* Run any shutdown hooks */
+	doshutdownhooks();
+
+	/* Make sure IRQ's are disabled */
+	IRQdisable;
+
+	if (howto & RB_HALT) {
+		if (howto & RB_POWERDOWN) {
+
+			printf("\nAttempting to power down...\n");
+			delay(500000);
+			beagle_powerdown();
+		}
+
+		printf("The operating system has halted.\n");
+		printf("Please press any key to reboot.\n\n");
+		cngetc();
+	}
+
+	printf("rebooting...\n");
+	delay(500000);
+	omdog_reset();
+	printf("reboot failed; spinning\n");
+	while(1);
+	/*NOTREACHED*/
+}
+
+static __inline
+pd_entry_t *
+read_ttb(void)
+{
+  long ttb;
+
+  __asm __volatile("mrc	p15, 0, %0, c2, c0, 0" : "=r" (ttb));
+
+
+  return (pd_entry_t *)(ttb & ~((1<<14)-1));
+}
+
+#if 1
+#define VERBOSE_INIT_ARM
+#endif
+
+/*
+ * simple memory mapping function used in early bootstrap stage
+ * before pmap is initialized.
+ * size and cacheability are ignored and map one section with nocache.
+ */
+static vaddr_t section_free = 0xfd400000; /* XXX - huh */
+
+int bootstrap_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
+    int cacheable, bus_space_handle_t *bshp);
+int
+bootstrap_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
+    int cacheable, bus_space_handle_t *bshp)
+{
+	u_long startpa;
+	vaddr_t va;
+	pd_entry_t *pagedir = read_ttb();
+	/* This assumes PA==VA for page directory */
+
+	va = section_free;
+	section_free += L1_S_SIZE;
+
+	/*
+	startpa = trunc_page(bpa);
+	*/
+	startpa = bpa & ~L1_S_OFFSET;
+	pmap_map_section((vaddr_t)pagedir, va, startpa, 
+	    VM_PROT_READ | VM_PROT_WRITE, PTE_NOCACHE);
+	cpu_tlb_flushD();
+
+	*bshp = (bus_space_handle_t)(va + (bpa - startpa));
+
+	return(0);
+}
+
+static void
+copy_io_area_map(pd_entry_t *new_pd)
+{
+	pd_entry_t *cur_pd = read_ttb();
+	vaddr_t va;
+
+	for (va = MACHINE_IO_AREA_VBASE;
+	     (cur_pd[va>>L1_S_SHIFT] & L1_TYPE_MASK) == L1_TYPE_S;
+	     va += L1_S_SIZE) {
+
+		new_pd[va>>L1_S_SHIFT] = cur_pd[va>>L1_S_SHIFT];
+		if (va == (0 - L1_S_SIZE))
+			break; /* STUPID */
+
+	}
+}
+
+/*
+ * u_int initarm(...)
+ *
+ * Initial entry point on startup. This gets called before main() is
+ * entered.
+ * It should be responsible for setting up everything that must be
+ * in place when main is called.
+ * This includes
+ *   Taking a copy of the boot configuration structure.
+ *   Initialising the physical console so characters can be printed.
+ *   Setting up page tables for the kernel
+ *   Relocating the kernel to the bottom of physical memory
+ */
+u_int
+initarm(void *arg)
+{
+	int loop;
+	int loop1;
+	u_int l1pagetable;
+	pv_addr_t kernel_l1pt;
+	paddr_t memstart;
+	psize_t memsize;
+
+#if 0
+	int led_data = 0;
+#endif
+	/* early bus_space_map support */
+	struct bus_space tmp_bs_tag;
+	int	(*map_func_save)(void *, bus_addr_t, bus_size_t, int, 
+	    bus_space_handle_t *);
+
+	/*
+	 * Heads up ... Setup the CPU / MMU / TLB functions
+	 */
+	if (set_cpufuncs())
+		panic("cpu not recognized!");
+
+	intc_intr_bootstrap(0x48200000); /* XXX - constant */
+
+#if 0
+	/* Calibrate the delay loop. */
+#endif
+
+
+	/*
+	 * Temporarily replace bus_space_map() functions so that
+	 * console devices can get mapped.
+	 *
+	 * Note that this relies upon the fact that both regular
+	 * and a4x bus_space tags use the same map function.
+	 */
+#if defined(CPU_ARMv7) 
+	tmp_bs_tag = armv7_bs_tag;
+	map_func_save = armv7_bs_tag.bs_map;
+	armv7_bs_tag.bs_map = bootstrap_bs_map;
+	armv7_a4x_bs_tag.bs_map = bootstrap_bs_map;
+#endif
+	tmp_bs_tag.bs_map = bootstrap_bs_map;
+
+	/* setup a serial console for very early boot */
+	consinit();
+
+	/* Talk to the user */
+	printf("\nOpenBSD/beagle booting ...\n");
+
+	/*
+	 * Examine the boot args string for options we need to know about
+	 * now.
+	 */
+	process_kernel_args("");
+#ifdef RAMDISK_HOOKS
+        boothowto |= RB_DFLTROOT;
+#endif /* RAMDISK_HOOKS */
+
+
+	{
+		/* XXX - scma11 for now, fix memory sizing */
+		memstart = SDRAM_START;
+		memsize =  0x02000000; /* 32MB */
+	}
+
+
+#define DEBUG
+#ifdef DEBUG
+	printf("initarm: Configuring system ...\n");
+#endif
+
+	/* Fake bootconfig structure for the benefit of pmap.c */
+	/* XXX must make the memory description h/w independant */
+	bootconfig.dramblocks = 1;
+	bootconfig.dram[0].address = memstart;
+	bootconfig.dram[0].pages = memsize / PAGE_SIZE;
+
+	/*
+	 * Set up the variables that define the availablilty of
+	 * physical memory.  For now, we're going to set
+	 * physical_freestart to 0xa0200000 (where the kernel
+	 * was loaded), and allocate the memory we need downwards.
+	 * If we get too close to the page tables that RedBoot
+	 * set up, we will panic.  We will update physical_freestart
+	 * and physical_freeend later to reflect what pmap_bootstrap()
+	 * wants to see.
+	 *
+	 * XXX pmap_bootstrap() needs an enema.
+	 */
+	physical_start = bootconfig.dram[0].address;
+	physical_end = physical_start + (bootconfig.dram[0].pages * PAGE_SIZE);
+
+	{
+		extern char _end[];
+		physical_freestart = (((unsigned long)_end - KERNEL_TEXT_BASE +0xfff) & ~0xfff);
+		physical_freeend = memstart+memsize;
+	}
+
+	physmem = (physical_end - physical_start) / PAGE_SIZE;
+
+#ifdef DEBUG
+	/* Tell the user about the memory */
+	printf("physmemory: %d pages at 0x%08lx -> 0x%08lx\n", physmem,
+	    physical_start, physical_end - 1);
+#endif
+
+	/*
+	 * Okay, the kernel starts 2MB in from the bottom of physical
+	 * memory.  We are going to allocate our bootstrap pages downwards
+	 * from there.
+	 *
+	 * We need to allocate some fixed page tables to get the kernel
+	 * going.  We allocate one page directory and a number of page
+	 * tables and store the physical addresses in the kernel_pt_table
+	 * array.
+	 *
+	 * The kernel page directory must be on a 16K boundary.  The page
+	 * tables must be on 4K bounaries.  What we do is allocate the
+	 * page directory on the first 16K boundary that we encounter, and
+	 * the page tables on 4K boundaries otherwise.  Since we allocate
+	 * at least 3 L2 page tables, we are guaranteed to encounter at
+	 * least one 16K aligned region.
+	 */
+
+#ifdef VERBOSE_INIT_ARM
+	printf("Allocating page tables\n");
+#endif
+
+	free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE;
+
+#ifdef VERBOSE_INIT_ARM
+	printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n",
+	       physical_freestart, free_pages, free_pages);
+#endif
+
+	/* Define a macro to simplify memory allocation */
+#define	valloc_pages(var, np)				\
+	alloc_pages((var).pv_pa, (np));			\
+	(var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start;
+
+#define alloc_pages(var, np)				\
+	physical_freeend -= ((np) * PAGE_SIZE);		\
+	if (physical_freeend < physical_freestart)	\
+		panic("initarm: out of memory");	\
+	(var) = physical_freeend;			\
+	free_pages -= (np);				\
+	memset((char *)(var), 0, ((np) * PAGE_SIZE));
+
+	loop1 = 0;
+	kernel_l1pt.pv_pa = 0;
+	for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) {
+		/* Are we 16KB aligned for an L1 ? */
+		if (((physical_freeend - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) == 0
+		    && kernel_l1pt.pv_pa == 0) {
+			valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
+		} else {
+			valloc_pages(kernel_pt_table[loop1],
+			    L2_TABLE_SIZE / PAGE_SIZE);
+			++loop1;
+		}
+	}
+
+	/* This should never be able to happen but better confirm that. */
+	if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (L1_TABLE_SIZE-1)) != 0)
+		panic("initarm: Failed to align the kernel page directory");
+
+	/*
+	 * Allocate a page for the system page mapped to V0x00000000
+	 * This page will just contain the system vectors and can be
+	 * shared by all processes.
+	 */
+	alloc_pages(systempage.pv_pa, 1);
+
+	/* Allocate stacks for all modes */
+	valloc_pages(irqstack, IRQ_STACK_SIZE);
+	valloc_pages(abtstack, ABT_STACK_SIZE);
+	valloc_pages(undstack, UND_STACK_SIZE);
+	valloc_pages(kernelstack, UPAGES);
+
+	/* Allocate enough pages for cleaning the Mini-Data cache. */
+
+#ifdef VERBOSE_INIT_ARM
+	printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa,
+	    irqstack.pv_va); 
+	printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa,
+	    abtstack.pv_va); 
+	printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa,
+	    undstack.pv_va); 
+	printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa,
+	    kernelstack.pv_va); 
+#endif
+
+	/*
+	 * XXX Defer this to later so that we can reclaim the memory
+	 * XXX used by the RedBoot page tables.
+	 */
+	alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / PAGE_SIZE);
+
+	/*
+	 * Ok we have allocated physical pages for the primary kernel
+	 * page tables
+	 */
+
+#ifdef VERBOSE_INIT_ARM
+	printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa);
+#endif
+
+	/*
+	 * Now we start construction of the L1 page table
+	 * We start by mapping the L2 page tables into the L1.
+	 * This means that we can replace L1 mappings later on if necessary
+	 */
+	l1pagetable = kernel_l1pt.pv_pa;
+
+	/* Map the L2 pages tables in the L1 page table */
+	pmap_link_l2pt(l1pagetable, 0x00000000,
+	    &kernel_pt_table[KERNEL_PT_SYS]);
+
+	for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
+		pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000,
+		    &kernel_pt_table[KERNEL_PT_KERNEL + loop]);
+
+	for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
+		pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
+		    &kernel_pt_table[KERNEL_PT_VMDATA + loop]);
+
+	/* update the top of the kernel VM */
+	pmap_curmaxkvaddr =
+	    KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000);
+
+#ifdef VERBOSE_INIT_ARM
+	printf("Mapping kernel\n");
+#endif
+
+	/* Now we fill in the L2 pagetable for the kernel static code/data */
+	{
+		extern char etext[], _end[];
+		size_t textsize = (u_int32_t) etext - KERNEL_TEXT_BASE;
+		size_t totalsize = (u_int32_t) _end - KERNEL_TEXT_BASE;
+		u_int logical;
+
+		textsize = (textsize + PGOFSET) & ~PGOFSET;
+		totalsize = (totalsize + PGOFSET) & ~PGOFSET;
+		
+		logical = 0x00000000;	/* offset of kernel in RAM */
+
+		logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
+		    physical_start + logical, textsize,
+		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+		logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
+		    physical_start + logical, totalsize - textsize,
+		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	}
+
+#ifdef VERBOSE_INIT_ARM
+	printf("Constructing L2 page tables\n");
+#endif
+
+	/* Map the stack pages */
+	pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
+	    IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
+	    ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
+	    UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
+	    UPAGES * PAGE_SIZE, VM_PROT_READ | VM_PROT_WRITE, PTE_CACHE);
+
+	pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
+	    L1_TABLE_SIZE, VM_PROT_READ | VM_PROT_WRITE, PTE_PAGETABLE);
+
+	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
+		pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
+		    kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
+		    VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
+	}
+
+	/* Map the Mini-Data cache clean area. */
+
+	/* Map the vector page. */
+#if 1
+	/* MULTI-ICE requires that page 0 is NC/NB so that it can download the
+	 * cache-clean code there.  */
+	pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa,
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
+#else
+	pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa,
+	    VM_PROT_EXEC|VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+#endif
+
+	/*
+	 * map integrated peripherals at same address in l1pagetable
+	 * so that we can continue to use console.
+	 */
+	copy_io_area_map((pd_entry_t *)l1pagetable);
+
+
+	/*
+	 * Now we have the real page tables in place so we can switch to them.
+	 * Once this is done we will be running with the REAL kernel page
+	 * tables.
+	 */
+
+	/*
+	 * Update the physical_freestart/physical_freeend/free_pages
+	 * variables.
+	 */
+	{
+		extern char _end[];
+
+		physical_freestart = physical_start +
+		    (((((u_int32_t) _end) + PGOFSET) & ~PGOFSET) -
+		     KERNEL_BASE);
+		physical_freeend = physical_end;
+		free_pages =
+		    (physical_freeend - physical_freestart) / PAGE_SIZE;
+	}
+
+	/* be a client to all domains */
+	cpu_domains(0x55555555);
+	/* Switch tables */
+#ifdef VERBOSE_INIT_ARM
+	printf("freestart = 0x%08lx, free_pages = %d (0x%x)\n",
+	       physical_freestart, free_pages, free_pages);
+	printf("switching to new L1 page table  @%#lx...", kernel_l1pt.pv_pa);
+#endif
+
+	/* set new intc register address so that splfoo() doesn't
+	   touch illegal address.  */
+	intc_intr_bootstrap(0x48200000); /* XXX - constant */
+
+	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
+	setttb(kernel_l1pt.pv_pa);
+	cpu_tlb_flushID();
+	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
+
+	/*
+	 * Moved from cpu_startup() as data_abort_handler() references
+	 * this during uvm init
+	 */
+	proc0paddr = (struct user *)kernelstack.pv_va;
+	proc0.p_addr = proc0paddr;
+
+#ifdef VERBOSE_INIT_ARM
+	printf("bootstrap done.\n");
+#endif
+
+	arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL);
+
+	/*
+	 * Pages were allocated during the secondary bootstrap for the
+	 * stacks for different CPU modes.
+	 * We must now set the r13 registers in the different CPU modes to
+	 * point to these stacks.
+	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
+	 * of the stack memory.
+	 */
+#ifdef VERBOSE_INIT_ARM
+	printf("init subsystems: stacks ");
+#endif
+
+	set_stackptr(PSR_IRQ32_MODE,
+	    irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_ABT32_MODE,
+	    abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_UND32_MODE,
+	    undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
+
+	/*
+	 * Well we should set a data abort handler.
+	 * Once things get going this will change as we will need a proper
+	 * handler.
+	 * Until then we will use a handler that just panics but tells us
+	 * why.
+	 * Initialisation of the vectors will just panic on a data abort.
+	 * This just fills in a slighly better one.
+	 */
+#ifdef VERBOSE_INIT_ARM
+	printf("vectors ");
+#endif
+	data_abort_handler_address = (u_int)data_abort_handler;
+	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
+	undefined_handler_address = (u_int)undefinedinstruction_bounce;
+
+	/* Initialise the undefined instruction handlers */
+#ifdef VERBOSE_INIT_ARM
+	printf("undefined ");
+#endif
+	undefined_init();
+
+	/* Load memory into UVM. */
+#ifdef VERBOSE_INIT_ARM
+	printf("page ");
+#endif
+	uvm_setpagesize();        /* initialize PAGE_SIZE-dependent variables */
+	uvm_page_physload(atop(physical_freestart), atop(physical_freeend),
+	    atop(physical_freestart), atop(physical_freeend),
+	    VM_FREELIST_DEFAULT);
+
+	/* Boot strap pmap telling it where the kernel page table is */
+#ifdef VERBOSE_INIT_ARM
+	printf("pmap ");
+#endif
+	pmap_bootstrap((pd_entry_t *)kernel_l1pt.pv_va, KERNEL_VM_BASE,
+	    KERNEL_VM_BASE + KERNEL_VM_SIZE);
+
+#ifdef __HAVE_MEMORY_DISK__
+	md_root_setconf(memory_disk, sizeof memory_disk);
+#endif
+
+#ifdef IPKDB
+	/* Initialise ipkdb */
+	ipkdb_init();
+	if (boothowto & RB_KDB)
+		ipkdb_connect(0);
+#endif
+
+	/*
+	 * Restore proper bus_space operation, now that pmap is initialized.
+	 */
+#if defined(CPU_ARMv7) 
+	armv7_bs_tag.bs_map = map_func_save;
+	armv7_a4x_bs_tag.bs_map = map_func_save;
+#endif
+
+#ifdef DDB
+	db_machine_init();
+
+	/* Firmware doesn't load symbols. */
+	ddb_init();
+
+	if (boothowto & RB_KDB)
+		Debugger();
+#endif
+
+	/* We return the new stack pointer address */
+	return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
+}
+
+const char *console = "ffuart";
+
+
+void
+process_kernel_args(char *args)
+{
+	char *cp = args;
+
+	if (cp == NULL || *(int *)cp != BOOT_STRING_MAGIC) {
+		boothowto = RB_AUTOBOOT;
+		return;
+	}
+
+	/* Eat the cookie */
+	*(int *)cp = 0;
+	cp += sizeof(int);
+
+	boothowto = 0;
+
+	/* Make a local copy of the bootargs */
+	strncpy(bootargs, cp, MAX_BOOT_STRING - sizeof(int));
+
+	cp = bootargs;
+	boot_file = bootargs;
+
+	/* Skip the kernel image filename */
+	while (*cp != ' ' && *cp != 0)
+		++cp;
+
+	if (*cp != 0)
+		*cp++ = 0;
+
+	while (*cp == ' ')
+		++cp;
+
+	boot_args = cp;
+
+	printf("bootfile: %s\n", boot_file);
+	printf("bootargs: %s\n", boot_args);
+
+	/* Setup pointer to boot flags */
+	while (*cp != '-')
+		if (*cp++ == '\0')
+			return;
+
+	for (;*++cp;) {
+		int fl;
+
+		fl = 0;
+		switch(*cp) {
+		case 'a':
+			fl |= RB_ASKNAME;
+			break;
+		case 'c':
+			fl |= RB_CONFIG;
+			break;
+		case 'd':
+			fl |= RB_KDB;
+			break;
+		case 's':
+			fl |= RB_SINGLE;
+			break;
+		/* XXX undocumented console switching flags */
+		case '0':
+			console = "ffuart";
+			break;
+		case '1':
+			console = "btuart";
+			break;
+		case '2':
+			console = "stuart";
+			break;
+		case 'g':
+			console = "glass";
+			break;
+		default:
+			printf("unknown option `%c'\n", *cp);
+			break;
+		}
+		boothowto |= fl;
+	}
+}
+
+
+void
+consinit(void)
+{
+	static int consinit_called = 0;
+#if NCOM > 0
+	paddr_t paddr;
+#endif
+		
+	if (consinit_called != 0)
+		return;   
+		
+	consinit_called = 1;
+
+#if NCOM > 0
+	paddr = 0x49020000; /* XXX - addr */
+#if defined(CPU_ARMv7) 
+	comcnattach(&armv7_a4x_bs_tag, paddr, comcnspeed, 48000000, comcnmode);
+#endif
+	comdefaultrate = comcnspeed;
+#endif /* NCOM */
+}
+
+
+int glass_console = 0;
+
+void
+board_startup(void)
+{
+        if (boothowto & RB_CONFIG) {
+#ifdef BOOT_CONFIG
+		user_config();
+#else
+		printf("kernel does not support -c; continuing..\n");
+#endif
+	}
+}
diff --git a/sys/arch/beagle/beagle/beagle_start.S b/sys/arch/beagle/beagle/beagle_start.S
new file mode 100644
index 00000000000..1638de583da
--- /dev/null
+++ b/sys/arch/beagle/beagle/beagle_start.S
@@ -0,0 +1,177 @@
+/*	$OpenBSD: beagle_start.S,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: lubbock_start.S,v 1.1 2003/06/18 10:51:15 bsh Exp $ */
+
+/*
+ * Copyright (c) 2002, 2003  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of Genetec Corporation may not be used to endorse or 
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+#include <arm/armreg.h>
+#include <arm/pte.h>
+#include <arm/pmap.h>		/* for PMAP_DOMAIN_KERNEL */
+
+#ifndef SDRAM_START
+#define SDRAM_START	0x80000000
+#endif
+
+/*
+ * CPWAIT -- Canonical method to wait for CP15 update.
+ * NOTE: Clobbers the specified temp reg.
+ * copied from arm/arm/cpufunc_asm_xscale.S
+ * XXX: better be in a common header file.
+ */
+#define	CPWAIT_BRANCH							 \
+	sub	pc, pc, #4
+
+#define	CPWAIT(tmp)							 \
+	mrc	p15, 0, tmp, c2, c0, 0	/* arbitrary read of CP15 */	;\
+	mov	tmp, tmp		/* wait for it to complete */	;\
+	CPWAIT_BRANCH			/* branch to next insn */
+	
+/*
+ * Kernel start routine for DBPXA250 (Lubbock)
+ * this code is excuted at the very first after the kernel is loaded
+ * by RedBoot.
+ */
+	.text
+
+	.global	_C_LABEL(bootstrap_start)
+_C_LABEL(bootstrap_start):
+	/* Are we running on ROM ? */
+	cmp     pc, #0x06000000
+	bhi     bootstrap_start_ram
+
+	/* move me to RAM
+	 * XXX: we can use memcpy if it is PIC
+	 */
+	ldr r1, Lcopy_size
+	adr r0, _C_LABEL(bootstrap_start)
+	add r1, r1, #3
+	mov r1, r1, LSR #2
+	mov r2, #SDRAM_START
+	add r2, r2, #0x00200000
+	mov r4, r2
+
+5:	ldr r3,[r0],#4
+	str r3,[r2],#4
+	subs r1,r1,#1
+	bhi 5b
+
+	cmp	pc, r5
+	/* Jump to RAM */
+	ldr r0, Lstart_off
+
+	blo 1f
+	/* if we were running out of virtual mapped space, disable mmu */
+	mov	r2, #0
+	mov     r1, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
+	mcr     15, 0, r1, c1, c0, 0
+	mcrne   15, 0, r2, c8, c7, 0    /* nail I+D TLB on ARMv4 and greater */
+	
+1:
+	add pc, r4, r0
+
+Lcopy_size:	.word _edata-_C_LABEL(bootstrap_start)
+Lstart_off:	.word bootstrap_start_ram-_C_LABEL(bootstrap_start)
+
+bootstrap_start_ram:	
+	/*
+	 *  Kernel is loaded in SDRAM (0xa0200000..), and is expected to run
+	 *  in VA 0xc0200000..  
+	 */
+
+	mrc	p15, 0, r0, c2, c0, 0	/* get ttb prepared by redboot */
+	adr	r4, mmu_init_table2
+	
+/*
+#define BUILD_STARTUP_PAGETABLE
+*/
+#ifdef BUILD_STARTUP_PAGETABLE
+	mrc	p15, 0, r2, c1, c0, 0
+	mov	r2, #0
+	tst	r2, #CPU_CONTROL_MMU_ENABLE /* we already have a page table? */
+	bne	3f
+
+	/* build page table from scratch */
+	ldr	r0, Lstartup_pagetable
+	adr	r4, mmu_init_table
+	b	3f
+
+2:
+	str	r3, [r0, r2]
+	add	r2, r2, #4
+	add	r3, r3, #(L1_S_SIZE)
+	adds	r1, r1, #-1
+	bhi	2b
+3:	
+	ldmia	r4!, {r1,r2,r3}   /* # of sections, PA|attr, VA */
+	cmp	r1, #0
+	bne	2b	
+#endif
+
+	mcr	p15, 0, r0, c2, c0, 0	/* Set TTB */
+	mcr	p15, 0, r0, c8, c7, 0	/* Flush TLB */
+
+	/* Set the Domain Access register.  Very important! */
+        mov     r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
+	mcr	p15, 0, r0, c3, c0, 0
+
+	/* Enable MMU */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #CPU_CONTROL_MMU_ENABLE
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT(r0)
+
+	/* Jump to kernel code in TRUE VA */
+	adr	r0, Lstart
+	ldr	pc, [r0]
+
+Lstart:
+	.word	start
+
+#define MMU_INIT(va,pa,n_sec,attr) \
+	.word	n_sec					    ; \
+	.word	4*((va)>>L1_S_SHIFT)			    ; \
+	.word	(pa)|(attr)				    ;
+	
+#ifdef BUILD_STARTUP_PAGETABLE
+#ifndef STARTUP_PAGETABLE_ADDR
+#define STARTUP_PAGETABLE_ADDR 0x82000000
+#endif
+Lstartup_pagetable:	.word	STARTUP_PAGETABLE_ADDR
+mmu_init_table:	
+	/* fill all table VA==PA */
+	MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
+	/* map SDRAM VA==PA, WT cacheable */
+	MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
+#endif
+mmu_init_table2:	
+	/* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */
+	MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
+
+	.word 0	/* end of table */
diff --git a/sys/arch/beagle/compile/.cvsignore b/sys/arch/beagle/compile/.cvsignore
new file mode 100644
index 00000000000..b72af3039e6
--- /dev/null
+++ b/sys/arch/beagle/compile/.cvsignore
@@ -0,0 +1,2 @@
+GENERIC
+RAMDISK
diff --git a/sys/arch/beagle/conf/Makefile.beagle b/sys/arch/beagle/conf/Makefile.beagle
new file mode 100644
index 00000000000..4fcd951099f
--- /dev/null
+++ b/sys/arch/beagle/conf/Makefile.beagle
@@ -0,0 +1,217 @@
+#	$OpenBSD: Makefile.beagle,v 1.1 2009/05/08 03:13:26 drahn Exp $
+
+# Makefile for OpenBSD
+#
+# This makefile is constructed from a machine description:
+#	config machineid
+# Most changes should be made in the machine description
+#	/sys/arch/beagle/conf/``machineid''
+# after which you should do
+#	config machineid
+# Machine generic makefile changes should be made in
+#	/sys/arch/beagle/conf/Makefile.beagle
+# after which config should be rerun for all machines of that type.
+#
+# N.B.: NO DEPENDENCIES ON FOLLOWING FLAGS ARE VISIBLE TO MAKEFILE
+#	IF YOU CHANGE THE DEFINITION OF ANY OF THESE RECOMPILE EVERYTHING
+#
+# -DTRACE	compile in kernel tracing hooks
+# -DQUOTA	compile in file system quotas
+
+# DEBUG is set to -g if debugging.
+# PROF is set to -pg if profiling.
+
+.include <bsd.own.mk>
+
+MKDEP?=	mkdep
+SIZE?=	size
+STRIP?=	strip
+
+# source tree is located via $S relative to the compilation directory
+.ifndef S
+S!=	cd ../../../..; pwd
+.endif
+THISARM=	$S/arch/${BOARDTYPE}
+ARM=	$S/arch/arm
+
+INCLUDES=	-nostdinc -I. -I$S/arch -I$S
+CPPFLAGS=	${INCLUDES} ${IDENT} -D_KERNEL -D__${BOARDTYPE}__
+CDIAGFLAGS=	-Werror -Wall -Wstrict-prototypes -Wmissing-prototypes \
+		-Wno-uninitialized -Wno-format -Wno-main
+
+CMACHFLAGS= -ffreestanding
+#CMACHFLAGS=	-march=armv4 -mtune=strongarm -ffreestanding
+.if ${IDENT:M-DNO_PROPOLICE}
+CMACHFLAGS+=	-fno-stack-protector
+.endif
+CMACHFLAGS+=	-msoft-float -fno-builtin-printf -fno-builtin-log
+
+COPTS?=		-O2
+CFLAGS=		${DEBUG} ${CDIAGFLAGS} ${CMACHFLAGS} ${COPTS} ${PIPE}
+AFLAGS=		-x assembler-with-cpp -D_LOCORE ${CMACHFLAGS} 
+#LINKFLAGS=	-Ttext 0xF0000020 -e start --warn-common
+#LINKFLAGS=	-T ${THISARM}/conf/kern.ldscript
+LINKFLAGS=	-T ldscript
+LINKFLAGS+=	--warn-common
+STRIPFLAGS=	-g -X -x
+
+HOSTCC= ${CC}
+HOSTED_CPPFLAGS=${CPPFLAGS:S/^-nostdinc$//}
+HOSTED_CFLAGS=	${CFLAGS}
+
+# compile rules: rules are named ${TYPE}_${SUFFIX}${CONFIG_DEP}
+# where TYPE is NORMAL, DRIVER, or PROFILE; SUFFIX is the file suffix,
+# capitalized (e.g. C for a .c file), and CONFIG_DEP is _C if the file
+# is marked as config-dependent.
+
+NORMAL_C_NOP=	${CC} ${CFLAGS} ${CPPFLAGS} -c $<
+NORMAL_C=	${CC} ${CFLAGS} ${CPPFLAGS} ${PROF} -c $<
+NORMAL_C_C=	${CC} ${CFLAGS} ${CPPFLAGS} ${PROF} ${PARAM} -c $<
+
+DRIVER_C=	${CC} ${CFLAGS} ${CPPFLAGS} ${PROF} -c $<
+DRIVER_C_C=	${CC} ${CFLAGS} ${CPPFLAGS} ${PROF} ${PARAM} -c $<
+
+NORMAL_S=	${CC} ${AFLAGS} ${CPPFLAGS} -c $<
+NORMAL_S_C=	${CC} ${AFLAGS} ${CPPFLAGS} ${PARAM} -c $<
+
+HOSTED_C=	${HOSTCC} ${HOSTED_CFLAGS} ${HOSTED_CPPFLAGS} -c $<
+
+%OBJS
+
+%CFILES
+
+%SFILES
+
+# load lines for config "xxx" will be emitted as:
+# xxx: ${SYSTEM_DEP} swapxxx.o
+#	${SYSTEM_LD_HEAD}
+#	${SYSTEM_LD} swapxxx.o
+#	${SYSTEM_LD_TAIL}
+SYSTEM_OBJ=	${BOARDTYPE}_start.o locore.o param.o ioconf.o ${OBJS}
+SYSTEM_DEP=	Makefile ${SYSTEM_OBJ}
+SYSTEM_LD_HEAD=	rm -f $@
+SYSTEM_LD_HEAD+=; \
+    ( cat ${ARM}/conf/ldscript.head ;\
+    cat ${ARM}/conf/ldscript.tail ) |  \
+	sed -e 's/@KERNEL_BASE_PHYS@/${KERNEL_BASE_PHYS}/' \
+	-e 's/@KERNEL_BASE_VIRT@/${KERNEL_BASE_VIRT}/' \
+     > ldscript
+
+SYSTEM_LD=	@echo ${LD} ${LINKFLAGS} -o $@ '$${SYSTEM_OBJ}' vers.o; \
+		${LD} ${LINKFLAGS} -o $@ ${SYSTEM_OBJ} vers.o
+SYSTEM_LD_TAIL=	@${SIZE} $@; chmod 755 $@
+
+DEBUG?=
+.if ${DEBUG} == "-g"
+LINKFLAGS+=	-X
+SYSTEM_LD_TAIL+=; \
+		echo cp $@ $@.gdb; rm -f $@.gdb; cp $@ $@.gdb; \
+		echo ${STRIP} ${STRIPFLAGS} $@; ${STRIP} ${STRIPFLAGS} $@
+.else
+LINKFLAGS+=	-x
+.endif
+
+%LOAD
+
+assym.h: $S/kern/genassym.sh ${ARM}/arm/genassym.cf Makefile
+	cat ${ARM}/arm/genassym.cf | \
+	    sh $S/kern/genassym.sh ${CC} ${CFLAGS} \
+	    ${CPPFLAGS} ${PARAM} > assym.h.tmp && \
+	    mv -f assym.h.tmp assym.h
+
+param.c: $S/conf/param.c
+	rm -f param.c
+	cp $S/conf/param.c .
+
+param.o: param.c Makefile
+	${NORMAL_C_C}
+
+mcount.o: $S/lib/libkern/mcount.c Makefile
+	${NORMAL_C_NOP}
+
+ioconf.o: ioconf.c
+	${NORMAL_C}
+
+newvers: ${SYSTEM_DEP} ${SYSTEM_SWAP_DEP}
+	sh $S/conf/newvers.sh
+	${CC} ${CFLAGS} ${CPPFLAGS} ${PROF} -c vers.c
+
+
+clean::
+	rm -f eddep *bsd bsd.gdb tags *.[io] [a-z]*.s \
+	    [Ee]rrs linterrs makelinks assym.h
+
+lint:
+	@lint -hbxncez -Dvolatile= ${CPPFLAGS} ${PARAM} -UKGDB \
+	    ${CFILES} ioconf.c param.c | \
+	    grep -v 'static function .* unused'
+
+tags:
+	@echo "see $S/kern/Makefile for tags"
+
+links:
+	egrep '#if' ${CFILES} | sed -f $S/conf/defines | \
+	  sed -e 's/:.*//' -e 's/\.c/.o/' | sort -u > dontlink
+	echo ${CFILES} | tr -s ' ' '\12' | sed 's/\.c/.o/' | \
+	  sort -u | comm -23 - dontlink | \
+	  sed 's,.*/\(.*.o\),rm -f \1; ln -s ../GENERIC/\1 \1,' > makelinks
+	sh makelinks && rm -f dontlink makelinks
+
+SRCS=	${ARM}/arm/locore.S \
+	param.c ioconf.c ${CFILES} ${SFILES}
+depend:: .depend
+.depend: ${SRCS} assym.h param.c ${APMINC}
+	${MKDEP} ${AFLAGS} ${CPPFLAGS} ${ARM}/arm/locore.S
+	${MKDEP} -a ${CFLAGS} ${CPPFLAGS} param.c ioconf.c ${CFILES}
+.if ${SFILES} != ""
+	${MKDEP} -a ${AFLAGS} ${CPPFLAGS} ${SFILES}
+.endif
+	cat ${ARM}/arm/genassym.cf | \
+	    sh $S/kern/genassym.sh ${MKDEP} -f assym.dep ${CFLAGS} \
+	    ${CPPFLAGS} 
+	@sed -e 's/.*\.o:.* /assym.h: /' < assym.dep >> .depend
+	@rm -f assym.dep
+
+
+# depend on root or device configuration
+autoconf.o conf.o: Makefile
+
+bsd.rd: bsd
+		cp bsd bsd.rd
+		$S/../distrib/${BOARDTYPE}/ramdisk/rdsetroot < $S/../distrib/${BOARDTYPE}/ramdisk/mr.fs bsd.rd
+
+bsd.img: bsd.rd
+	${OBJCOPY} -O binary bsd.rd bsd.img
+ 
+# depend on network or filesystem configuration 
+uipc_domain.o uipc_proto.o vfs_conf.o: Makefile 
+if.o if_tun.o if_loop.o if_ethersubr.o: Makefile
+if_arp.o if_ether.o: Makefile
+ip_input.o ip_output.o in_pcb.o in_proto.o: Makefile
+tcp_subr.o tcp_timer.o tcp_output.o: Makefile
+
+# depend on maxusers
+machdep.o: Makefile
+
+# depend on CPU configuration 
+locore.o machdep.o: Makefile
+
+${BOARDTYPE}_start.o: ${THISARM}/${BOARDTYPE}/${BOARDTYPE}_start.S assym.h
+	${NORMAL_S}
+
+locore.o: ${ARM}/arm/locore.S assym.h
+	${NORMAL_S}
+
+# The install target can be redefined by putting a
+# install-kernel-${MACHINE_NAME} target into /etc/mk.conf
+MACHINE_NAME!=  uname -n
+install: install-kernel-${MACHINE_NAME}
+.if !target(install-kernel-${MACHINE_NAME}})
+install-kernel-${MACHINE_NAME}:
+	rm -f /obsd
+	ln /bsd /obsd
+	cp bsd /nbsd
+	mv /nbsd /bsd
+.endif
+
+%RULES
diff --git a/sys/arch/beagle/conf/RAMDISK b/sys/arch/beagle/conf/RAMDISK
new file mode 100644
index 00000000000..f6a5242a2a3
--- /dev/null
+++ b/sys/arch/beagle/conf/RAMDISK
@@ -0,0 +1,181 @@
+# $OpenBSD: RAMDISK,v 1.1 2009/05/08 03:13:26 drahn Exp $
+#
+# GENERIC machine description file
+#
+# This machine description file is used to generate the default OpenBSD
+# kernel.  The generic kernel does not include all options, subsystems
+# and device drivers, but should be useful for most applications.
+#
+# The machine description file can be customised for your specific
+# machine to reduce the kernel size and improve its performance.
+#
+# For further information on compiling OpenBSD kernels, see the config(8)
+# man page.
+#
+# For further information on hardware support for this architecture, see
+# the intro(4) man page.  For further information about kernel options
+# for this architecture, see the options(4) man page.  For an explanation
+# of each device driver in this file see the section 4 man page for the
+# device.
+
+machine	beagle	arm
+
+options	TIMEZONE=0	# time zone to adjust RTC time by
+options	DST=0		# daylight saving time used by RTC
+options	FFS		# UFS
+#options	CD9660		# ISO 9660 + Rock Ridge file system
+options	MSDOSFS		# MS-DOS file system
+options	INET		# IP + ICMP + TCP + UDP
+options	INET6		# IPv6 (needs INET)
+options	DDB		# kernel debugger
+options	FIFO		# FIFOs; RECOMMENDED
+#options	NFSCLIENT	# NFS 
+
+options		ARM11_AVIC_INTR
+
+options		CACHE_CLEAN_BLOCK_INTR
+
+makeoptions	KERNEL_BASE_PHYS="0x80300000"
+makeoptions	KERNEL_BASE_VIRT="0xc0300000"
+makeoptions	BOARDTYPE="beagle"
+options	BUILD_STARTUP_PAGETABLE
+options	STARTUP_PAGETABLE_ADDR=0x80200000
+options	SDRAM_START="0x80000000"
+
+options		APERTURE
+
+# estimated number of users
+
+maxusers	32
+
+# CPU options
+options	CPU_ARMv7	# Support the ARM11
+makeoptions	CPUFLAGS="-mcpu=armv5"
+
+#option WSDISPLAY_COMPAT_USL		# VT handling
+#option WSDISPLAY_COMPAT_RAWKBD		# can get raw scancodes
+option WSDISPLAY_DEFAULTSCREENS=1
+#option WSDISPLAY_COMPAT_PCVT		# emulate some ioctls
+
+config		bsd	root on rd0a swap on rd0b
+
+# The main bus device
+mainbus0	at root
+cpu0		at mainbus?
+ahb0		at mainbus?
+
+prcm0		at ahb? addr 0x48004800	# power/clock controller
+intc0		at ahb? addr 0x480fe000	# interrupt controller
+gptimer0	at ahb? addr 0x49032000	intr 38 # timer GPTIMER2
+gptimer1	at ahb? addr 0x48318000	intr 37 # timer GPTIMER1
+
+#sm0		at ahb?	addr 0x0C000300 intr 188 #ethernet
+
+#omgpio0		at ahb? addr 0x48018000 intr 29
+#omgpio1		at ahb? addr 0x4801a000 intr 30
+#omgpio2		at ahb? addr 0x4801c000 intr 31
+#omgpio3		at ahb? addr 0x4801e000 intr 32
+
+omdog0		at ahb? addr 0x48314000 		# watchdog timer
+
+#omkbd0		at ahb? addr 0x48022000 		
+#wskbd*		at omkbd? mux 1
+
+#ohci0		at ahb? addr 0x4805E000 size 0x400 intr 78	# ohci (shim)
+
+#mcspi0		at ahb? addr 0x48098000 intr 65
+#mcspi1		at ahb? addr 0x4809A000 intr 66
+
+#atlas0		at ahb? intr 85	# really a spi device, not ahb
+#wskbd*		at atlas? mux 1 
+
+#usbotg0	at ahb? addr 0x4c000000 size 0x70 intr 3
+#usb*		at ohci?
+
+# ## USB bus support
+# usb*		at ohci?	flags 0x1
+# uhub*		at usb?
+# uhub*		at uhub?
+# 
+# uhub*		at usb?			# USB Hubs
+# uhub*		at uhub?		# USB Hubs
+# umodem*		at uhub?		# USB Modems/Serial
+# ucom*		at umodem?
+# uvisor*		at uhub?		# Handspring Visor
+# ucom*		at uvisor?
+# uvscom*		at uhub?		# SUNTAC Slipper U VS-10U serial
+# ucom*		at uvscom?
+# ubsa*		at uhub?		# Belkin serial adapter
+# ucom*		at ubsa?
+# uftdi*		at uhub?		# FTDI FT8U100AX serial adapter
+# ucom*		at uftdi?
+# uplcom* 	at uhub?		# I/O DATA USB-RSAQ2 serial adapter
+# ucom*		at uplcom?
+# umct*		at uhub?		# MCT USB-RS232 serial adapter
+# ucom*		at umct?
+# uaudio* 	at uhub?		# USB Audio
+# audio*		at uaudio?
+# umidi*		at uhub?		# USB MIDI
+# midi*		at umidi?
+# ulpt*		at uhub?		# USB Printers
+# umass*		at uhub?		# USB Mass Storage devices
+# scsibus*	at umass?
+# uhidev*		at uhub?		# Human Interface Devices
+# ums*		at uhidev?		# USB mouse
+# wsmouse*	at ums? mux 0
+# ukbd*		at uhidev?		# USB keyboard
+# wskbd*		at ukbd? mux 1
+# uhid*		at uhidev?		# USB generic HID support
+# aue*		at uhub?		# ADMtek AN986 Pegasus Ethernet
+# atu*		at uhub?		# Atmel AT76c50x based 802.11b
+# axe*		at uhub?		# ASIX Electronics AX88172 USB Ethernet
+# cue*		at uhub?		# CATC USB-EL1201A based Ethernet
+# kue*		at uhub?		# Kawasaki KL5KUSB101B based Ethernet
+# cdce*		at uhub?		# CDC Ethernet
+# upl*		at uhub?		# Prolific PL2301/PL2302 host-to-host `network'
+# udav*		at uhub?		# Davicom DM9601 based Ethernet
+# url*		at uhub?		# Realtek RTL8150L based adapters
+# wi*		at uhub?		# WaveLAN IEEE 802.11DS
+# urio*		at uhub?		# Diamond Multimedia Rio 500
+# uscanner*	at uhub?		# USB Scanners
+# usscanner*	at uhub?		# USB SCSI scanners, e.g., HP5300
+# scsibus*	at usscanner?
+# #uyap*		at uhub?		# Y@P firmware loader
+# udsbr*		at uhub?		# D-Link DSB-R100 radio
+# radio*		at udsbr?		# USB radio
+# #ubt*		at uhub?		# USB Bluetooth
+# ugen*		at uhub?		# USB Generic driver
+# 
+# ukphy*	at mii?				# "unknown" PHYs
+# 
+# sd*		at scsibus?
+# st*		at scsibus?
+# cd*		at scsibus?
+# ch*		at scsibus?
+# ss*		at scsibus?
+# uk*		at scsibus?
+
+
+# onboard uarts
+com0	at ahb?	addr	0x49020000	size 0x400 intr 74 # UART3
+
+#com1	at ahb?	addr	0xXXXXXX00	size 0x400 intr 73
+#com2	at ahb?	addr	0xXXXXXX00	size 0x400 intr 74
+
+# LCD
+#omdisplay0	at ahb? addr 0x48050000 intr 25 # LCD DISPLAY
+#wsdisplay*	at omdisplay? console ?
+
+# APM emulation
+#apm0		at pxaip?
+
+# Pseudo-Devices
+#pseudo-device	wsmux		2	# mouse & keyboard multiplexor
+#pseudo-device	crypto		1
+pseudo-device	loop		1	# network loopback
+pseudo-device   bpfilter        1       # packet filter
+pseudo-device   rd              1       # ram disk
+
+# RAMDISK stuff
+options	MINIROOTSIZE=5120
+options	RAMDISK_HOOKS
diff --git a/sys/arch/beagle/conf/files.beagle b/sys/arch/beagle/conf/files.beagle
new file mode 100644
index 00000000000..40feb861c51
--- /dev/null
+++ b/sys/arch/beagle/conf/files.beagle
@@ -0,0 +1,126 @@
+#	$OpenBSD: files.beagle,v 1.1 2009/05/08 03:13:26 drahn Exp $
+#
+# First try for arm-specific configuration info
+#
+
+maxpartitions	16
+maxusers	2 8 64
+
+major	{wd = 16}
+major	{sd = 24}
+major	{cd = 26}
+major	{rd = 18}
+
+file	arch/arm/arm/conf.c
+
+file	arch/beagle/beagle/beagle_machdep.c
+
+# ARM11
+define  ahb {[addr=-1], [size=0], [intr=-1]}
+device ahb
+attach ahb at mainbus
+file	arch/beagle/beagle/ahb.c	ahb
+file	arch/arm/armv7/armv7_space.c	ahb
+file	arch/arm/armv7/armv7_a4x_space.c	ahb	# XXX
+file	arch/arm/armv7/armv7_a4x_io.S		ahb	# XXX
+file	arch/arm/armv7/armv7_mutex.c
+
+# note that the order of the devices in _this_ file
+# affects the order that the devices will configure.
+
+device prcm
+attach prcm at ahb
+file	arch/beagle/dev/prcm.c			prcm
+
+device omgpio
+attach omgpio at ahb
+file	arch/beagle/dev/omgpio.c			omgpio needs-count
+
+device intc
+attach intc at ahb
+file	arch/beagle/dev/intc.c			intc
+
+device gptimer
+attach gptimer at ahb
+file	arch/beagle/dev/gptimer.c			gptimer
+
+device omdog
+attach omdog at ahb
+file	arch/beagle/dev/omdog.c			omdog
+
+attach sm at ahb with sm_ahb
+file	arch/beagle/dev/if_sm_ahb.c			sm_ahb
+
+attach ohci at ahb with omohci
+file	arch/beagle/dev/omohci.c			omohci
+
+# NS16550 compatible serial ports
+attach	com at ahb with com_ahb
+file	arch/beagle/dev/omap_com.c		com_ahb
+
+device omkbd: wskbddev
+attach omkbd at ahb
+file	arch/beagle/dev/omkbd.c		omkbd
+
+# LCD frame buffer
+device omdisplay: wsemuldisplaydev, rasops16
+attach omdisplay at ahb
+file arch/beagle/dev/omdisplay.c		omdisplay
+
+
+#
+# Machine-independent SCSI drivers
+#
+include "../../../scsi/files.scsi"
+include "../../../dev/atapiscsi/files.atapiscsi"
+
+# CPU support and integrated peripherals
+file	arch/arm/arm/irq_dispatch.S
+file	arch/arm/arm/softintr.c                         
+
+# MCSPI - spi connection to atlas 
+device mcspi 
+attach mcspi at ahb
+file	arch/beagle/dev/mcspi.c		mcspi
+
+# ATLAS (spi) driver
+device atlas: wskbddev
+attach atlas at ahb				# create a spi bus for this?
+file arch/beagle/dev/atlas.c			atlas
+
+# pseudo-Audio Device Driver
+device oaudio: audio
+attach oaudio at ahb				# configure after Atlas Driver
+file arch/beagle/dev/beagle_audio.c			oaudio
+
+#
+# Machine-independent ATA drivers
+#
+include "dev/ata/files.ata"
+
+# Generic MD files
+file	arch/beagle/beagle/autoconf.c
+
+file	arch/arm/arm/disksubr.c			disk
+
+
+# ARM FPE
+file	arch/arm/fpe-arm/armfpe_glue.S		armfpe
+file	arch/arm/fpe-arm/armfpe_init.c		armfpe
+file	arch/arm/fpe-arm/armfpe.s		armfpe
+
+
+# Machine-independent I2O drivers.
+include "dev/i2o/files.i2o"
+
+# Include WSCONS stuff
+include "dev/wscons/files.wscons"
+include "dev/rasops/files.rasops"
+include "dev/wsfont/files.wsfont"
+include "dev/pckbc/files.pckbc"
+
+# Include USB stuff
+include "dev/usb/files.usb"
+
+# Media Independent Interface (mii)
+include "dev/mii/files.mii"
diff --git a/sys/arch/beagle/dev/gptimer.c b/sys/arch/beagle/dev/gptimer.c
new file mode 100644
index 00000000000..b5485293c05
--- /dev/null
+++ b/sys/arch/beagle/dev/gptimer.c
@@ -0,0 +1,513 @@
+/* $OpenBSD: gptimer.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ *	WARNING - this timer initializion has not been checked
+ *	to see if it will do _ANYTHING_ sane if the omap enters
+ *	low power mode.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/evcount.h>
+#include <sys/device.h>
+#include <sys/timetc.h>
+#include <dev/clock_subr.h>
+#include <beagle/dev/prcmvar.h>
+#include <machine/bus.h>
+#include <arch/beagle/beagle/ahb.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <arm/cpufunc.h>
+
+/* registers */
+#define	GP_TIDR		0x000
+#define		GP_TIDR_REV	0xff
+#define GP_TIOCP_CFG	0x010
+#define 	GP_TIOCP_CFG_CLKA	0x000000300
+#define 	GP_TIOCP_CFG_EMUFREE	0x000000020
+#define 	GP_TIOCP_CFG_IDLEMODE	0x000000018
+#define 	GP_TIOCP_CFG_ENAPWAKEUP	0x000000004
+#define 	GP_TIOCP_CFG_SOFTRESET	0x000000002
+#define 	GP_TIOCP_CFG_AUTOIDLE	0x000000001
+#define	GP_TISTAT	0x014
+#define 	GP_TISTAT_RESETDONE	0x000000001
+#define	GP_TISR		0x018
+#define		GP_TISTAT_TCAR		0x00000004
+#define		GP_TISTAT_OVF		0x00000002
+#define		GP_TISTAT_MATCH		0x00000001
+#define GP_TIER		0x1c
+#define		GP_TIER_TCAR_EN		0x4
+#define		GP_TIER_OVF_EN		0x2
+#define		GP_TIER_MAT_EN		0x1
+#define	GP_TWER		0x020
+#define		GP_TWER_TCAR_EN		0x00000004
+#define		GP_TWER_OVF_EN		0x00000002
+#define		GP_TWER_MAT_EN		0x00000001
+#define	GP_TCLR		0x024
+#define		GP_TCLR_GPO		(1<<14)
+#define		GP_TCLR_CAPT		(1<<13)
+#define		GP_TCLR_PT		(1<<12)
+#define		GP_TCLR_TRG		(3<<10)
+#define		GP_TCLR_TRG_O		(1<<10)
+#define		GP_TCLR_TRG_OM		(2<<10)
+#define		GP_TCLR_TCM		(3<<8)
+#define		GP_TCLR_TCM_RISE	(1<<8)
+#define		GP_TCLR_TCM_FALL	(2<<8)
+#define		GP_TCLR_TCM_BOTH	(3<<8)
+#define		GP_TCLR_SCPWM		(1<<7)
+#define		GP_TCLR_CE		(1<<6)
+#define		GP_TCLR_PRE		(1<<5)
+#define		GP_TCLR_PTV		(7<<2)
+#define		GP_TCLR_AR		(1<<1)
+#define		GP_TCLR_ST		(1<<0)
+#define	GP_TCRR		0x028				/* counter */
+#define	GP_TLDR		0x02c				/* reload */
+#define	GP_TTGR		0x030
+#define	GP_TWPS		0x034
+#define		GP_TWPS_TCLR	0x01
+#define		GP_TWPS_TCRR	0x02
+#define		GP_TWPS_TLDR	0x04
+#define		GP_TWPS_TTGR	0x08
+#define		GP_TWPS_TMAR	0x10
+#define		GP_TWPS_ALL	0x1f
+#define	GP_TMAR		0x038
+#define	GP_TCAR		0x03C
+#define	GP_TSICR	0x040
+#define		GP_TSICR_POSTED		0x00000002
+#define		GP_TSICR_SFT		0x00000001
+#define	GP_TCAR2	0x044
+#define	GP_SIZE	0x100
+
+
+#define TIMER_FREQUENCY			32768	/* 32kHz is used, selectable */
+
+static struct evcount clk_count;
+static struct evcount stat_count;
+#define GPT1_IRQ  38
+#define GPTIMER0_IRQ	38
+
+//static int clk_irq = GPT1_IRQ; /* XXX 37 */
+
+int gptimer_match(struct device *parent, void *v, void *aux);
+void gptimer_attach(struct device *parent, struct device *self, void *args);
+int gptimer_intr(void *frame);
+void gptimer_delay(int reg);
+
+bus_space_tag_t gptimer_iot;
+bus_space_handle_t gptimer_ioh0,  gptimer_ioh1; 
+int gptimer_irq = 0;
+
+volatile u_int32_t nexttickevent;
+volatile u_int32_t nextstatevent;
+u_int32_t	ticks_per_second;
+u_int32_t	ticks_per_intr;
+u_int32_t	ticks_err_cnt;
+u_int32_t	ticks_err_sum;
+u_int32_t	statvar, statmin;
+
+struct cfattach	gptimer_ca = {
+	sizeof (struct device), gptimer_match, gptimer_attach
+};
+
+struct cfdriver gptimer_cd = {
+	NULL, "gptimer", DV_DULL
+};
+
+int
+gptimer_match(struct device *parent, void *v, void *aux)
+{
+	return (1);
+}
+
+void
+gptimer_attach(struct device *parent, struct device *self, void *args)
+{
+        struct ahb_attach_args *aa = args;
+	bus_space_handle_t ioh; 
+	u_int32_t rev;
+
+	gptimer_iot = aa->aa_iot;
+	if (bus_space_map(gptimer_iot, aa->aa_addr, GP_SIZE, 0, &ioh))
+		panic("gptimer_attach: bus_space_map failed!");
+
+	rev = bus_space_read_4(gptimer_iot, ioh, GP_TIDR);
+
+	printf(" rev %d.%d\n", rev >> 4 & 0xf, rev & 0xf);
+	if (self->dv_unit == 0) {
+		gptimer_ioh0 = ioh;
+		gptimer_irq = aa->aa_intr;
+		bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TCLR, 0);
+	} else if (self->dv_unit == 1) {
+		/* start timer because it is used in delay */
+		gptimer_ioh1 = ioh;
+		bus_space_write_4(gptimer_iot, gptimer_ioh1, GP_TCRR, 0);
+		gptimer_delay(GP_TWPS_ALL);
+		bus_space_write_4(gptimer_iot, gptimer_ioh1, GP_TLDR, 0);
+		gptimer_delay(GP_TWPS_ALL);
+		bus_space_write_4(gptimer_iot, gptimer_ioh1, GP_TCLR,
+		    GP_TCLR_AR | GP_TCLR_ST);
+		gptimer_delay(GP_TWPS_ALL);
+
+	}
+	else 
+		panic("attaching too many gptimers at %x\n", aa->aa_addr);
+}
+
+/* 
+ * See comment in arm/xscale/i80321_clock.c
+ *
+ * counter is count up, but with autoreload timers it is not possible
+ * to detect how many  interrupts passed while interrupts were blocked.
+ * also it is not possible to atomically add to the register
+ * get get it to precisely fire at a non-fixed interval.
+ *
+ * To work around this two timers are used, GPT1 is used as a reference
+ * clock without reload , however we just ignore the interrupt it
+ * would (may?) generate.
+ *
+ * Internally this keeps track of when the next timer should fire
+ * and based on that time and the current value of the reference
+ * clock a number is written into the timer count register to schedule
+ * the next event.
+ */
+
+int
+gptimer_intr(void *frame)
+{
+	u_int32_t now, r;
+	u_int32_t nextevent, duration;
+
+	printf("T\n");
+	/* clear interrupt */
+	now = bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR);
+
+	while ((int32_t) (nexttickevent - now) < 0) {
+		nexttickevent += ticks_per_intr;
+		ticks_err_sum += ticks_err_cnt;
+#if 0
+		if (ticks_err_sum  > hz) {
+			u_int32_t match_error;
+			match_error = ticks_err_sum / hz
+			ticks_err_sum -= (match_error * hz);
+		}
+#else
+		/* looping a few times is faster than divide */
+		while (ticks_err_sum  > hz) {
+			nexttickevent += 1;
+			ticks_err_sum -= hz;
+		}
+#endif
+		clk_count.ec_count++;
+		hardclock(frame);
+	}
+	while ((int32_t) (nextstatevent - now) < 0) {
+		do {
+			r = random() & (statvar -1);
+		} while (r == 0); /* random == 0 not allowed */
+		nextstatevent += statmin + r;
+		/* XXX - correct nextstatevent? */
+		stat_count.ec_count++;
+		statclock(frame);
+	}
+        if ((now - nexttickevent) < (now - nextstatevent))
+                nextevent = nexttickevent;
+        else
+                nextevent = nextstatevent;
+
+/* XXX */
+	duration = nextevent -
+	    bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR);
+#if 0
+	printf("duration 0x%x %x %x\n", nextevent -
+	    bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR),
+	    bus_space_read_4(gptimer_iot, gptimer_ioh0, GP_TCRR),
+	    bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR));
+#endif
+
+
+        if (duration <= 0)
+                duration = 1; /* trigger immediately. */
+
+        if (duration > ticks_per_intr) {
+                /*
+                 * If interrupts are blocked too long, like during
+                 * the root prompt or ddb, the timer can roll over,
+                 * this will allow the system to continue to run
+                 * even if time is lost.
+                 */
+                duration = ticks_per_intr;
+                nexttickevent = now;
+                nextstatevent = now;
+        }
+
+	gptimer_delay(GP_TWPS_ALL);
+	bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TISR,
+		bus_space_read_4(gptimer_iot, gptimer_ioh0, GP_TISR));
+	gptimer_delay(GP_TWPS_ALL);
+        bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TCRR, -duration);
+ 
+	return 1;
+}
+
+/*
+ * would be interesting to play with trigger mode while having one timer
+ * in 32KHz mode, and the other timer running in sysclk mode and use
+ * the high resolution speeds (matters more for delay than tick timer
+ */
+
+void
+cpu_initclocks()
+{
+//	u_int32_t now;
+	stathz = 128;
+	profhz = 1024;
+
+	ticks_per_second = TIMER_FREQUENCY;
+
+	setstatclockrate(stathz);
+
+	ticks_per_intr = ticks_per_second / hz;
+	ticks_err_cnt = ticks_per_second % hz;
+	ticks_err_sum = 0;; 
+
+	prcm_setclock(1, PRCM_CLK_SPEED_32);
+	prcm_setclock(2, PRCM_CLK_SPEED_32);
+	/* establish interrupts */
+	intc_intr_establish(gptimer_irq, IPL_CLOCK, gptimer_intr,
+	    NULL, "tick");
+
+	/* setup timer 0 (hardware timer 2) */
+	/* reset? - XXX */
+
+        bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TLDR, 0);
+
+	nexttickevent = nextstatevent = bus_space_read_4(gptimer_iot,
+	    gptimer_ioh1, GP_TCRR) + ticks_per_intr;
+
+	gptimer_delay(GP_TWPS_ALL);
+	bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TIER, GP_TIER_OVF_EN);
+	gptimer_delay(GP_TWPS_ALL);
+	bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TWER, GP_TWER_OVF_EN);
+	gptimer_delay(GP_TWPS_ALL);
+	bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TCLR,
+	    GP_TCLR_AR | GP_TCLR_ST);
+	gptimer_delay(GP_TWPS_ALL);
+	bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TISR,
+		bus_space_read_4(gptimer_iot, gptimer_ioh0, GP_TISR));
+	gptimer_delay(GP_TWPS_ALL);
+	bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TCRR, -ticks_per_intr);
+	gptimer_delay(GP_TWPS_ALL);
+}
+
+void
+gptimer_delay(int reg)
+{
+	while (bus_space_read_4(gptimer_iot, gptimer_ioh0, GP_TWPS) & reg)
+		;
+}
+
+#if 0
+void
+microtime(struct timeval *tvp)
+{
+	int s;
+	int deltacnt;
+	u_int32_t counter, expected;
+	s = splhigh();
+
+	if (1) {	/* not inited */
+		tvp->tv_sec = 0;
+		tvp->tv_usec = 0;
+		return;
+	}
+	s = splhigh();
+	counter = bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR);
+	expected = nexttickevent;
+
+	*tvp = time;
+	splx(s);
+
+	deltacnt = counter - expected + ticks_per_intr;
+
+#if 1
+	/* low frequency timer algorithm */
+	tvp->tv_usec += deltacnt * 1000000ULL / TIMER_FREQUENCY;
+#else
+	/* high frequency timer algorithm - XXX */
+	tvp->tv_usec += deltacnt / (TIMER_FREQUENCY / 1000000ULL);
+#endif
+
+	while (tvp->tv_usec >= 1000000) {
+		tvp->tv_sec++;
+		tvp->tv_usec -= 1000000;
+	}
+
+}
+#endif
+
+void
+delay(u_int usecs)
+{
+	u_int32_t clock, oclock, delta, delaycnt;
+	volatile int j;
+	int csec, usec;
+
+	if (usecs > (0x80000000 / (TIMER_FREQUENCY))) {
+		csec = usecs / 10000;
+		usec = usecs % 10000;
+
+		delaycnt = (TIMER_FREQUENCY / 100) * csec +
+		    (TIMER_FREQUENCY / 100) * usec / 10000;
+	} else {
+		delaycnt = TIMER_FREQUENCY * usecs / 1000000;
+	}
+	if (delaycnt <= 1)
+		for (j = 100; j > 0; j--)
+			;
+
+	if (gptimer_ioh1 == NULL) {
+		/* BAH */
+		for (; usecs > 0; usecs--)
+			for (j = 100; j > 0; j--)
+				;
+		return;
+	}
+	oclock = bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR);
+	while (1) {
+		for (j = 100; j > 0; j--)
+			;
+		clock = bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR);
+		delta = clock - oclock;
+		if (delta > delaycnt)
+			break;
+	}
+	
+}
+
+void
+setstatclockrate(int newhz)
+{
+	int minint, statint;
+	int s;
+	
+	s = splclock();
+
+	statint = ticks_per_second / newhz;
+	/* calculate largest 2^n which is smaller that just over half statint */
+	statvar = 0x40000000; /* really big power of two */
+	minint = statint / 2 + 100;
+	while (statvar > minint)
+		statvar >>= 1;
+
+	statmin = statint - (statvar >> 1);
+	
+	splx(s);
+
+	/*
+	 * XXX this allows the next stat timer to occur then it switches
+	 * to the new frequency. Rather than switching instantly.
+	 */
+}
+
+todr_chip_handle_t todr_handle;
+
+/*
+ * inittodr:
+ *
+ *      Initialize time from the time-of-day register.
+ */
+#define MINYEAR         2003    /* minimum plausible year */
+void
+inittodr(time_t base)
+{
+	time_t deltat;
+	struct timeval rtctime;
+	struct timespec ts;
+	int badbase;
+
+	if (base < (MINYEAR - 1970) * SECYR) {
+		printf("WARNING: preposterous time in file system\n");
+		/* read the system clock anyway */
+		base = (MINYEAR - 1970) * SECYR;
+		badbase = 1;
+	} else
+		badbase = 0;
+
+	if (todr_handle == NULL ||
+	    todr_gettime(todr_handle, &rtctime) != 0 ||
+	    rtctime.tv_sec == 0) {
+		/*
+		 * Believe the time in the file system for lack of
+		 * anything better, resetting the TODR.
+		 */
+		rtctime.tv_sec = base;
+		rtctime.tv_usec = 0;
+		if (todr_handle != NULL && !badbase) {
+			printf("WARNING: preposterous clock chip time\n");
+			resettodr();
+		}
+		goto bad;
+	} else {
+		ts.tv_sec = rtctime.tv_sec;
+		ts.tv_nsec = rtctime.tv_usec * 1000;
+		tc_setclock(&ts);
+	}
+
+	if (!badbase) {
+		/*
+		 * See if we gained/lost two or more days; if
+		 * so, assume something is amiss.
+		 */
+		deltat = rtctime.tv_sec - base;
+		if (deltat < 0)
+			deltat = -deltat;
+		if (deltat < 2 * SECDAY)
+			return;         /* all is well */
+		printf("WARNING: clock %s %ld days\n",
+		    rtctime.tv_sec < base ? "lost" : "gained",
+		    (long)deltat / SECDAY);
+	}
+ bad:
+	printf("WARNING: CHECK AND RESET THE DATE!\n");
+}
+
+
+/*
+ * resettodr:
+ *
+ *      Reset the time-of-day register with the current time.
+ */
+void
+resettodr(void)
+{
+	struct timeval rtctime;
+
+	if (rtctime.tv_sec == 0)
+		return;
+			
+	microtime(&rtctime);
+
+	if (todr_handle != NULL &&
+	   todr_settime(todr_handle, &rtctime) != 0)
+		printf("resettodr: failed to set time\n");
+}
+
diff --git a/sys/arch/beagle/dev/intc.c b/sys/arch/beagle/dev/intc.c
new file mode 100644
index 00000000000..71518f14b0f
--- /dev/null
+++ b/sys/arch/beagle/dev/intc.c
@@ -0,0 +1,501 @@
+/* $OpenBSD: intc.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+#include <sys/evcount.h>
+#include <machine/bus.h>
+#include <arch/beagle/beagle/ahb.h>
+
+/* registers */
+#define	INTC_REVISION		0x00	/* R */
+#define	INTC_SYSCONFIG		0x10	/* RW */
+#define		INTC_SYSCONFIG_AUTOIDLE		0x1
+#define		INTC_SYSCONFIG_SOFTRESET	0x2
+#define	INTC_SYSSTATUS		0x14	/* R */
+#define		INTC_SYSSYSTATUS_RESETDONE	0x1
+#define	INTC_SIR_IRQ		0x40	/* R */	
+#define	INTC_SIR_FIQ		0x44	/* R */
+#define	INTC_CONTROL		0x48	/* RW */
+#define		INTC_CONTROL_NEWIRQ	0x1
+#define		INTC_CONTROL_NEWFIQ	0x1
+#define		INTC_CONTROL_GLOBALMASK	0x1
+#define	INTC_PROTECTION		0x4c	/* RW */
+#define		INTC_PROTECTION_PROT 1	/* only privileged mode */
+#define	INTC_IDLE		0x50	/* RW */
+
+#define INTC_IRQ_TO_REG(i)	(((i) >> 5) & 0x3)
+#define INTC_IRQ_TO_REGi(i)	((i) & 0x1f)
+#define	INTC_ITRn(i)		0x80+(0x20*i)+0x00	/* R */
+#define	INTC_MIRn(i)		0x80+(0x20*i)+0x04	/* RW */
+#define	INTC_CLEARn(i)		0x80+(0x20*i)+0x08	/* RW */
+#define	INTC_SETn(i)		0x80+(0x20*i)+0x0c	/* RW */
+#define	INTC_ISR_SETn(i)	0x80+(0x20*i)+0x10	/* RW */
+#define	INTC_ISR_CLEARn(i)	0x80+(0x20*i)+0x14	/* RW */
+#define INTC_PENDING_IRQn(i)	0x80+(0x20*i)+0x18	/* R */
+#define INTC_PENDING_FIQn(i)	0x80+(0x20*i)+0x1c	/* R */
+
+#define	INTC_ITR0		0x80	/* R */
+#define	INTC_MIR0		0x84	/* RW */
+#define	INTC_CLEAR0		0x88	/* RW */
+#define	INTC_SET0		0x8c	/* RW */
+#define	INTC_ISR_SET0		0x90	/* RW */
+#define	INTC_ISR_CLEAR0		0x94	/* RW */
+#define INTC_PENDING_IRQ0	0x98 	/* R */
+#define INTC_PENDING_FIQ0	0x9c 	/* R */
+
+#define	INTC_ITR1		0xa0	/* R */
+#define	INTC_MIR1		0xa4	/* RW */
+#define	INTC_CLEAR1		0xa8	/* RW */
+#define	INTC_SET1		0xac	/* RW */
+#define	INTC_ISR_SET1		0xb0	/* RW */
+#define	INTC_ISR_CLEAR1		0xb4	/* RW */
+#define INTC_PENDING_IRQ1	0xb8 	/* R */
+#define INTC_PENDING_FIQ1	0xbc 	/* R */
+
+#define	INTC_ITR2		0xc0	/* R */
+#define	INTC_MIR2		0xc4	/* RW */
+#define	INTC_CLEAR2		0xc8	/* RW */
+#define	INTC_SET2		0xcc	/* RW */
+#define	INTC_ISR_SET2		0xd0	/* RW */
+#define	INTC_ISR_CLEAR2		0xd4	/* RW */
+#define INTC_PENDING_IRQ2	0xd8 	/* R */
+#define INTC_PENDING_FIQ2	0xdc 	/* R */
+
+#define INTC_ILRn(i)		0x100+(4*i)
+#define		INTC_ILR_IRQ	0x0		/* not of FIQ */
+#define		INTC_ILR_FIQ	0x1
+#define		INTC_ILR_PRIs(pri)	((pri) << 2)
+#define		INTC_ILR_PRI(reg)	(((reg) >> 2) & 0x2f)
+#define		INTC_MIN_PRI	63
+#define		INTC_STD_PRI	32
+#define		INTC_MAX_PRI	0
+
+#define	INTC_SIZE		0x200
+
+#define NIRQ	INTC_NUM_IRQ
+
+struct intrhand {
+	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
+	int (*ih_func)(void *);		/* handler */
+	void *ih_arg;			/* arg for handler */
+	int ih_ipl;			/* IPL_* */
+	int ih_irq;			/* IRQ number */
+	struct evcount	ih_count;
+	char *ih_name;
+};
+
+struct intrq {
+	TAILQ_HEAD(, intrhand) iq_list;	/* handler list */
+	int iq_irq;			/* IRQ to mask while handling */
+	int iq_levels;			/* IPL_*'s this IRQ has */
+	int iq_ist;			/* share type */
+};
+
+volatile int current_ipl_level;
+volatile int softint_pending;
+
+struct intrq intc_handler[NIRQ];
+u_int32_t intc_smask[NIPL];
+u_int32_t intc_imask[3][NIPL];
+
+bus_space_tag_t		intc_iot;
+bus_space_handle_t	intc_ioh;
+
+int	intc_match(struct device *, void *, void *);
+void	intc_attach(struct device *, struct device *, void *);
+int	_spllower(int new);
+int	_splraise(int new);
+void	intc_setipl(int new);
+void	intc_calc_mask(void);
+void	intc_do_pending(void);
+
+struct cfattach	intc_ca = {
+	sizeof (struct device), intc_match, intc_attach
+};
+
+struct cfdriver intc_cd = {
+	NULL, "intc", DV_DULL
+};
+
+int intc_attached = 0;
+
+int
+intc_match(struct device *parent, void *v, void *aux)
+{
+	if (intc_attached != 0)
+		return 0;
+
+	/* XXX */
+	return (1);
+}
+
+void
+intc_attach(struct device *parent, struct device *self, void *args)
+{
+        struct ahb_attach_args *aa = args;
+	int i;
+	u_int32_t rev;
+
+	intc_iot = aa->aa_iot;
+	if (bus_space_map(intc_iot, aa->aa_addr, INTC_SIZE, 0, &intc_ioh))
+		panic("intc_attach: bus_space_map failed!");
+
+	rev = bus_space_read_4(intc_iot, intc_ioh, INTC_REVISION);
+
+	printf(" rev %d.%d\n", rev >> 4 & 0xf, rev & 0xf);
+
+	/* software reset of the part? */
+	/* set protection bit (kernel only)? */
+#if 0
+	bus_space_write_4(intc_iot, intc_ioh, INTC_PROTECTION,
+	     INTC_PROTECTION_PROT);
+#endif
+
+
+	/* XXX - check power saving bit */
+
+
+	/* mask all interrupts */
+	bus_space_write_4(intc_iot, intc_ioh, INTC_MIR0, 0xffffffff);
+	bus_space_write_4(intc_iot, intc_ioh, INTC_MIR1, 0xffffffff);
+	bus_space_write_4(intc_iot, intc_ioh, INTC_MIR2, 0xffffffff);
+
+	for (i = 0; i < NIRQ; i++) {
+		bus_space_write_4(intc_iot, intc_ioh, INTC_ILRn(i),
+		    INTC_ILR_PRIs(INTC_MIN_PRI)|INTC_ILR_IRQ);
+
+		TAILQ_INIT(&intc_handler[i].iq_list);
+	}
+	intc_calc_mask();
+	bus_space_write_4(intc_iot, intc_ioh, INTC_CONTROL,
+	    INTC_CONTROL_NEWIRQ);
+
+	intc_attached = 1;
+
+	_splraise(IPL_HIGH);
+	enable_interrupts(I32_bit);
+}
+
+void
+intc_calc_mask(void)
+{
+	int irq;
+	struct intrhand *ih;
+	int i;
+
+	for (irq = 0; irq < NIRQ; irq++) {
+		int max = IPL_NONE;
+		int min = IPL_HIGH;
+		TAILQ_FOREACH(ih, &intc_handler[irq].iq_list, ih_list) {
+			if (ih->ih_ipl > max)
+				max = ih->ih_ipl;
+
+			if (ih->ih_ipl < min)
+				min = ih->ih_ipl;
+		}
+
+		intc_handler[irq].iq_irq = max;
+
+		if (max == IPL_NONE)
+			min = IPL_NONE;
+
+#ifdef DEBUG_INTC
+		if (min != IPL_NONE) {
+			printf("irq %d to block at %d %d reg %d bit %d\n",
+			    irq, max, min, INTC_IRQ_TO_REG(irq),
+			    INTC_IRQ_TO_REGi(irq));
+		}
+#endif
+		/* Enable interrupts at lower levels, clear -> enable */
+		for (i = 0; i < min; i++)
+			intc_imask[INTC_IRQ_TO_REG(irq)][i] &=
+			    ~(1 << INTC_IRQ_TO_REGi(irq));
+		for (; i <= IPL_HIGH; i++)
+			intc_imask[INTC_IRQ_TO_REG(irq)][i] |=
+			    1 << INTC_IRQ_TO_REGi(irq);
+		/* XXX - set enable/disable, priority */ 
+		bus_space_write_4(intc_iot, intc_ioh, INTC_ILRn(irq),
+		    INTC_ILR_PRIs(NIPL-max)|INTC_ILR_IRQ);
+	}
+	for (i = IPL_NONE; i <= IPL_HIGH; i++) {
+#if 0
+		printf("calc_mask lvl %d val %x %x %x\n", i,
+		    intc_imask[0][i], intc_imask[1][i], intc_imask[2][i] );
+#endif
+		intc_smask[i] = 0;
+		if (i < IPL_SOFT)
+			intc_smask[i] |= SI_TO_IRQBIT(SI_SOFT);
+		if (i < IPL_SOFTCLOCK)
+			intc_smask[i] |= SI_TO_IRQBIT(SI_SOFTCLOCK);
+		if (i < IPL_SOFTNET)
+			intc_smask[i] |= SI_TO_IRQBIT(SI_SOFTNET);
+		if (i < IPL_SOFTTTY)
+			intc_smask[i] |= SI_TO_IRQBIT(SI_SOFTTTY);
+	}
+	intc_setipl(current_ipl_level);
+}
+
+/*
+ * XXX - is it possible to do the soft interrupts with actual interrupt
+ * instead of emulating them?
+ */
+void
+intc_do_pending(void)
+{
+	static int processing = 0;
+	int oldirqstate, spl_save;
+
+	oldirqstate = disable_interrupts(I32_bit);
+
+	spl_save = current_ipl_level;
+
+	if (processing == 1) {
+		restore_interrupts(oldirqstate);
+		return;
+	}
+//	printf("softint_pending %x\n", softint_pending);
+
+#define DO_SOFTINT(si, ipl) \
+	if ((softint_pending & intc_smask[current_ipl_level]) &	\
+	    SI_TO_IRQBIT(si)) {						\
+		softint_pending &= ~SI_TO_IRQBIT(si);			\
+		if (current_ipl_level < ipl)				\
+			intc_setipl(ipl);				\
+		restore_interrupts(oldirqstate);			\
+		softintr_dispatch(si);					\
+		oldirqstate = disable_interrupts(I32_bit);		\
+		intc_setipl(spl_save);					\
+	}
+
+	do {
+		DO_SOFTINT(SI_SOFTTTY, IPL_SOFTTTY);
+		DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET);
+		DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK);
+		DO_SOFTINT(SI_SOFT, IPL_SOFT);
+	} while (softint_pending & intc_smask[current_ipl_level]);
+		
+
+#if 0
+	printf("exit softint_pending %x pri %x mask %x\n", softint_pending,
+	    current_ipl_level, intc_smask[current_ipl_level]);
+#endif
+
+	processing = 0;
+	restore_interrupts(oldirqstate);
+}
+
+void
+splx(int new)
+{
+
+	intc_setipl(new);
+
+	if (softint_pending & intc_smask[current_ipl_level])
+		intc_do_pending();
+}
+
+int
+_spllower(int new)
+{
+	int old = current_ipl_level;
+	splx(new);
+	return (old);
+}
+
+int
+_splraise(int new)
+{
+	int old;
+	old = current_ipl_level;
+
+	/*
+	 * setipl must always be called because there is a race window
+	 * where the variable is updated before the mask is set
+	 * an interrupt occurs in that window without the mask always
+	 * being set, the hardware might not get updated on the next
+	 * splraise completely messing up spl protection.
+	 */
+	if (old > new)
+		new = old;
+
+	intc_setipl(new);
+  
+	return (old);
+}
+
+void
+_setsoftintr(int si)
+{
+	int oldirqstate;
+
+	oldirqstate = disable_interrupts(I32_bit);
+	softint_pending |= SI_TO_IRQBIT(si);
+	restore_interrupts(oldirqstate);
+
+	/* Process unmasked pending soft interrupts. */
+	if (softint_pending & intc_smask[current_ipl_level])
+		intc_do_pending();
+}
+
+
+
+void
+intc_setipl(int new)
+{
+	int i;
+	int psw;
+	if (intc_attached == 0)
+		return;
+
+	psw = disable_interrupts(I32_bit);
+	current_ipl_level = new;
+	for (i = 0; i < 3; i++)
+		bus_space_write_4(intc_iot, intc_ioh,
+		    INTC_MIRn(i), intc_imask[i][new]);
+	bus_space_write_4(intc_iot, intc_ioh, INTC_CONTROL,
+	    INTC_CONTROL_NEWIRQ);
+	restore_interrupts(psw);
+}
+
+void
+intc_intr_bootstrap(vaddr_t addr)
+{
+	int i, j;
+	extern struct bus_space armv7_bs_tag;
+	intc_iot = &armv7_bs_tag;
+	intc_ioh = addr;
+	for (i = 0; i < 3; i++)
+		for (j = 0; j < NIPL; j++)
+			intc_imask[i][j] = 0xffffffff;
+}
+
+void
+intc_irq_handler(void *frame)
+{
+	int irq, pri, s;
+	struct intrhand *ih;
+	void *arg;
+
+	irq = bus_space_read_4(intc_iot, intc_ioh, INTC_SIR_IRQ);
+#ifdef DEBUG_INTC
+	printf("irq %d fired\n", irq);
+#endif
+
+	pri = intc_handler[irq].iq_irq;
+	s = _splraise(pri);
+	TAILQ_FOREACH(ih, &intc_handler[irq].iq_list, ih_list) {
+		if (ih->ih_arg != 0)
+			arg = ih->ih_arg;
+		else
+			arg = frame;
+
+		if (ih->ih_func(arg)) 
+			ih->ih_count.ec_count++;
+
+	}
+	bus_space_write_4(intc_iot, intc_ioh, INTC_CONTROL,
+	    INTC_CONTROL_NEWIRQ);
+	splx(s);	 /* XXX - handles pending */
+}
+
+void *
+intc_intr_establish(int irqno, int level, int (*func)(void *),
+    void *arg, char *name)
+{
+	int psw;
+	struct intrhand *ih;
+
+	if (irqno < 0 || irqno > NIRQ)
+		panic("intc_intr_establish: bogus irqnumber %d: %s\n",
+		     irqno, name);
+	psw = disable_interrupts(I32_bit);
+
+	/* no point in sleeping unless someone can free memory. */
+	ih = (struct intrhand *)malloc (sizeof *ih, M_DEVBUF,
+	    cold ? M_NOWAIT : M_WAITOK);
+	if (ih == NULL)
+		panic("intr_establish: can't malloc handler info");
+	ih->ih_func = func;
+	ih->ih_arg = arg;
+	ih->ih_ipl = level;
+	ih->ih_irq = irqno;
+	ih->ih_name = name;
+
+	TAILQ_INSERT_TAIL(&intc_handler[irqno].iq_list, ih, ih_list);
+
+	if (name != NULL)
+		evcount_attach(&ih->ih_count, name, (void *)&ih->ih_irq,
+		    &evcount_intr);
+
+#ifdef DEBUG_INTC
+	printf("intc_intr_establish irq %d level %d [%s]\n", irqno, level,
+	    name);
+#endif
+	intc_calc_mask();
+	
+	restore_interrupts(psw);
+	return (ih);
+}
+
+void
+intc_intr_disestablish(void *cookie)
+{
+	int psw;
+	struct intrhand *ih = cookie;
+	int irqno = ih->ih_irq;
+	psw = disable_interrupts(I32_bit);
+	TAILQ_REMOVE(&intc_handler[irqno].iq_list, ih, ih_list);
+	if (ih->ih_name != NULL)
+		evcount_detach(&ih->ih_count);
+	free(ih, M_DEVBUF);
+	restore_interrupts(psw);
+}
+
+#if 0
+int intc_tst(void *a);
+
+int
+intc_tst(void *a)
+{
+	printf("inct_tst called\n");
+	bus_space_write_4(intc_iot, intc_ioh, INTC_ISR_CLEAR0, 2);
+	return 1;
+}
+
+void intc_test(void);
+void intc_test(void)
+{
+	void * ih;
+	printf("about to register handler\n");
+	ih = intc_intr_establish(1, IPL_BIO, intc_tst, NULL, "intctst");
+
+	printf("about to set bit\n");
+	bus_space_write_4(intc_iot, intc_ioh, INTC_ISR_SET0, 2);
+
+	printf("about to clear bit\n");
+	bus_space_write_4(intc_iot, intc_ioh, INTC_ISR_CLEAR0, 2);
+
+	printf("about to remove handler\n");
+	intc_intr_disestablish(ih);
+
+	printf("done\n");
+}
+#endif
diff --git a/sys/arch/beagle/dev/intc.h b/sys/arch/beagle/dev/intc.h
new file mode 100644
index 00000000000..44617cf8347
--- /dev/null
+++ b/sys/arch/beagle/dev/intc.h
@@ -0,0 +1,83 @@
+/*	$OpenBSD: intc.h,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _OMAPINTC_INTR_H_
+#define _OMAPINTC_INTR_H_
+
+#define	ARM_IRQ_HANDLER	_C_LABEL(intc_irq_handler)
+
+#ifndef _LOCORE
+
+#include <arm/armreg.h>
+#include <arm/cpufunc.h>
+#include <machine/intr.h>
+#include <arm/softintr.h>
+
+extern __volatile int current_spl_level;
+extern __volatile int softint_pending;
+void intc_do_pending(void);
+
+#define SI_TO_IRQBIT(si)  (1U<<(si))
+void intc_setipl(int new);
+void intc_splx(int new);
+int intc_splraise(int ipl);
+int intc_spllower(int ipl);
+void intc_setsoftintr(int si);
+
+#define  INTC_NUM_IRQ	96
+
+/*
+ * An useful function for interrupt handlers.
+ * XXX: This shouldn't be here.
+ */
+static __inline int
+find_first_bit( uint32_t bits )
+{
+	int count;
+
+	/* since CLZ is available only on ARMv5, this isn't portable
+	 * to all ARM CPUs.  This file is for OMAPINTC processor. 
+	 */
+	asm( "clz %0, %1" : "=r" (count) : "r" (bits) );
+	return 31-count;
+}
+
+
+int	_splraise(int);
+int	_spllower(int);
+void	splx(int);
+void	_setsoftintr(int);
+
+/*
+ * This function *MUST* be called very early on in a port's
+ * initarm() function, before ANY spl*() functions are called.
+ *
+ * The parameter is the virtual address of the OMAPINTC's Interrupt
+ * Controller registers.
+ */
+void intc_intr_bootstrap(vaddr_t);
+
+void intc_irq_handler(void *);
+void *intc_intr_establish(int irqno, int level, int (*func)(void *),
+    void *cookie, char *name);
+void intc_intr_disestablish(void *cookie);
+const char *intc_intr_string(void *cookie);
+
+#endif /* ! _LOCORE */
+
+#endif /* _OMAPINTC_INTR_H_ */
+
diff --git a/sys/arch/beagle/dev/omap_com.c b/sys/arch/beagle/dev/omap_com.c
new file mode 100644
index 00000000000..b1181496516
--- /dev/null
+++ b/sys/arch/beagle/dev/omap_com.c
@@ -0,0 +1,150 @@
+/* $OpenBSD: omap_com.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Steve C. Woodford for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/tty.h>
+
+#include <machine/intr.h>
+#include <machine/bus.h>
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+/* pick up armv7_a4x_bs_tag */
+#include <arch/arm/armv7/armv7var.h>
+
+#include <arch/beagle/beagle/ahb.h>
+
+#define com_isr 8
+#define ISR_RECV	(ISR_RXPL | ISR_XMODE | ISR_RCVEIR)
+
+int	omapuart_match(struct device *, void *, void *);
+void	omapuart_attach(struct device *, struct device *, void *);
+void	omapuart_power(int why, void *);
+
+struct cfattach com_ahb_ca = {
+        sizeof (struct com_softc), omapuart_match, omapuart_attach
+};
+
+int
+omapuart_match(struct device *parent, void *cf, void *aux)
+{
+        struct ahb_attach_args *aa = aux;
+	bus_space_tag_t bt = &armv7_a4x_bs_tag;	/* XXX: This sucks */
+	bus_space_handle_t bh;
+	int rv;
+
+	/* XXX */
+	if (aa->aa_addr == 0x4806A000 && aa->aa_intr == 72)
+		return 1;
+	if (aa->aa_addr == 0x4806C000 && aa->aa_intr == 73)
+		return 1;
+	if (aa->aa_addr == 0x4806E000 && aa->aa_intr == 74)
+		return 1;
+	{
+		extern bus_addr_t comconsaddr;
+
+		if (comconsaddr == aa->aa_addr)
+			return (1);
+	}
+
+	if (bus_space_map(bt, aa->aa_addr, aa->aa_size, 0, &bh))
+		return (0);
+
+	/* Make sure the UART is enabled - XXX */
+	bus_space_write_1(bt, bh, com_ier, IER_EUART);
+
+	rv = comprobe1(bt, bh);
+	bus_space_unmap(bt, bh, aa->aa_size);
+
+	return (rv);
+}
+
+void
+omapuart_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct com_softc *sc = (struct com_softc *)self;
+        struct ahb_attach_args *aa = aux;
+
+	sc->sc_iot = &armv7_a4x_bs_tag;	/* XXX: This sucks */
+	sc->sc_iobase = aa->aa_addr;
+	sc->sc_frequency = 48000000;
+	sc->sc_uarttype = COM_UART_TI16750;
+
+	bus_space_map(sc->sc_iot, sc->sc_iobase, aa->aa_size, 0, &sc->sc_ioh);
+
+	com_attach_subr(sc);
+
+	(void)intc_intr_establish(aa->aa_intr, IPL_TTY, comintr,
+	    sc, sc->sc_dev.dv_xname);
+
+#if 0
+	(void)powerhook_establish(&omapuart_power, sc);
+#endif
+}
+
+#if 0
+void
+omapuart_power(int why, void *arg)
+{
+	struct com_softc *sc = arg;
+	bus_space_tag_t iot = sc->sc_iot;
+	bus_space_handle_t ioh = sc->sc_ioh;
+	struct tty *tp = sc->sc_tty;
+
+	switch (why) {
+	case PWR_SUSPEND:
+	case PWR_STANDBY:
+		break;
+	case PWR_RESUME:
+		if (sc->enabled) {
+			sc->sc_initialize = 1;
+			comparam(tp, &tp->t_termios);
+			bus_space_write_1(iot, ioh, com_ier, sc->sc_ier);
+
+			if (ISSET(sc->sc_hwflags, COM_HW_SIR)) {
+				bus_space_write_1(iot, ioh, com_isr,
+				    ISR_RECV);
+			}
+		}
+		break;
+	}
+}
+#endif
diff --git a/sys/arch/beagle/dev/omdisplay.c b/sys/arch/beagle/dev/omdisplay.c
new file mode 100644
index 00000000000..062867ce71c
--- /dev/null
+++ b/sys/arch/beagle/dev/omdisplay.c
@@ -0,0 +1,1377 @@
+/* $OpenBSD: omdisplay.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+#include <sys/evcount.h>
+#include <sys/conf.h>
+#include <sys/uio.h>
+#include <machine/bus.h>
+#include <arch/beagle/beagle/ahb.h>
+#include <arch/beagle/dev/omgpiovar.h>
+
+#include <dev/cons.h>
+#include <dev/wscons/wsconsio.h>
+#include <dev/wscons/wsdisplayvar.h>
+#include <dev/wscons/wscons_callbacks.h>
+
+#include <dev/rasops/rasops.h>
+
+#include "splash16.h"
+
+#define OMDISPLAY_SIZE			0x1000
+/* registers */
+/* DSS */
+#define DSS_REVISIONNUMBER		0x00
+#define DSS_CONTROL			0x40
+#define DSS_PSA_LCD_REG_1		0x50
+#define DSS_PSA_LCD_REG_2		0x54
+#define DSS_PSA_VIDEO_REG		0x58
+#define DSS_STATUS			0x5C
+
+/* DCR */
+#define DISPC_REVISION			0x0000
+#define DISPC_SYSCONFIG			0x0010
+#define		DISPC_SYSCONFIG_AUTOIDLE		0x00000001
+#define		DISPC_SYSCONFIG_SOFTRESET		0x00000002
+#define		DISPC_SYSCONFIG_SIDLEMODE_FORCE		0x00000000
+#define		DISPC_SYSCONFIG_SIDLEMODE_NONE		0x00000008
+#define		DISPC_SYSCONFIG_SIDLEMODE_SMART		0x00000010
+#define		DISPC_SYSCONFIG_MIDLEMODE_FORCE		0x00000000
+#define		DISPC_SYSCONFIG_MIDLEMODE_NONE		0x00001000
+#define		DISPC_SYSCONFIG_MIDLEMODE_SMART		0x00002000
+#define DISPC_SYSSTATUS			0x0014
+#define		DISPC_SYSTATUS_RESETDONE		0x00000001
+#define DISPC_IRQSTATUS			0x0018
+#define		DISPC_IRQSTATUS_FRAMEDONE		0x00000001
+#define		DISPC_IRQSTATUS_VSYNC			0x00000002
+#define		DISPC_IRQSTATUS_EVSYNCEVEN		0x00000004
+#define		DISPC_IRQSTATUS_EVSYNCODD		0x00000008
+#define		DISPC_IRQSTATUS_ACBIASCOUNT		0x00000010
+#define		DISPC_IRQSTATUS_PROGLINENUM		0x00000020
+#define		DISPC_IRQSTATUS_GFXFIFOUNDER		0x00000040
+#define		DISPC_IRQSTATUS_GFXENDWINDOW		0x00000080
+#define		DISPC_IRQSTATUS_PALGAMMA		0x00000100
+#define		DISPC_IRQSTATUS_OCPERROR		0x00000200
+#define		DISPC_IRQSTATUS_VID1FIFOUNDER		0x00000400
+#define		DISPC_IRQSTATUS_VID1ENDWIND		0x00000800
+#define		DISPC_IRQSTATUS_VID2FIFOUNDER		0x00001000
+#define		DISPC_IRQSTATUS_VID2ENDWIND		0x00002000
+#define		DISPC_IRQSTATUS_SYNCLOST		0x00004000
+#define DISPC_IRQENABLE			0x001C
+#define		DISPC_IRQENABLE_FRAMEDONE		0x00000001
+#define		DISPC_IRQENABLE_VSYNC			0x00000002
+#define		DISPC_IRQENABLE_EVSYNCEVEN		0x00000004
+#define		DISPC_IRQENABLE_EVSYNCODD		0x00000008
+#define		DISPC_IRQENABLE_ACBIASCOUNT		0x00000010
+#define		DISPC_IRQENABLE_PROGLINENUM		0x00000020
+#define		DISPC_IRQENABLE_GFXFIFOUNDER		0x00000040
+#define		DISPC_IRQENABLE_GFXENDWINDOW		0x00000080
+#define		DISPC_IRQENABLE_PALGAMMA		0x00000100
+#define		DISPC_IRQENABLE_OCPERROR		0x00000200
+#define		DISPC_IRQENABLE_VID1FIFOUNDER		0x00000400
+#define		DISPC_IRQENABLE_VID1ENDWIND		0x00000800
+#define		DISPC_IRQENABLE_VID2FIFOUNDER		0x00001000
+#define		DISPC_IRQENABLE_VID2ENDWIND		0x00002000
+#define		DISPC_IRQENABLE_SYNCLOST		0x00004000
+#define DISPC_CONTROL			0x0040
+#define 	DISPC_CONTROL_LCDENABLE			0x00000001
+#define 	DISPC_CONTROL_DIGITALENABLE		0x00000002
+#define 	DISPC_CONTROL_MONOCOLOR			0x00000004
+#define 	DISPC_CONTROL_STNTFT			0x00000008
+#define 	DISPC_CONTROL_M8B			0x00000010
+#define 	DISPC_CONTROL_GOLCD			0x00000020
+#define 	DISPC_CONTROL_GODIGITAL			0x00000040
+#define 	DISPC_CONTROL_TFTDITHEREN		0x00000080
+#define 	DISPC_CONTROL_TFTDATALINES_12		0x00000000
+#define 	DISPC_CONTROL_TFTDATALINES_16		0x00000100
+#define 	DISPC_CONTROL_TFTDATALINES_18		0x00000200
+#define 	DISPC_CONTROL_TFTDATALINES_24		0x00000300
+#define 	DISPC_CONTROL_SECURE			0x00000400
+#define 	DISPC_CONTROL_RFBIMODE			0x00000800
+#define 	DISPC_CONTROL_OVERLAYOPT		0x00001000
+#define 	DISPC_CONTROL_GPIN0			0x00002000
+#define 	DISPC_CONTROL_GPIN1			0x00004000
+#define 	DISPC_CONTROL_GPOUT0			0x00008000
+#define 	DISPC_CONTROL_GPOUT1			0x00010000
+#define 	DISPC_CONTROL_HT			0x00070000
+#define 	DISPC_CONTROL_HT_s(x)			((x) << 17)
+#define 	DISPC_CONTROL_TDMENABLE			0x00100000
+#define 	DISPC_CONTROL_TDMPARALLEL_8		0x00000000
+#define 	DISPC_CONTROL_TDMPARALLEL_9		0x00200000
+#define 	DISPC_CONTROL_TDMPARALLEL_12		0x00400000
+#define 	DISPC_CONTROL_TDMPARALLEL_16		0x00600000
+#define 	DISPC_CONTROL_TDMCYCLE_1		0x00000000
+#define 	DISPC_CONTROL_TDMCYCLE_2		0x00800000
+#define 	DISPC_CONTROL_TDMCYCLE_3		0x00000000
+#define 	DISPC_CONTROL_TDMCYCLE_3_2		0x01800000
+#define 	DISPC_CONTROL_TDMUNUSED_0		0x00000000
+#define 	DISPC_CONTROL_TDMUNUSED_1		0x02000000
+#define 	DISPC_CONTROL_TDMUNUSED_M		0x04000000
+#define DISPC_CONFIG			0x0044
+#define 	DISPC_CONFIG_PIXELGATED			0x00000001
+#define 	DISPC_CONFIG_LOADMODE_PGE		0x00000000
+#define 	DISPC_CONFIG_LOADMODE_PG		0x00000002
+#define 	DISPC_CONFIG_LOADMODE_DATA		0x00000004
+#define 	DISPC_CONFIG_LOADMODE_DATA_PG		0x00000006
+#define 	DISPC_CONFIG_PALETTEGAMMA		0x00000008
+#define 	DISPC_CONFIG_PIXELDATAGATED		0x00000010
+#define 	DISPC_CONFIG_PIXELCLOCKGATED		0x00000020
+#define 	DISPC_CONFIG_HSYNCGATED			0x00000040
+#define 	DISPC_CONFIG_VSYNCGATED			0x00000080
+#define 	DISPC_CONFIG_ACBIAGATED			0x00000100
+#define 	DISPC_CONFIG_FUNCGATED			0x00000200
+#define 	DISPC_CONFIG_TCKLCDEN			0x00000400
+#define 	DISPC_CONFIG_TCKLCDSEL			0x00000800
+#define 	DISPC_CONFIG_TCKDIGEN			0x00001000
+#define 	DISPC_CONFIG_TCKDIGSEL			0x00002000
+#define DISPC_CAPABLE			0x0048
+#define DISPC_DEFAULT_COLOR0		0x004C
+#define DISPC_DEFAULT_COLOR1		0x0050
+#define DISPC_TRANS_COLOR0		0x0054
+#define DISPC_TRANS_COLOR1		0x0058
+#define DISPC_LINE_STATUS		0x005C
+#define DISPC_LINE_NUMBER		0x0060
+#define DISPC_TIMING_H			0x0064
+#define		DISPC_TIMING_H_HSW_s(x)	((x) << 0)
+#define		DISPC_TIMING_H_HFP_s(x)	((x) << 8)
+#define		DISPC_TIMING_H_HBP_s(x)	((x) << 20)
+#define DISPC_TIMING_V			0x0068
+#define		DISPC_TIMING_V_VSW_s(x)	((x) << 0)
+#define		DISPC_TIMING_V_VFP_s(x)	((x) << 8)
+#define		DISPC_TIMING_V_VBP_s(x)	((x) << 20)
+#define DISPC_POL_FREQ			0x006C
+#define 	DISPC_POL_FREQ_ACB_s(x)	((x) << 0)
+#define 	DISPC_POL_FREQ_ACBI_s(x)	((x) << 8)
+#define 	DISPC_POL_FREQ_IVS	0x00001000
+#define 	DISPC_POL_FREQ_IHS	0x00002000
+#define 	DISPC_POL_FREQ_IPC	0x00004000
+#define 	DISPC_POL_FREQ_IEO	0x00008000
+#define 	DISPC_POL_FREQ_RF	0x00010000
+#define 	DISPC_POL_FREQ_ONOFF	0x00020000
+#define DISPC_DIVISOR			0x0070
+#define		DISPC_DIVISOR_PCD_s(x)	((x) << 0)
+#define		DISPC_DIVISOR_LCD_s(x)	((x) << 16)
+#define DISPC_SIZE_DIG			0x0078
+#define		DISPC_SIZE_DIG_PPL_s(x)	((x) << 0)
+#define		DISPC_SIZE_DIG_LPP_s(x)	((x) << 16)
+#define DISPC_SIZE_LCD			0x007C
+#define		DISPC_SIZE_LCD_PPL_s(x)	((x) << 0)
+#define		DISPC_SIZE_LCD_LPP_s(x)	((x) << 16)
+#define DISPC_GFX_BA0			0x0080
+#define DISPC_GFX_BA1			0x0084
+#define DISPC_GFX_POSITION		0x0088
+#define DISPC_GFX_SIZE			0x008C
+#define		DISPC_GFX_SIZE_X_s(x)	((x) << 0)
+#define		DISPC_GFX_SIZE_Y_s(x)	((x) << 16)
+#define DISPC_GFX_ATTRIBUTES		0x00A0
+#define		DISPC_GFX_ATTRIBUTES_GFXENABLE		0x001
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_1		0x000
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_2		0x002
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_4		0x004
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_8		0x006
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_12		0x008
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_16		0x00c
+#define		DISPC_GFX_ATTRIBUTES_GFXFMT_24		0x010
+#define		DISPC_GFX_ATTRIBUTES_GFXREPLICATE	0x020
+#define		DISPC_GFX_ATTRIBUTES_BURST_4		0x000
+#define		DISPC_GFX_ATTRIBUTES_BURST_8		0x040
+#define		DISPC_GFX_ATTRIBUTES_BURST_16		0x080
+#define		DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT	0x100
+#define		DISPC_GFX_ATTRIBUTES_NIBBLEMODE		0x200
+#define		DISPC_GFX_ATTRIBUTES_ENDIAN		0x400
+#define DISPC_GFX_FIFO_THRESHOLD	0x00A4
+#define 	DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT	16
+#define 	DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT	0
+#define DISPC_GFX_FIFO_SIZE_STATUS	0x00A8
+#define DISPC_GFX_ROW_INC		0x00AC
+#define DISPC_GFX_PIXEL_INC		0x00B0
+#define DISPC_GFX_WINDOW_SKIP		0x00B4
+#define DISPC_GFX_TABLE_BA		0x00B8
+#define DISPC_VID1_BA0			0x00BC
+#define DISPC_VID1_BA1			0x00C0
+#define DISPC_VID1_POSITION		0x00C4
+#define DISPC_VID1_SIZE			0x00C8
+#define DISPC_VID1_ATTRIBUTES		0x00CC
+#define DISPC_VID1_FIFO_THRESHOLD	0x00D0
+#define DISPC_VID1_FIFO_SIZE_STATUS	0x00D4
+#define DISPC_VID1_ROW_INC		0x00D8
+#define DISPC_VID1_PIXEL_INC		0x00DC
+#define DISPC_VID1_FIR			0x00E0
+#define DISPC_VID1_PICTURE_SIZE		0x00E4
+#define DISPC_VID1_ACCU0 		0x00E8
+#define DISPC_VID1_ACCU1		0x00EC
+#define DISPC_VID1_FIR_COEF_H0		0x00F0
+#define DISPC_VID1_FIR_COEF_H1		0x00F8
+#define DISPC_VID1_FIR_COEF_H2		0x0100
+#define DISPC_VID1_FIR_COEF_H3		0x0108
+#define DISPC_VID1_FIR_COEF_H4		0x0110
+#define DISPC_VID1_FIR_COEF_H5		0x0118
+#define DISPC_VID1_FIR_COEF_H6		0x0120
+#define DISPC_VID1_FIR_COEF_H7		0x0128
+#define DISPC_VID1_FIR_COEF_HV0		0x00F4
+#define DISPC_VID1_FIR_COEF_HV1		0x00FC
+#define DISPC_VID1_FIR_COEF_HV2		0x0104
+#define DISPC_VID1_FIR_COEF_HV3		0x010C
+#define DISPC_VID1_FIR_COEF_HV4		0x0114
+#define DISPC_VID1_FIR_COEF_HV5		0x011C
+#define DISPC_VID1_FIR_COEF_HV6		0x0124
+#define DISPC_VID1_FIR_COEF_HV7		0x012C
+#define DISPC_VID1_CONV_COEF0		0x0130
+#define DISPC_VID1_CONV_COEF1		0x0134
+#define DISPC_VID1_CONV_COEF2		0x0138
+#define DISPC_VID1_CONV_COEF3		0x013C
+#define DISPC_VID1_CONV_COEF4		0x0140
+#define DISPC_VID2_BA0			0x014C
+#define DISPC_VID2_BA1			0x0150
+#define DISPC_VID2_POSITION		0x0154
+#define DISPC_VID2_SIZE			0x0158
+#define DISPC_VID2_ATTRIBUTES		0x015C
+#define DISPC_VID2_FIFO_THRESHOLD	0x0160
+#define DISPC_VID2_FIFO_SIZE_STATUS	0x0164
+#define DISPC_VID2_ROW_INC		0x0168
+#define DISPC_VID2_PIXEL_INC		0x016C
+#define DISPC_VID2_FIR			0x0170
+#define DISPC_VID2_PICTURE_SIZE		0x0174
+#define DISPC_VID2_ACCU0		0x0178
+#define DISPC_VID2_ACCU1		0x017C
+#define DISPC_VID2_FIR_COEF_H0		0x0180
+#define DISPC_VID2_FIR_COEF_H1		0x0188
+#define DISPC_VID2_FIR_COEF_H2		0x0190
+#define DISPC_VID2_FIR_COEF_H3		0x0198
+#define DISPC_VID2_FIR_COEF_H4		0x01A0
+#define DISPC_VID2_FIR_COEF_H5		0x01A8
+#define DISPC_VID2_FIR_COEF_H6		0x01B0
+#define DISPC_VID2_FIR_COEF_H7		0x01B8
+#define DISPC_VID2_FIR_COEF_HV0		0x0184
+#define DISPC_VID2_FIR_COEF_HV1		0x018C
+#define DISPC_VID2_FIR_COEF_HV2		0x0194
+#define DISPC_VID2_FIR_COEF_HV3		0x019C
+#define DISPC_VID2_FIR_COEF_HV4		0x01A4
+#define DISPC_VID2_FIR_COEF_HV5		0x01AC
+#define DISPC_VID2_FIR_COEF_HV6		0x01B4
+#define DISPC_VID2_FIR_COEF_HV7		0x01BC
+#define DISPC_VID2_CONV_COEF0		0x01C0
+#define DISPC_VID2_CONV_COEF1		0x01C4
+#define DISPC_VID2_CONV_COEF2		0x01C8
+#define DISPC_VID2_CONV_COEF3		0x01CC
+#define DISPC_VID2_CONV_COEF4		0x01D0
+#define DISPC_DATA_CYCLE1		0x01D4
+#define DISPC_DATA_CYCLE2		0x01D8
+#define DISPC_DATA_CYCLE3		0x01DC
+#define DISPC_SIZE			0x0200
+
+/* RFBI */
+#define RFBI_REVISION		0x0000
+#define RFBI_SYSCONFIG		0x0010
+#define RFBI_SYSSTATUS		0x0014
+#define RFBI_CONTROL		0x0040
+#define RFBI_PIXEL_CNT		0x0044
+#define RFBI_LINE_NUMBER	0x0048
+#define RFBI_CMD		0x004C
+#define RFBI_PARAM		0x0050
+#define RFBI_DATA		0x0054
+#define RFBI_READ		0x0058
+#define RFBI_STATUS		0x005C
+#define RFBI_CONFIG0		0x0060
+#define RFBI_CONFIG1		0x0078
+#define RFBI_ONOFF_TIME0	0x0064
+#define RFBI_ONOFF_TIME1	0x007C
+#define RFBI_CYCLE_TIME0	0x0068
+#define RFBI_CYCLE_TIME1	0x0080
+#define RFBI_DATA_CYCLE1_0	0x006C
+#define RFBI_DATA_CYCLE1_1	0x0084
+#define RFBI_DATA_CYCLE2_0	0x0070
+#define RFBI_DATA_CYCLE2_1	0x0088
+#define RFBI_DATA_CYCLE3_0	0x0074
+#define RFBI_DATA_CYCLE3_1	0x008C
+#define RFBI_VSYNC_WIDTH	0x0090
+#define RFBI_HSYNC_WIDTH	0x0094
+
+/* VENC1 */
+#define REV_ID				0x0000
+#define STATUS				0x0004
+#define F_CONTROL			0x0008
+#define VIDOUT_CTRL			0x0010
+#define SYNC_CTRL			0x0014
+#define LLEN				0x001C
+#define FLENS				0x0020
+#define HFLTR_CTRL			0x0024
+#define CC_CARR_WSS_CARR		0x0028
+#define C_PHASE				0x002C
+#define GAIN_U				0x0030
+#define GAIN_V				0x0034
+#define GAIN_Y				0x0038
+#define BLACK_LEVEL			0x003C
+#define BLANK_LEVEL			0x0040
+#define X_COLOR				0x0044
+#define M_CONTROL			0x0048
+#define BSTAMP_WSS_DATA			0x004C
+#define S_CARR				0x0050
+#define LINE21				0x0054
+#define LN_SEL				0x0058
+#define L21_WC_CTL			0x005C
+#define HTRIGGER_VTRIGGER		0x0060
+#define SAVID_EAVID			0x0064
+#define FLEN_FAL			0x0068
+#define LAL_PHASE_RESET			0x006C
+#define HS_INT_START_STOP_X			0x0070
+#define HS_EXT_START_STOP_X			0x0074
+#define VS_INT_START_X				0x0078
+#define VS_INT_STOP_X_VS_INT_START_Y		0x007C
+#define VS_INT_STOP_Y_VS_EXT_START_X		0x0080
+#define VS_EXT_STOP_X_VS_EXT_START_Y		0x0084
+#define VS_EXT_STOP_Y				0x0088
+#define AVID_START_STOP_X			0x0090
+#define AVID_START_STOP_Y			0x0094
+#define FID_INT_START_X_FID_INT_START_Y		0x00A0
+#define FID_INT_OFFSET_Y_FID_EXT_START_X	0x00A4
+#define FID_EXT_START_Y_FID_EXT_OFFSET_Y	0x00A8
+#define TVDETGP_INT_START_STOP_X	0x00B0
+#define TVDETGP_INT_START_STOP_Y	0x00B4
+#define GEN_CTRL			0x00B8
+#define DAC_TST_DAC_A			0x00C4
+#define DAC_B_DAC_C			0x00C8
+
+
+/* NO CONSOLE SUPPORT */
+
+
+/* assumes 565 panel. */
+struct omdisplay_panel_data {
+	int width;
+	int height;
+	int horiz_sync_width;
+	int horiz_front_porch;
+	int horiz_back_porch;
+	int vert_sync_width;
+	int vert_front_porch;
+	int vert_back_porch;
+	int panel_flags;
+	int sync;
+	int depth;
+#define PANEL_SYNC_H_ACTIVE_HIGH 1
+#define PANEL_SYNC_V_ACTIVE_HIGH 2
+	int linebytes;
+};
+
+#define PIXELDEPTH	16
+#define PIXELWIDTH	2
+
+struct omdisplay_panel_data	default_panel = {
+	240,	/* Width */
+	322,	/* Height */
+	9, 9, 19, 	/* horiz sync, fp, bp */
+	1, 2, 2,  	/* vert  sync, fp, bp */
+	0, 	/* flags */
+	0,	/* sync */
+	PIXELDEPTH,
+	240*PIXELWIDTH
+};
+
+struct omdisplay_screen {
+	LIST_ENTRY(omdisplay_screen) link;
+
+	/* Frame buffer */
+	bus_dmamap_t dma;
+	bus_dma_segment_t segs[1];
+	int     nsegs;
+	size_t  buf_size;
+	size_t  map_size;
+	void    *buf_va;
+	int     depth;
+
+	/* rasterop */
+	struct rasops_info rinfo;
+};
+
+struct omdisplay_softc {
+	struct device sc_dev;
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_dsioh;
+	bus_space_handle_t sc_dcioh;
+	bus_space_handle_t sc_rfbioh;
+	bus_space_handle_t sc_venioh;
+	bus_dma_tag_t 		sc_dma_tag;
+
+	void *sc_ih;
+
+	int	sc_nscreens;
+	LIST_HEAD(,omdisplay_screen) sc_screens;
+
+	void 				*sc_ph; /* powerhook */
+
+	struct omdisplay_panel_data	*sc_geometry;
+	struct omdisplay_screen		*sc_active;
+};
+
+int omdisplay_match(struct device *parent, void *v, void *aux);
+void omdisplay_attach(struct device *parent, struct device *self, void *args);
+int omdisplay_ioctl(void *v, u_long cmd, caddr_t data, int flag,
+    struct proc *p);
+void omdisplay_burner(void *v, u_int on, u_int flags);
+int omdisplay_show_screen(void *v, void *cookie, int waitok,
+    void (*cb)(void *, int, int), void *cbarg);
+int omdisplay_param(struct omdisplay_softc *sc, ulong cmd,
+    struct wsdisplay_param *dp);
+int omdisplay_max_brightness(void);
+int omdisplay_get_brightness(void);
+void omdisplay_set_brightness(int newval);
+void omdisplay_set_brightness_internal(int newval);
+int omdisplay_get_backlight(void);
+void omdisplay_set_backlight(int on);
+void omdisplay_blank(int blank);
+void omdisplay_suspend(struct omdisplay_softc *sc);
+void omdisplay_resume(struct omdisplay_softc *sc);
+void omdisplay_power(int why, void *v);
+void omdisplay_initialize(struct omdisplay_softc *sc,
+    struct omdisplay_panel_data *geom);
+void omdisplay_setup_rasops(struct omdisplay_softc *sc,
+    struct rasops_info *rinfo);
+int omdisplay_alloc_screen(void *v, const struct wsscreen_descr *_type,
+    void **cookiep, int *curxp, int *curyp, long *attrp);
+int omdisplay_new_screen(struct omdisplay_softc *sc,
+    struct omdisplay_screen *scr, int depth);
+paddr_t omdisplay_mmap(void *v, off_t offset, int prot);
+void omdisplay_free_screen(void *v, void *cookie);
+void omdisplay_start(struct omdisplay_softc *sc);
+void omdisplay_stop(struct omdisplay_softc *sc);
+int omdisplay_intr(void *v);
+void omdisplay_dumpreg(struct omdisplay_softc *sc);
+
+struct cfattach	omdisplay_ca = {
+	sizeof (struct omdisplay_softc), omdisplay_match, omdisplay_attach
+};
+
+struct cfdriver omdisplay_cd = {
+	NULL, "omdisplay", DV_DULL
+};
+
+struct wsdisplay_accessops omdisplay_accessops = {
+	omdisplay_ioctl,
+	omdisplay_mmap,
+	omdisplay_alloc_screen,
+	omdisplay_free_screen,
+	omdisplay_show_screen,
+	NULL,	/* load font */
+	NULL,	/* scrollback */
+	NULL,	/* getchar */
+	omdisplay_burner
+
+};
+
+struct omdisplay_wsscreen_descr {
+	struct wsscreen_descr  c;       /* standard descriptor */
+	int depth;                      /* bits per pixel */
+	int flags;                      /* rasops flags */
+};
+
+struct omdisplay_wsscreen_descr omdisplay_screen = {
+	{
+		"std"
+	},
+	16,			/* bits per pixel */
+	0 /* rotate */
+};
+
+const struct wsscreen_descr *omdisplay_scr_descr[] = {
+	&omdisplay_screen.c
+};
+
+/* XXX - what about flip phones with CLI */
+const struct wsscreen_list omdisplay_screen_list = {
+        sizeof omdisplay_scr_descr / sizeof omdisplay_scr_descr[0],
+	omdisplay_scr_descr
+};
+
+
+int
+omdisplay_match(struct device *parent, void *v, void *aux)
+{
+	/* XXX */
+	return (1);
+}
+
+void
+omdisplay_attach(struct device *parent, struct device *self, void *args)
+{
+	struct ahb_attach_args *aa = args;
+	struct omdisplay_softc *sc = (struct omdisplay_softc *) self;
+	struct wsemuldisplaydev_attach_args wsaa;
+
+
+	sc->sc_iot = aa->aa_iot;
+
+	if (bus_space_map(sc->sc_iot, aa->aa_addr, OMDISPLAY_SIZE, 0,
+	    &sc->sc_dsioh))
+		panic("omdisplay_attach: bus_space_map failed!");
+
+	if (bus_space_subregion(sc->sc_iot, sc->sc_dsioh, 0x400, 1024,
+	    &sc->sc_dcioh))
+		panic("omdisplay_attach: bus_space_submap failed!");
+
+	if (bus_space_subregion(sc->sc_iot, sc->sc_dsioh, 0x800, 1024,
+	    &sc->sc_rfbioh))
+		panic("omdisplay_attach: bus_space_submap failed!");
+
+	if (bus_space_subregion(sc->sc_iot, sc->sc_dsioh, 0xc00, 1024,
+	    &sc->sc_venioh))
+		panic("omdisplay_attach: bus_space_submap failed!");
+
+
+	sc->sc_nscreens = 0;
+	LIST_INIT(&sc->sc_screens);
+
+	sc->sc_dma_tag = aa->aa_dmat;
+
+	sc->sc_ih = intc_intr_establish(aa->aa_intr, IPL_BIO /* XXX */,
+	    omdisplay_intr, sc, sc->sc_dev.dv_xname);
+
+	printf ("\n");
+
+	sc->sc_geometry = &default_panel;
+
+	{
+		/* XXX - dummy? */
+		struct rasops_info dummy;
+
+		omdisplay_initialize(sc, sc->sc_geometry);
+
+		/*
+		 * Initialize a dummy rasops_info to compute fontsize and
+		 * the screen size in chars.
+		 */
+		bzero(&dummy, sizeof(dummy));
+		omdisplay_setup_rasops(sc, &dummy);
+	}
+
+	wsaa.console = 0;
+	wsaa.scrdata = &omdisplay_screen_list;
+	wsaa.accessops = &omdisplay_accessops;
+	wsaa.accesscookie = sc;
+	wsaa.defaultscreens = 0;
+
+	(void)config_found(self, &wsaa, wsemuldisplaydevprint);
+
+	/* backlight? */
+
+	/* powerhook? */
+	sc->sc_ph = powerhook_establish(omdisplay_power, sc);
+}
+
+
+int
+omdisplay_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
+{
+	struct omdisplay_softc *sc = v;
+	struct wsdisplay_fbinfo *wsdisp_info;
+	struct omdisplay_screen *scr = sc->sc_active;
+	int res = EINVAL;
+
+	switch (cmd) {
+	case WSDISPLAYIO_GETPARAM:
+	case WSDISPLAYIO_SETPARAM:
+		res = omdisplay_param(sc, cmd, (struct wsdisplay_param *)data);
+		break;
+	case WSDISPLAYIO_GTYPE:
+		*(u_int *)data = WSDISPLAY_TYPE_PXALCD; /* XXX */
+		break;
+
+	case WSDISPLAYIO_GINFO:
+		wsdisp_info = (struct wsdisplay_fbinfo *)data;
+
+		wsdisp_info->height = sc->sc_geometry->height;
+		wsdisp_info->width = sc->sc_geometry->width;
+		wsdisp_info->depth = 16; /* XXX */
+		wsdisp_info->cmsize = 0;
+		break;
+		
+	case WSDISPLAYIO_GETCMAP:
+	case WSDISPLAYIO_PUTCMAP:
+		return EINVAL;  /* XXX Colormap */
+
+	case WSDISPLAYIO_SVIDEO:
+	case WSDISPLAYIO_GVIDEO:
+		break;
+
+	case WSDISPLAYIO_GCURPOS:
+	case WSDISPLAYIO_SCURPOS:
+	case WSDISPLAYIO_GCURMAX:
+	case WSDISPLAYIO_GCURSOR:
+	case WSDISPLAYIO_SCURSOR:
+	default:
+		return -1;      /* not implemented */
+
+	case WSDISPLAYIO_LINEBYTES:
+		if (scr != NULL)
+			*(u_int *)data = scr->rinfo.ri_stride;
+		else 
+			*(u_int *)data = 0;
+		break;
+
+	}
+
+	if (res == EINVAL)
+		res = omdisplay_ioctl(v, cmd, data, flag, p);
+
+	return res;
+}
+
+void
+omdisplay_burner(void *v, u_int on, u_int flags)
+{
+
+        omdisplay_set_brightness(on ? omdisplay_get_brightness() : 0);
+
+	/* GPIO controls for appsliver */
+	if (on) {
+		omgpio_set_bit(93);			/* 1 enable backlight */
+		omgpio_set_dir(93, OMGPIO_DIR_OUT);
+		omgpio_clear_bit(26);			/* 0 enable LCD */
+		omgpio_set_dir(26, OMGPIO_DIR_OUT);
+	} else {
+		omgpio_clear_bit(93);			/* 0 disable backlt */
+		omgpio_set_dir(93, OMGPIO_DIR_OUT);
+		omgpio_set_bit(26);			/* 1 disable LCD */
+		omgpio_set_dir(26, OMGPIO_DIR_OUT);
+	}
+}
+
+int
+omdisplay_show_screen(void *v, void *cookie, int waitok,
+    void (*cb)(void *, int, int), void *cbarg)  
+{
+	struct omdisplay_softc *sc = v;
+	struct rasops_info *ri = cookie;
+	struct omdisplay_screen *scr = ri->ri_hw, *old;
+
+	old = sc->sc_active;
+	if (old == scr)
+		return 0;
+  
+	if (old != NULL)
+		; /* Stop old screen */
+
+	sc->sc_active = scr;
+	omdisplay_initialize(sc, sc->sc_geometry);
+	
+	/* Turn on LCD */
+	omdisplay_burner(v, 1, 0);
+
+	return (0);
+}
+
+
+
+/*
+ * wsdisplay I/O controls
+ */
+int
+omdisplay_param(struct omdisplay_softc *sc, ulong cmd,
+    struct wsdisplay_param *dp)
+{
+	int res = EINVAL;
+
+	switch (dp->param) {
+	case WSDISPLAYIO_PARAM_BACKLIGHT:
+		if (cmd == WSDISPLAYIO_GETPARAM) {
+			dp->min = 0;
+			dp->max = 1;
+			dp->curval = omdisplay_get_backlight();
+			res = 0;
+		} else if (cmd == WSDISPLAYIO_SETPARAM) {
+/* XXX */
+//			omdisplay_set_backlight(dp->curval);
+			res = 0;
+		}
+		break;
+
+	case WSDISPLAYIO_PARAM_CONTRAST:
+		/* unsupported */
+		res = ENOTTY;
+		break;
+
+	case WSDISPLAYIO_PARAM_BRIGHTNESS:
+		if (cmd == WSDISPLAYIO_GETPARAM) {
+			dp->min = 1;
+			dp->max = omdisplay_max_brightness();
+			dp->curval = omdisplay_get_brightness();
+			res = 0;
+		} else if (cmd == WSDISPLAYIO_SETPARAM) {
+/* XXX */
+//			omdisplay_set_brightness(dp->curval);
+			res = 0;
+		}
+		break;
+	}
+
+	return res;
+}
+
+
+/*
+ * LCD backlight
+ */
+
+static  int lcdbrightnesscurval = 1;
+static  int lcdislit = 1;
+static  int lcdisblank = 0;
+
+struct lcd_backlight {
+	int	duty;		/* LZ9JG18 DAC value */
+	int	cont;		/* BACKLIGHT_CONT signal */
+	int	on;		/* BACKLIGHT_ON signal */
+};
+
+const struct lcd_backlight lcd_bl[] = {
+	{ 0x00, 0, 0 },		/* 0:     Off */
+	{ 0x00, 0, 1 },		/* 1:      0% */
+	{ 0x01, 0, 1 },		/* 2:     20% */
+	{ 0x07, 0, 1 },		/* 3:     40% */
+	{ 0x01, 1, 1 },		/* 4:     60% */
+	{ 0x07, 1, 1 },		/* 5:     80% */
+	{ 0x11, 1, 1 },		/* 6:    100% */
+	{ -1, -1, -1 }		/* 7: Invalid */
+};
+#define CURRENT_BACKLIGHT lcd_bl
+
+int
+omdisplay_max_brightness(void)
+{
+	int i;
+
+	for (i = 0; CURRENT_BACKLIGHT[i].duty != -1; i++)
+		;
+	return i - 1;
+}
+
+int
+omdisplay_get_brightness(void)
+{
+
+	return lcdbrightnesscurval;
+}
+
+void
+omdisplay_set_brightness(int newval)
+{
+	int max;
+
+	max = omdisplay_max_brightness();
+	if (newval < 0)
+		newval = 0;
+	else if (newval > max)
+		newval = max;
+
+	if (omdisplay_get_backlight() && !lcdisblank)
+		omdisplay_set_brightness_internal(newval);
+
+	if (newval > 0)
+		lcdbrightnesscurval = newval;
+}
+
+void
+omdisplay_set_brightness_internal(int newval)
+{
+	static int curval = 1;
+	int i;
+
+	/*
+	 * It appears that the C3000 backlight can draw too much power if we
+	 * switch it from a low to a high brightness.  Increasing brightness
+	 * in steps avoids this issue.
+	 */
+	if (newval > curval) {
+		for (i = curval + 1; i <= newval; i++) {
+/* atlas controls */
+			/* CURRENT_BACKLIGHT[newval].duty); */
+		}
+	} else {
+/* atlas controls */
+		/* CURRENT_BACKLIGHT[newval].duty); */
+	}
+
+	curval = newval;
+}
+
+int
+omdisplay_get_backlight(void)
+{
+
+	return lcdislit;
+}
+
+void
+omdisplay_set_backlight(int on)
+{
+
+	if (!on) {
+		omdisplay_set_brightness(0);
+		lcdislit = 0;
+	} else {
+		lcdislit = 1;
+		omdisplay_set_brightness(omdisplay_get_brightness());
+	}
+}
+   
+void
+omdisplay_blank(int blank)
+{
+		
+	if (blank) {
+		omdisplay_set_brightness(0);
+		lcdisblank = 1;
+	} else {
+		lcdisblank = 0;
+		omdisplay_set_brightness(omdisplay_get_brightness());
+	}
+}
+
+void
+omdisplay_suspend(struct omdisplay_softc *sc)
+{
+	if (sc->sc_active != NULL) {
+		omdisplay_stop(sc);
+		/* XXX disable clocks */
+	}
+}
+
+void
+omdisplay_resume(struct omdisplay_softc *sc)
+{
+	if (sc->sc_active != NULL) {
+		/* XXX - clocks? */
+		omdisplay_initialize(sc, sc->sc_geometry);
+		omdisplay_start(sc);
+	}
+}
+
+void
+omdisplay_power(int why, void *v)
+{
+	struct omdisplay_softc *sc = v;
+
+        switch (why) {
+        case PWR_SUSPEND:
+        case PWR_STANDBY:
+                omdisplay_set_brightness(0);
+		omdisplay_suspend(sc);
+                break;
+
+        case PWR_RESUME:
+		omdisplay_resume(sc);
+                omdisplay_set_brightness(omdisplay_get_brightness());
+                break;
+        }
+}
+
+
+
+void
+omdisplay_initialize(struct omdisplay_softc *sc,
+    struct omdisplay_panel_data *geom)
+{
+	struct omdisplay_screen *scr;
+	u_int32_t reg;
+	u_int32_t mode;
+#if 0
+	int den, nom; /* pixel rate */
+#endif
+
+
+	reg = bus_space_read_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL);
+
+	scr = sc->sc_active;
+
+	if (reg & (DISPC_CONTROL_LCDENABLE|DISPC_CONTROL_DIGITALENABLE)) {
+		omdisplay_stop(sc);
+	}
+
+	/* XXX - enable clocks */
+
+	/* disable all interrupts */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_IRQENABLE, 0);
+
+	/* GPIOs ? */
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONFIG,
+	    DISPC_CONFIG_LOADMODE_PG|DISPC_CONFIG_LOADMODE_DATA);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DEFAULT_COLOR0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DEFAULT_COLOR1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TRANS_COLOR0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TRANS_COLOR1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_LINE_NUMBER, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DATA_CYCLE1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DATA_CYCLE2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DATA_CYCLE3, 0);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_SYSCONFIG,
+	    DISPC_SYSCONFIG_SIDLEMODE_NONE|
+	    DISPC_SYSCONFIG_MIDLEMODE_NONE);
+		
+#if 0
+	if (geom->panel_flags & LCDPANEL_TDM) {
+		nom = tdmflags >>8 & 0x3;
+		den = tdmflags & 0x3;
+	} else {
+		nom = 1;
+		den = 1;
+	}
+	hsync = geom->width*den/nom + geom->horiz_sync_width +
+	    geom->horiz_front_porch + geom->horiz_back_porch;
+#endif
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TIMING_H,
+	    DISPC_TIMING_H_HSW_s(geom->horiz_sync_width) |
+	    DISPC_TIMING_H_HFP_s(geom->horiz_front_porch) |
+	    DISPC_TIMING_H_HBP_s(geom->horiz_back_porch));
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TIMING_V,
+	    DISPC_TIMING_V_VSW_s(geom->vert_sync_width) |
+	    DISPC_TIMING_V_VFP_s(geom->vert_front_porch) |
+	    DISPC_TIMING_V_VBP_s(geom->vert_back_porch));
+
+	reg = 0;
+	if (geom->sync & PANEL_SYNC_H_ACTIVE_HIGH)
+		reg |= DISPC_POL_FREQ_IHS;
+	if (geom->sync & PANEL_SYNC_V_ACTIVE_HIGH)
+		reg |= DISPC_POL_FREQ_IVS;
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_POL_FREQ, reg);
+
+	
+	/* clkdiv = pixclock/period; */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_SIZE_LCD,
+	    DISPC_SIZE_LCD_PPL_s(geom->width-1) |
+	    DISPC_SIZE_LCD_LPP_s(geom->height-1));
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_SIZE_DIG,
+	    DISPC_SIZE_LCD_PPL_s(geom->width-1) |
+	    DISPC_SIZE_LCD_LPP_s(geom->height-1));
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_SIZE,
+		DISPC_GFX_SIZE_X_s(geom->width-1) |
+		DISPC_GFX_SIZE_Y_s(geom->height-1));
+
+
+	/* XXX!!! */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DIVISOR,
+		DISPC_DIVISOR_LCD_s(1) | DISPC_DIVISOR_PCD_s(6));
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_BA0,
+	    scr->segs[0].ds_addr);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_BA1,
+	    scr->segs[0].ds_addr);
+
+	/* non-rotated */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_PIXEL_INC, 1);
+
+
+	/* XXX 24bit -> 32 pixels */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_ROW_INC,
+	    1 + scr->rinfo.ri_stride -
+	    (scr->rinfo.ri_width * scr->rinfo.ri_depth / 8));
+
+	switch (geom->depth) {
+	case 1:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_1;
+		break;
+	case 2:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_2;
+		break;
+	case 4:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_4;
+		break;
+	case 8:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_8;
+		break;
+	case 12:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_12;
+		break;
+	case 16:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_16;
+		break;
+	case 24:
+		mode = DISPC_GFX_ATTRIBUTES_GFXFMT_24;
+		break;
+	default:
+		panic("invalid depth %d\n", geom->depth);
+	}
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_ATTRIBUTES,
+	    DISPC_GFX_ATTRIBUTES_GFXENABLE | mode |
+	    DISPC_GFX_ATTRIBUTES_BURST_8);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_POSITION, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_WINDOW_SKIP, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_FIFO_THRESHOLD,
+	    (0xfc << DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT) |
+	    (0xc0 << DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT));
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_ROW_INC, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_PIXEL_INC, 1);
+
+	/* DISPC_CONFIG_PALETTEGAMMA not enabled */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_TABLE_BA,
+	    scr->segs[0].ds_addr);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_BA0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_BA1, 0); 
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_SIZE, 0); 
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ATTRIBUTES, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIFO_THRESHOLD,
+	    0xc00040); /* XXX */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIFO_SIZE_STATUS,
+	    0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ROW_INC, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_PIXEL_INC, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_PICTURE_SIZE, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ACCU0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ACCU1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H3, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H4, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H5, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H6, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H7, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV3, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV4, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV5, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV6, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV7, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF3, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF4, 0);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_BA0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_BA1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_SIZE, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ATTRIBUTES, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIFO_THRESHOLD,
+	    0xc00040); /* XXX */
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIFO_SIZE_STATUS,
+	    0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ROW_INC, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_PIXEL_INC, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_PICTURE_SIZE, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ACCU0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ACCU1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H3, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H4, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H5, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H6, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H7, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV3, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV4, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV5, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV6, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV7, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF0, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF1, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF2, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF3, 0);
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF4, 0); 
+
+	omdisplay_start(sc);
+}
+
+void
+omdisplay_setup_rasops(struct omdisplay_softc *sc, struct rasops_info *rinfo)
+{
+	struct omdisplay_wsscreen_descr *descr;
+	struct omdisplay_panel_data *geom;
+
+	descr = &omdisplay_screen;
+	geom = sc->sc_geometry;
+
+	rinfo->ri_flg = descr->flags;
+	rinfo->ri_depth = descr->depth;
+	rinfo->ri_width = geom->width;
+	rinfo->ri_height = geom->height;
+	rinfo->ri_stride = geom->linebytes;
+
+	/* pixel position */
+	if (descr->depth == 16) {
+		rinfo->ri_rnum = 5;
+		rinfo->ri_rpos = 11;
+		rinfo->ri_gnum = 6;
+		rinfo->ri_gpos = 5;
+		rinfo->ri_bnum = 5;
+		rinfo->ri_bpos = 0;
+	}
+
+	if (descr->c.nrows == 0) {
+		/* get rasops to compute screen size the first time */
+		rasops_init(rinfo, 100, 100);
+	} else {
+		if (descr->flags != 0) /* rotate */
+			rasops_init(rinfo, descr->c.ncols, descr->c.nrows);
+		else
+			rasops_init(rinfo, descr->c.nrows, descr->c.ncols);
+	}
+
+	descr->c.nrows = rinfo->ri_rows;
+	descr->c.ncols = rinfo->ri_cols;
+	descr->c.capabilities = rinfo->ri_caps;
+	descr->c.textops = &rinfo->ri_ops;
+
+}
+
+
+int
+omdisplay_alloc_screen(void *v, const struct wsscreen_descr *_type,
+    void **cookiep, int *curxp, int *curyp, long *attrp)
+{
+	struct omdisplay_softc *sc = v;
+	struct omdisplay_screen *scr;
+	struct rasops_info *ri;
+	struct omdisplay_wsscreen_descr *type =
+	    (struct omdisplay_wsscreen_descr *)_type;
+	int error;
+
+	scr = malloc(sizeof *scr, M_DEVBUF, (cold ? M_NOWAIT : M_WAITOK));
+	if (scr == NULL)
+		return (ENOMEM);
+
+	error = omdisplay_new_screen(sc, scr, type->depth);
+	if (error != 0) {
+		free(scr, M_DEVBUF);
+		return (error);
+	}
+
+	/*
+	 * initialize raster operation for this screen.
+	 */
+	ri = &scr->rinfo;
+	ri->ri_hw = (void *)scr;
+	ri->ri_bits = scr->buf_va;
+	omdisplay_setup_rasops(sc, ri);
+
+	/* assumes 16 bpp */
+	ri->ri_ops.alloc_attr(ri, 0, 0, 0, attrp);
+
+	*cookiep = ri;
+	*curxp = 0;
+	*curyp = 0;
+
+	return 0;
+}
+
+/*
+ * Create and initialize a new screen buffer.
+ */
+int
+omdisplay_new_screen(struct omdisplay_softc *sc,
+    struct omdisplay_screen *scr, int depth)
+{
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	bus_dma_tag_t dma_tag;
+	struct omdisplay_panel_data *geometry;
+	int width, height;
+	bus_size_t size;
+	int error, palette_size;
+	int busdma_flag = (cold ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
+
+	if (sc != NULL) {
+		iot = sc->sc_iot;
+		ioh = sc->sc_dcioh;
+		dma_tag = sc->sc_dma_tag;
+		geometry = sc->sc_geometry;
+	} else {
+		/* We are creating the console screen. */
+#if 0
+		iot = omdisplay_console.iot;
+		ioh = omdisplay_console.ioh;
+		dma_tag = omdisplay_console.dma_tag;
+		geometry = omdisplay_console.geometry;
+#endif
+	}
+
+	width = geometry->width;
+	height = geometry->height;
+	palette_size = 0;
+
+	switch (depth) {
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		palette_size = (1 << depth) * sizeof (uint16_t);
+		/* FALLTHROUGH */
+	case 16:
+	case 24:
+		size = geometry->height * geometry->linebytes;
+		break;
+	default:
+		printf("%s: Unknown depth (%d)\n",
+		    sc != NULL ? sc->sc_dev.dv_xname : "console", depth);
+		return (EINVAL);
+	}
+
+	bzero(scr, sizeof *scr);
+
+	scr->nsegs = 0;
+	scr->depth = depth;
+	scr->buf_size = size;
+	scr->buf_va = NULL;
+	size = roundup(size, 16);
+#if 0
+	 + 3 * sizeof (struct lcd_dma_descriptor)
+	    + palette_size;
+#endif
+
+	error = bus_dmamem_alloc(dma_tag, size, 0x100000, 0,
+	    scr->segs, 1, &(scr->nsegs), busdma_flag);
+	if (error != 0 || scr->nsegs != 1) {
+		/* XXX: Actually we can handle nsegs > 1 case by means
+		   of multiple DMA descriptors for a panel.  It would
+		    make code here a bit hairy */
+		if (error == 0)
+			error = E2BIG;
+		goto bad;
+	}
+
+	error = bus_dmamem_map(dma_tag, scr->segs, scr->nsegs,
+	    size, (caddr_t *)&(scr->buf_va), busdma_flag | BUS_DMA_COHERENT);
+	if (error != 0)
+		goto bad;
+
+	memset(scr->buf_va, 0, scr->buf_size);
+	bcopy(splash, scr->buf_va,
+	    sizeof (splash) > scr->buf_size ? scr->buf_size : sizeof (splash));
+
+	/* map memory for DMA */
+	if (bus_dmamap_create(dma_tag, 1024 * 1024 * 2, 1, 
+	    1024 * 1024 * 2, 0,  busdma_flag, &scr->dma))
+		goto bad;
+	error = bus_dmamap_load(dma_tag, scr->dma,
+	    scr->buf_va, size, NULL, busdma_flag);
+	if (error != 0) {
+		goto bad;
+	}
+
+	scr->map_size = size;		/* used when unmap this. */
+
+	if (sc != NULL) {
+		LIST_INSERT_HEAD(&(sc->sc_screens), scr, link);
+		sc->sc_nscreens++;
+	}
+
+	omdisplay_initialize(sc, geometry);
+	
+	return (0);
+
+ bad:
+	if (scr->buf_va)
+		bus_dmamem_unmap(dma_tag, scr->buf_va, size);
+	if (scr->nsegs)
+		bus_dmamem_free(dma_tag, scr->segs, scr->nsegs);
+	return (error);
+}
+paddr_t
+omdisplay_mmap(void *v, off_t offset, int prot)
+{
+	struct omdisplay_softc *sc = v;
+	struct omdisplay_screen *screen = sc->sc_active;  /* ??? */
+
+	if ((offset & PAGE_MASK) != 0)
+		return (-1);
+
+	if (screen == NULL)
+		return (-1);
+
+	if (offset < 0 ||
+	    offset >= screen->rinfo.ri_stride * screen->rinfo.ri_height)
+		return (-1);
+
+	return (bus_dmamem_mmap(sc->sc_dma_tag, screen->segs, screen->nsegs,
+	    offset, prot, BUS_DMA_WAITOK | BUS_DMA_COHERENT));
+}
+
+void
+omdisplay_free_screen(void *v, void *cookie)
+{
+	struct omdisplay_softc *sc = v;
+	struct rasops_info *ri = cookie;
+	struct omdisplay_screen *scr = ri->ri_hw;
+
+	LIST_REMOVE(scr, link);
+	sc->sc_nscreens--;
+	if (scr == sc->sc_active) {
+		/* at first, we need to stop LCD DMA */
+		sc->sc_active = NULL;
+
+#ifdef DEBUG
+		printf("lcd_free on active screen\n");
+#endif
+
+		omdisplay_stop(sc);
+	}
+
+	if (scr->buf_va)
+		bus_dmamem_unmap(sc->sc_dma_tag, scr->buf_va, scr->map_size);
+
+	if (scr->nsegs > 0)
+		bus_dmamem_free(sc->sc_dma_tag, scr->segs, scr->nsegs);
+
+	free(scr, M_DEVBUF);
+}
+
+void
+omdisplay_start(struct omdisplay_softc *sc)
+{
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL,
+	    DISPC_CONTROL_GPOUT0 | DISPC_CONTROL_GPOUT1 |
+	    DISPC_CONTROL_TFTDATALINES_18 /*XXX 18? */ |
+	    DISPC_CONTROL_STNTFT |
+	    DISPC_CONTROL_GOLCD |
+	    DISPC_CONTROL_LCDENABLE);
+}
+
+void
+omdisplay_stop(struct omdisplay_softc *sc)
+{
+	bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL,
+	    bus_space_read_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL) &
+	    ~(DISPC_CONTROL_DIGITALENABLE|DISPC_CONTROL_LCDENABLE));
+
+	/* XXX - wait for end of frame? */
+}
+
+int
+omdisplay_intr(void *v)
+{
+	/* XXX */
+	return 1;
+}
+
diff --git a/sys/arch/beagle/dev/omdog.c b/sys/arch/beagle/dev/omdog.c
new file mode 100644
index 00000000000..283829eb4f2
--- /dev/null
+++ b/sys/arch/beagle/dev/omdog.c
@@ -0,0 +1,118 @@
+/* $OpenBSD: omdog.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+#include <sys/evcount.h>
+#include <sys/socket.h>
+#include <sys/timeout.h>
+#include <machine/intr.h>
+#include <machine/bus.h>
+#include <arch/beagle/beagle/ahb.h>
+#include <arch/beagle/dev/omgpiovar.h>
+
+/* registers */
+#define WIDR		0x00
+#define WD_SYSCONFIG	0x10
+#define WD_SYSSTATUS	0x14
+#define WISR		0x18
+#define WIER		0x1C
+#define WCLR		0x24
+#define WCRR		0x28
+#define WLDR		0x2C
+#define WTGR		0x30
+#define WWPS		0x34
+#define		WWPS_PEND_ALL	0x1f
+#define WSPR		0x48
+#define WD_SIZE		0x80
+
+
+struct omdog_softc {
+	struct device		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+};
+
+struct omdog_softc *omdog_sc;
+
+/* 
+ * to enable  the watchdog, write 0xXXXXbbbb then 0xXXXX4444 to WSPR
+ * to disable the watchdog, write 0xXXXXaaaa then 0xXXXX5555 to WSPR
+ */
+
+
+int omdog_match(struct device *parent, void *v, void *aux);
+void omdog_attach(struct device *parent, struct device *self, void *args);
+void omdog_wpending(int flags);
+
+struct cfattach	omdog_ca = {
+	sizeof (struct omdog_softc), omdog_match, omdog_attach
+};
+
+struct cfdriver omdog_cd = {
+	NULL, "omdog", DV_DULL
+};
+
+int
+omdog_match(struct device *parent, void *v, void *aux)
+{
+	return (1);
+}
+
+void
+omdog_attach(struct device *parent, struct device *self, void *args)
+{
+        struct ahb_attach_args *aa = args;
+	struct omdog_softc *sc = (struct omdog_softc *) self;
+	u_int32_t rev;
+
+	sc->sc_iot = aa->aa_iot;
+	if (bus_space_map(sc->sc_iot, aa->aa_addr, WD_SIZE, 0, &sc->sc_ioh))
+		panic("gptimer_attach: bus_space_map failed!");
+
+	rev = bus_space_read_4(sc->sc_iot, sc->sc_ioh, WIDR);
+
+	printf(" rev %d.%d\n", rev >> 4 & 0xf, rev & 0xf);
+	omdog_sc = sc;
+}
+
+void
+omdog_wpending(int flags)
+{
+	struct omdog_softc *sc = omdog_sc;
+	while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, WWPS) & flags)
+		;
+}
+
+void omdog_reset(void); 	/* XXX */
+
+void
+omdog_reset()
+{
+	bus_space_write_4(omdog_sc->sc_iot, omdog_sc->sc_ioh, WCRR, 0xffffff80);
+	omdog_wpending(WWPS_PEND_ALL);
+
+	/* this sequence will start the watchdog. */
+	bus_space_write_4(omdog_sc->sc_iot, omdog_sc->sc_ioh, WSPR, 0xbbbb);
+	omdog_wpending(WWPS_PEND_ALL);
+	bus_space_write_4(omdog_sc->sc_iot, omdog_sc->sc_ioh, WSPR, 0x4444);
+	omdog_wpending(WWPS_PEND_ALL);
+	delay(100000);
+}
diff --git a/sys/arch/beagle/dev/omgpio.c b/sys/arch/beagle/dev/omgpio.c
new file mode 100644
index 00000000000..82a071a6b09
--- /dev/null
+++ b/sys/arch/beagle/dev/omgpio.c
@@ -0,0 +1,457 @@
+/* $OpenBSD: omgpio.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/queue.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/evcount.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <arch/beagle/beagle/ahb.h>
+#include <arch/beagle/dev/omgpiovar.h>
+#include "omgpio.h"
+
+
+/* registers */
+#define	GPIO_REVISION		0x00
+#define	GPIO_SYSCONFIG		0x10
+#define	GPIO_SYSSTATUS		0x14
+#define	GPIO_IRQSTATUS1		0x18
+#define	GPIO_IRQENABLE1		0x1C
+#define	GPIO_WAKEUPENABLE	0x20
+#define	GPIO_IRQSTATUS2		0x28
+#define	GPIO_IRQENABLE2		0x2C
+#define	GPIO_CTRL		0x30
+#define	GPIO_OE			0x34
+#define	GPIO_DATAIN		0x38
+#define	GPIO_DATAOUT		0x3C
+#define	GPIO_LEVELDETECT0	0x40
+#define	GPIO_LEVELDETECT1	0x44
+#define	GPIO_RISINGDETECT	0x48
+#define	GPIO_FALLINGDETECT	0x4C
+#define	GPIO_DEBOUNCENABLE	0x50
+#define	GPIO_DEBOUNCINGTIME	0x54
+#define	GPIO_CLEARIRQENABLE1	0x60
+#define	GPIO_SETIRQENABLE1	0x64
+#define	GPIO_CLEARIRQENABLE2	0x70
+#define	GPIO_SETIRQENABLE2	0x74
+#define	GPIO_CLEARWKUENA	0x80
+#define	GPIO_SETWKUENA		0x84
+#define	GPIO_CLEARDATAOUT	0x90
+#define	GPIO_SETDATAOUT		0x94
+#define	GPIO_SIZE		0x100
+
+
+#define GPIO_NUM_PINS		32
+
+struct intrhand {
+	int (*ih_func)(void *);		/* handler */
+	void *ih_arg;			/* arg for handler */
+	int ih_ipl;			/* IPL_* */
+	int ih_irq;			/* IRQ number */
+	int ih_gpio;			/* gpio pin */
+	struct evcount	ih_count;
+	char *ih_name;
+};
+
+struct omgpio_softc {
+	struct device		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	void			*sc_ih_h;
+	void			*sc_ih_l;
+	int 			sc_max_il;
+	int 			sc_min_il;
+	int			sc_irq;
+	struct intrhand		*sc_handlers[GPIO_NUM_PINS];
+};
+
+#define GPIO_PIN_TO_INST(x)	((x) >> 5)
+#define GPIO_PIN_TO_OFFSET(x)	((x) & 0x1f)
+
+int omgpio_match(struct device *parent, void *v, void *aux);
+void omgpio_attach(struct device *parent, struct device *self, void *args);
+void omgpio_recalc_interrupts(struct omgpio_softc *sc);
+int omgpio_irq(void *);
+int omgpio_irq_dummy(void *);
+
+struct cfattach	omgpio_ca = {
+	sizeof (struct omgpio_softc), omgpio_match, omgpio_attach
+};
+
+struct cfdriver omgpio_cd = {
+	NULL, "omgpio", DV_DULL
+};
+
+int
+omgpio_match(struct device *parent, void *v, void *aux)
+{
+	return (1);
+}
+
+void
+omgpio_attach(struct device *parent, struct device *self, void *args)
+{
+        struct ahb_attach_args *aa = args;
+	struct omgpio_softc *sc = (struct omgpio_softc *) self;
+	u_int32_t rev;
+
+	sc->sc_iot = aa->aa_iot;
+	if (bus_space_map(sc->sc_iot, aa->aa_addr, GPIO_SIZE, 0, &sc->sc_ioh))
+		panic("omgpio_attach: bus_space_map failed!");
+
+	rev = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_REVISION);
+
+	printf(" rev %d.%d\n", rev >> 4 & 0xf, rev & 0xf);
+
+	sc->sc_irq = aa->aa_intr;
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_CLEARIRQENABLE1, ~0);
+
+	/* XXX - SYSCONFIG */
+	/* XXX - CTRL */
+	/* XXX - DEBOUNCE */
+}
+
+/* XXX - This assumes MCU INTERRUPTS are IRQ1, and DSP are IRQ2 */
+
+#if 0
+/* XXX - FIND THESE REGISTERS !!! */
+unsigned int
+omgpio_get_function(unsigned int gpio, unsigned int fn)
+{
+	return 0;
+}
+
+void
+omgpio_set_function(unsigned int gpio, unsigned int fn)
+{
+}
+#endif
+
+/*
+ * get_bit() is not reliable if used on an output pin.
+ */
+
+unsigned int
+omgpio_get_bit(unsigned int gpio)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	u_int32_t reg;
+	
+	reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DATAIN);
+	return (reg >> GPIO_PIN_TO_OFFSET(gpio)) & 0x1;
+}
+
+void
+omgpio_set_bit(unsigned int gpio)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_SETDATAOUT,
+	    1 << GPIO_PIN_TO_OFFSET(gpio));
+}
+
+void
+omgpio_clear_bit(unsigned int gpio)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_CLEARDATAOUT,
+	    1 << GPIO_PIN_TO_OFFSET(gpio));
+}
+
+void
+omgpio_set_dir(unsigned int gpio, unsigned int dir)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	int s;
+	u_int32_t reg;
+
+	s = splhigh();
+
+	reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DATAIN);
+	if (dir == OMGPIO_DIR_IN)
+		reg |= 1 << GPIO_PIN_TO_OFFSET(gpio);
+	else
+		reg &= ~(1 << GPIO_PIN_TO_OFFSET(gpio));
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_OE, reg);
+
+	splx(s);
+}
+
+void
+omgpio_clear_intr(unsigned int gpio)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_IRQSTATUS1,
+	    1 << GPIO_PIN_TO_OFFSET(gpio));
+}
+
+void
+omgpio_intr_mask(unsigned int gpio)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_CLEARIRQENABLE1,
+	    1 << GPIO_PIN_TO_OFFSET(gpio));
+}
+
+void
+omgpio_intr_unmask(unsigned int gpio)
+{
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_SETIRQENABLE1,
+	    1 << GPIO_PIN_TO_OFFSET(gpio));
+}
+
+void
+omgpio_intr_level(unsigned int gpio, unsigned int level)
+{
+	u_int32_t fe, re, l0, l1, bit;
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+	int s;
+
+	s = splhigh();
+
+	fe = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_FALLINGDETECT);
+	re = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_RISINGDETECT);
+	l0 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT0);
+	l1 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT1);
+	
+	bit = 1 << GPIO_PIN_TO_OFFSET(gpio);
+
+        switch (level) {
+        case IST_NONE:
+		fe &= ~bit;
+		re &= ~bit;
+		l0 &= ~bit;
+		l1 &= ~bit;
+		break;
+        case IST_EDGE_FALLING:
+		fe |= bit;
+		re &= ~bit;
+		l0 &= ~bit;
+		l1 &= ~bit;
+		break;
+        case IST_EDGE_RISING:
+		fe &= ~bit;
+		re |= bit;
+		l0 &= ~bit;
+		l1 &= ~bit;
+		break;
+	case IST_PULSE: /* XXX */
+		/* FALLTHRU */
+        case IST_EDGE_BOTH:
+		fe |= bit;
+		re |= bit;
+		l0 &= ~bit;
+		l1 &= ~bit;
+                break;
+	case IST_LEVEL_LOW:
+		fe &= ~bit;
+		re &= ~bit;
+		l0 |= bit;
+		l1 &= ~bit;
+                break;
+	case IST_LEVEL_HIGH:
+		fe &= ~bit;
+		re &= ~bit;
+		l0 &= ~bit;
+		l1 |= bit;
+                break;
+		break;
+        default:
+                panic("omgpio_intr_level: bad level: %d", level);
+                break;
+        }
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_FALLINGDETECT, fe);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_RISINGDETECT, re);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT0, l0);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT1, l1);
+
+	splx(s);
+}
+
+void *
+omgpio_intr_establish(unsigned int gpio, int level, int spl,
+    int (*func)(void *), void *arg, char *name)
+{
+	int psw;
+	struct intrhand *ih;
+	struct omgpio_softc *sc;
+
+	/*
+	 * XXX - is gpio here the pin or the interrupt number
+	 * which is 96 + gpio pin?
+	 */
+
+	if (GPIO_PIN_TO_INST(gpio) > NOMGPIO)
+		panic("omgpio_intr_establish: bogus irqnumber %d: %s\n",
+		     gpio, name);
+
+	sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
+
+	if (sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] != NULL)
+		panic("omgpio_intr_establish: gpio pin busy %d old %s new %s\n",
+		    gpio, sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)]->ih_name,
+		    name);
+
+	psw = disable_interrupts(I32_bit);
+
+	/* no point in sleeping unless someone can free memory. */
+	ih = (struct intrhand *)malloc( sizeof *ih, M_DEVBUF,
+	    cold ? M_NOWAIT : M_WAITOK);
+	if (ih == NULL)
+		panic("intr_establish: can't malloc handler info");
+	ih->ih_func = func;
+	ih->ih_arg = arg;
+	ih->ih_ipl = level;
+	ih->ih_gpio = gpio;
+	ih->ih_irq = gpio + INTC_NUM_IRQ;
+	ih->ih_name = name;
+
+	sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] = ih;
+
+	evcount_attach(&ih->ih_count, name, (void *)&ih->ih_irq, &evcount_intr);
+
+	omgpio_intr_level(gpio, level);
+	omgpio_intr_unmask(gpio);
+
+	omgpio_recalc_interrupts(sc);
+
+	restore_interrupts(psw);
+
+	return (ih);
+}
+
+void
+omgpio_intr_disestablish(void *cookie)
+{
+	int psw;
+	struct intrhand *ih = cookie;
+	struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(ih->ih_gpio)];
+	int gpio = ih->ih_gpio;
+	psw = disable_interrupts(I32_bit);
+
+	ih = sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)];
+	sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] = NULL;
+
+	evcount_detach(&ih->ih_count);
+
+	free(ih, M_DEVBUF);
+
+	omgpio_intr_level(gpio, IST_NONE);
+	omgpio_intr_mask(gpio);
+	omgpio_clear_intr(gpio); /* Just in case */
+
+	omgpio_recalc_interrupts(sc);
+
+	restore_interrupts(psw);
+}
+
+int
+omgpio_irq(void *v)
+{
+	struct omgpio_softc *sc = v;
+	u_int32_t pending;
+	struct intrhand *ih;
+	int bit;
+
+	pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IRQSTATUS1);
+
+	while (pending != 0) {
+		bit = ffs(pending) - 1;
+		ih = sc->sc_handlers[bit];
+
+		if (ih != NULL) {
+			if (ih->ih_func(ih->ih_arg))
+				ih->ih_count.ec_count++;
+			omgpio_clear_intr(ih->ih_gpio);
+		} else {
+			panic("omgpio: irq fired no hander, gpio %x %x %x\n",
+				sc->sc_dev.dv_unit * 32 + bit, pending,
+	bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IRQENABLE1)
+
+				);
+		}
+		pending &= ~(1 << bit);
+	}
+	return 1;
+}
+
+int
+omgpio_irq_dummy(void *v)
+{
+	return 0;
+}
+
+void
+omgpio_recalc_interrupts(struct omgpio_softc *sc)
+{
+	struct intrhand *ih;
+	int max = IPL_NONE;
+	int min = IPL_HIGH;
+	int i;
+
+	for (i = 0; i < GPIO_NUM_PINS; i++) {
+		ih = sc->sc_handlers[i];
+		if (ih != NULL) {
+			if (ih->ih_ipl > max)
+				max = ih->ih_ipl;
+
+			if (ih->ih_ipl < min)
+				min = ih->ih_ipl;
+		}
+	}
+	if (max == IPL_NONE)
+		min = IPL_NONE;
+
+#if 0
+	if ((max == IPL_NONE || max != sc->sc_max_il) && sc->sc_ih_h != NULL)
+		intc_intr_disestablish(sc->sc_ih_h);
+
+	if (max != IPL_NONE && max != sc->sc_max_il) {
+		sc->sc_ih_h = intc_intr_establish(sc->sc_irq, max, omgpio_irq,
+		    sc, NULL);
+	}
+#else
+	if (sc->sc_ih_h != NULL)
+		intc_intr_disestablish(sc->sc_ih_h);
+
+	if (max != IPL_NONE) {
+		sc->sc_ih_h = intc_intr_establish(sc->sc_irq, max, omgpio_irq,
+		    sc, NULL);
+	}
+#endif
+
+	sc->sc_max_il = max;
+
+	if (sc->sc_ih_l != NULL)
+		intc_intr_disestablish(sc->sc_ih_l);
+
+	if (max != min) {
+		sc->sc_ih_h = intc_intr_establish(sc->sc_irq, min,
+		    omgpio_irq_dummy, sc, NULL);
+	}
+	sc->sc_min_il = min;
+}
diff --git a/sys/arch/beagle/dev/omgpiovar.h b/sys/arch/beagle/dev/omgpiovar.h
new file mode 100644
index 00000000000..9fa277b994f
--- /dev/null
+++ b/sys/arch/beagle/dev/omgpiovar.h
@@ -0,0 +1,40 @@
+/* $OpenBSD: omgpiovar.h,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef OMGPIOVAR_H
+#define OMGPIOVAR_H
+
+#define OMGPIO_DIR_IN 	0
+#define OMGPIO_DIR_OUT	1
+
+unsigned int omgpio_get_function(unsigned int gpio, unsigned int fn);
+void omgpio_set_function(unsigned int gpio, unsigned int fn);
+unsigned int omgpio_get_bit(unsigned int gpio);
+void omgpio_set_bit(unsigned int gpio);
+void omgpio_clear_bit(unsigned int gpio);
+void omgpio_set_dir(unsigned int gpio, unsigned int dir);
+
+/* interrupts */
+void omgpio_clear_intr(unsigned int gpio);
+void omgpio_intr_mask(unsigned int gpio);
+void omgpio_intr_unmask(unsigned int gpio);
+void omgpio_intr_level(unsigned int gpio, unsigned int level);
+void *omgpio_intr_establish(unsigned int gpio, int level, int spl,
+    int (*func)(void *), void *arg, char *name);
+void omgpio_intr_disestablish(void *cookie);
+
+#endif /* OMGPIOVAR_H */
diff --git a/sys/arch/beagle/dev/omohci.c b/sys/arch/beagle/dev/omohci.c
new file mode 100644
index 00000000000..f4a88950a3c
--- /dev/null
+++ b/sys/arch/beagle/dev/omohci.c
@@ -0,0 +1,364 @@
+/*	$OpenBSD: omohci.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+
+/*
+ * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/timeout.h>
+
+#include <machine/intr.h>
+#include <machine/bus.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <dev/usb/ohcireg.h>
+#include <dev/usb/ohcivar.h>
+#include <arch/beagle/beagle/ahb.h>
+#include <beagle/dev/prcmvar.h>
+
+#define HOSTUEADDR		0x0E0
+#define HOSTUESTATUS		0x0E4
+#define HOSTTIMEOUTCTRL		0x0E8
+#define HOSTREVISION		0x0EC
+#define WHM_REVID_REGISTER	0x0F4
+#define WHM_TEST_OBSV		0x0F8
+#define WHM_TEST_CTL		0x0FC
+#define HHC_TEST_CFG		0x100
+#define HHC_TEST_CTL		0x104
+#define HHC_TEST_OBSV		0x108
+#define REVDEV			0x200 /* 16 bit */
+#define EP_NUM			0x204 /* 16 bit */
+#define DATA			0x208 /* 16 bit */
+#define CTRL			0x20C /* 16 bit */
+#define STAT_FLG		0x210 /* 16 bit */
+#define RXFSTAT			0x214 /* 16 bit */
+#define SYSCON1			0x218 /* 16 bit */
+#define SYSCON2			0x21C /* 16 bit */
+#define DEVSTAT			0x220 /* 16 bit */
+#define SOFREG			0x224 /* 16 bit */
+#define IRQ_EN			0x228 /* 16 bit */
+#define DMA_IRQ_EN		0x22C /* 16 bit */
+#define IRQ_SRC			0x230 /* 16 bit */
+#define EPN_STAT		0x234 /* 16 bit */
+#define DMAN_STAT		0x238 /* 16 bit */
+#define RXDMA_CFG		0x240 /* 16 bit */
+#define TXDMA_CFG		0x244 /* 16 bit */
+
+#define TXDMA0			0x250
+#define TXDMA1		0x254
+#define TXDMA2		0x258
+#define RXDMA0		0x260
+#define RXDMA1		0x264
+#define RXDMA2		0x268
+
+#define EP0	 	0x280
+#define EP_RX(x)	0x280 + (x * 4)
+#define EP_TX(x)	0x2C0 + (x * 4)
+
+#define OTG_REV		0x300
+#define OTG_SYSCON_1	0x304
+#define OTG_SYSCON_2	0x308
+#define		OTG_SYSCON2_OTG_EN		0x80000000
+#define		OTG_SYSCON2_UHOST_EN		0x00000100
+#define		OTG_SYSCON2_MODE_DISABLED	0x00000000
+#define		OTG_SYSCON2_MODE_CLIENT		0x00000001
+#define		OTG_SYSCON2_MODE_HOST		0x00000004
+#define OTG_CTRL	0x30C
+#if 0
+#define OTG_IRQ_EN	0x310 /* 16 bit */
+#define OTG_IRQ_SRC	0x314 /* 16 bit */
+#define OTG_OUTCTRL	0x318 /* 16 bit */
+#define OTG_TEST	0x320 /* 16 bit */
+#endif
+#define OTG_VC		0x3FC
+
+
+int	omohci_match(struct device *, void *, void *);
+void	omohci_attach(struct device *, struct device *, void *);
+int	omohci_detach(struct device *, int);
+void	omohci_power(int, void *);
+
+struct omohci_softc {
+	ohci_softc_t	sc;
+	void		*sc_ihc0;
+	void		*sc_ihc1;
+	void		*sc_ihc2;
+	void		*sc_ih0;
+	void		*sc_ih1;
+	void		*sc_ihotg;
+};
+
+void	omohci_enable(struct omohci_softc *);
+void	omohci_disable(struct omohci_softc *);
+
+struct cfattach omohci_ca = {
+        sizeof (struct omohci_softc), omohci_match, omohci_attach,
+	omohci_detach, ohci_activate
+};
+
+int
+omohci_match(struct device *parent, void *match, void *aux)
+{
+#if 0
+	if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) != CPU_ID_PXA27X)
+		return (0);
+#endif
+
+	return (1);
+}
+
+void
+omohci_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct omohci_softc	*sc = (struct omohci_softc *)self;
+        struct ahb_attach_args	*aa = aux;
+	usbd_status		r;
+
+	sc->sc.iot = aa->aa_iot;
+	sc->sc.sc_bus.dmatag = aa->aa_dmat;
+	sc->sc_ih0 = NULL;
+	sc->sc_ih1 = NULL;
+	sc->sc_ihc0 = NULL;
+	sc->sc_ihc1 = NULL;
+	sc->sc_ihc2 = NULL;
+	sc->sc_ihotg = NULL;
+	sc->sc.sc_size = 0;
+
+	/* Map I/O space */
+	if (bus_space_map(sc->sc.iot, aa->aa_addr, aa->aa_size, 0,
+	    &sc->sc.ioh)) {
+		printf(": cannot map mem space\n");
+		return;
+	}
+	sc->sc.sc_size = aa->aa_size;
+
+	/* XXX copied from ohci_pci.c. needed? */
+	bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
+	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
+
+#if 0
+	/* start the usb clock */
+	pxa2x0_clkman_config(CKEN_USBHC, 1);
+#endif
+	omohci_enable(sc);
+
+	/* Disable interrupts, so we don't get any spurious ones. */
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
+	    OHCI_MIE);
+
+	sc->sc_ihc0 = intc_intr_establish(aa->aa_intr, IPL_USB,
+	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
+	sc->sc_ihc1 = intc_intr_establish(aa->aa_intr+1, IPL_USB,
+	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
+	sc->sc_ihc2 = intc_intr_establish(aa->aa_intr+2, IPL_USB,
+	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
+	sc->sc_ih0 = intc_intr_establish(aa->aa_intr+3, IPL_USB,
+	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
+	sc->sc_ih1 = intc_intr_establish(aa->aa_intr+4, IPL_USB,
+	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
+	sc->sc_ihotg = intc_intr_establish(aa->aa_intr+5, IPL_USB,
+	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
+	if (sc->sc_ih0 == NULL ||
+	    sc->sc_ih1 == NULL ||
+	    sc->sc_ihc0 == NULL ||
+	    sc->sc_ihc1 == NULL ||
+	    sc->sc_ihc2 == NULL ||
+	    sc->sc_ihotg == NULL) {
+		printf(": unable to establish interrupt\n");
+		omohci_disable(sc);
+#if 0
+		pxa2x0_clkman_config(CKEN_USBHC, 0);
+#endif
+		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
+		sc->sc.sc_size = 0;
+		return;
+	}
+
+	prcm_enableclock(PRCM_CLK_EN_USB);
+
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OTG_SYSCON_2,
+	    OTG_SYSCON2_UHOST_EN | OTG_SYSCON2_MODE_HOST);
+
+	strlcpy(sc->sc.sc_vendor, "OMAP24xx", sizeof(sc->sc.sc_vendor));
+	r = ohci_init(&sc->sc);
+	if (r != USBD_NORMAL_COMPLETION) {
+		printf("%s: init failed, error=%d\n",
+		    sc->sc.sc_bus.bdev.dv_xname, r);
+		intc_intr_disestablish(sc->sc_ih0);
+		intc_intr_disestablish(sc->sc_ih1);
+		intc_intr_disestablish(sc->sc_ihc0);
+		intc_intr_disestablish(sc->sc_ihc1);
+		intc_intr_disestablish(sc->sc_ihc2);
+		intc_intr_disestablish(sc->sc_ihotg);
+		sc->sc_ih0 = NULL;
+		sc->sc_ih1 = NULL;
+		sc->sc_ihc0 = NULL;
+		sc->sc_ihc1 = NULL;
+		sc->sc_ihc2 = NULL;
+		sc->sc_ihotg = NULL;
+		omohci_disable(sc);
+#if 0
+		pxa2x0_clkman_config(CKEN_USBHC, 0);
+#endif
+		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
+		sc->sc.sc_size = 0;
+		return;
+	}
+
+	sc->sc.sc_powerhook = powerhook_establish(omohci_power, sc);
+	if (sc->sc.sc_powerhook == NULL)
+		printf("%s: cannot establish powerhook\n",
+		    sc->sc.sc_bus.bdev.dv_xname);
+
+	sc->sc.sc_child = config_found((void *)sc, &sc->sc.sc_bus,
+	    usbctlprint);
+}
+
+int
+omohci_detach(struct device *self, int flags)
+{
+	struct omohci_softc		*sc = (struct omohci_softc *)self;
+	int				rv;
+
+	rv = ohci_detach(&sc->sc, flags);
+	if (rv)
+		return (rv);
+
+	if (sc->sc.sc_powerhook != NULL) {
+		powerhook_disestablish(sc->sc.sc_powerhook);
+		sc->sc.sc_powerhook = NULL;
+	}
+
+	if (sc->sc_ih0 != NULL) {
+		intc_intr_disestablish(sc->sc_ih0);
+		intc_intr_disestablish(sc->sc_ih1);
+		intc_intr_disestablish(sc->sc_ihc0);
+		intc_intr_disestablish(sc->sc_ihc1);
+		intc_intr_disestablish(sc->sc_ihc2);
+		intc_intr_disestablish(sc->sc_ihotg);
+		sc->sc_ih0 = NULL;
+		sc->sc_ih1 = NULL;
+		sc->sc_ihc0 = NULL;
+		sc->sc_ihc1 = NULL;
+		sc->sc_ihc2 = NULL;
+		sc->sc_ihotg = NULL;
+	}
+
+	omohci_disable(sc);
+
+	/* stop clock */
+#if 0
+	pxa2x0_clkman_config(CKEN_USBHC, 0);
+#endif
+
+	if (sc->sc.sc_size) {
+		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
+		sc->sc.sc_size = 0;
+	}
+
+	return (0);
+}
+
+
+void
+omohci_power(int why, void *arg)
+{
+	struct omohci_softc		*sc = (struct omohci_softc *)arg;
+	int				s;
+
+	s = splhardusb();
+	sc->sc.sc_bus.use_polling++;
+	switch (why) {
+	case PWR_STANDBY:
+	case PWR_SUSPEND:
+		ohci_power(why, &sc->sc);
+#if 0
+		pxa2x0_clkman_config(CKEN_USBHC, 0);
+#endif
+		break;
+
+	case PWR_RESUME:
+#if 0
+		pxa2x0_clkman_config(CKEN_USBHC, 1);
+#endif
+		omohci_enable(sc);
+		ohci_power(why, &sc->sc);
+		break;
+	}
+	sc->sc.sc_bus.use_polling--;
+	splx(s);
+}
+
+void
+omohci_enable(struct omohci_softc *sc)
+{
+#if 0
+	u_int32_t			hr;
+
+	/* Full host reset */
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
+
+	DELAY(USBHC_RST_WAIT);
+
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
+
+	/* Force system bus interface reset */
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
+
+	while (bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR) & \
+	    USBHC_HR_FSBIR)
+		DELAY(3);
+
+	/* Enable the ports (physically only one, only enable that one?) */
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSEP2));
+#endif
+}
+
+void
+omohci_disable(struct omohci_softc *sc)
+{
+#if 0
+	u_int32_t			hr;
+
+	/* Full host reset */
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
+
+	DELAY(USBHC_RST_WAIT);
+
+	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
+	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
+	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
+#endif
+}
diff --git a/sys/arch/beagle/dev/prcm.c b/sys/arch/beagle/dev/prcm.c
new file mode 100644
index 00000000000..01e54d42cdc
--- /dev/null
+++ b/sys/arch/beagle/dev/prcm.c
@@ -0,0 +1,335 @@
+/* $OpenBSD: prcm.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <arm/cpufunc.h>
+#include <beagle/beagle/ahb.h>
+#include <beagle/dev/prcmvar.h>
+
+#define PRCM_REVISION		0x000
+#define PRCM_SYSCONFIG		0x010
+#define PRCM_IRQSTATUS_MPU	0x018
+#define PRCM_IRQENABLE_MPU	0x01c
+#define PRCM_VOLTCTRL		0x050
+#define PRCM_VOLTST		0x054
+#define PRCM_CLKSRC_CTRL	0x060
+#define PRCM_CLKOUT_CTRL	0x070
+#define PRCM_CLKEMUL_CTRL	0x078
+#define PRCM_CLKCFG_CTRL	0x080
+#define PRCM_CLKCFG_STATUS	0x084
+#define PRCM_VOLTSETUP		0x090
+#define PRCM_CLKSSETUP		0x094
+#define PRCM_POLCTRL		0x098
+#define PRCM_GP1		0x0b0
+#define PRCM_GP2		0x0b4
+#define PRCM_GP3		0x0b8
+#define PRCM_GP4		0x0bc
+#define PRCM_GP5		0x0c0
+#define PRCM_GP6		0x0c4
+#define PRCM_GP7		0x0c8
+#define PRCM_GP8		0x0cc
+#define PRCM_GP9		0x0d0
+#define PRCM_GP10		0x0d4
+#define PRCM_GP11		0x0d8
+#define PRCM_GP12		0x0dc
+#define PRCM_GP13		0x0e0
+#define PRCM_GP14		0x0e4
+#define PRCM_GP15		0x0e8
+#define PRCM_GP16		0x0ec
+#define PRCM_GP17		0x0f0
+#define PRCM_GP18		0x0f4
+#define PRCM_GP19		0x0f8
+#define PRCM_GP20		0x0fc
+
+#define CM_CLKSEL_MPU		0x140
+#define  CM_CLKSTCTRL_MPU	0x148
+#define  RM_RSTST_MPU		0x158
+#define  PM_WKDEP_MPU		0x1C8
+#define  PM_EVGENCTRL_MPU	0x1D4
+#define  PM_EVEGENONTIM_MPU	0x1D8
+#define  PM_EVEGENOFFTIM_MPU	0x1DC
+#define  PM_PWSTCTRL_MPU	0x1E0
+#define  PM_PWSTST_MPU		0x1E4
+#define  CM_FCLKEN1_CORE	0x200
+#define  	CM_FCLKEN1_CORE_DSS1	0x00000001
+#define  	CM_FCLKEN1_CORE_DSS2	0x00000002
+#define  	CM_FCLKEN1_CORE_TV	0x00000004
+#define  	CM_FCLKEN1_CORE_VLYNQ	0x00000008
+#define  	CM_FCLKEN1_CORE_GP2	0x00000010
+#define  	CM_FCLKEN1_CORE_GP3	0x00000020
+#define  	CM_FCLKEN1_CORE_GP4	0x00000040
+#define  	CM_FCLKEN1_CORE_GP5	0x00000080
+#define  	CM_FCLKEN1_CORE_GP6	0x00000100
+#define  	CM_FCLKEN1_CORE_GP7	0x00000200
+#define  	CM_FCLKEN1_CORE_GP8	0x00000400
+#define  	CM_FCLKEN1_CORE_GP9	0x00000800
+#define  	CM_FCLKEN1_CORE_GP10	0x00001000
+#define  	CM_FCLKEN1_CORE_GP11	0x00002000
+#define  	CM_FCLKEN1_CORE_GP12	0x00004000
+#define  	CM_FCLKEN1_CORE_MCBSP1	0x00008000
+#define  	CM_FCLKEN1_CORE_MCBSP2	0x00010000
+#define  	CM_FCLKEN1_CORE_MCSPI1	0x00020000
+#define  	CM_FCLKEN1_CORE_MCSPI2	0x00040000
+#define  	CM_FCLKEN1_CORE_I2C1	0x00080000
+#define  	CM_FCLKEN1_CORE_I2C2	0x00100000
+#define  	CM_FCLKEN1_CORE_UART1	0x00200000
+#define  	CM_FCLKEN1_CORE_UART2	0x00400000
+#define  	CM_FCLKEN1_CORE_HDQ	0x00800000
+#define  	CM_FCLKEN1_CORE_EAC	0x01000000
+#define  	CM_FCLKEN1_CORE_FAC	0x02000000
+#define  	CM_FCLKEN1_CORE_MMC	0x04000000
+#define  	CM_FCLKEN1_CORE_MSPR0	0x08000000
+#define  	CM_FCLKEN1_CORE_WDT3	0x10000000
+#define  	CM_FCLKEN1_CORE_WDT4	0x20000000
+#define  	CM_FCLKEN1_CORE_CAM	0x80000000
+#define  CM_FCLKEN2_CORE	0x204
+#define  	CM_FCLKEN2_CORE_UART3	0x00000004
+#define  	CM_FCLKEN2_CORE_SSI	0x00000002
+#define  	CM_FCLKEN2_CORE_USB	0x00000001
+#define  CM_ICLKEN1_CORE	0x210
+#define  	CM_ICLKEN1_CORE_DSS1	0x00000001
+#define  	CM_ICLKEN1_CORE_VLYNQ	0x00000008
+#define  	CM_ICLKEN1_CORE_GP2	0x00000010
+#define  	CM_ICLKEN1_CORE_GP3	0x00000020
+#define  	CM_ICLKEN1_CORE_GP4	0x00000040
+#define  	CM_ICLKEN1_CORE_GP5	0x00000080
+#define  	CM_ICLKEN1_CORE_GP6	0x00000100
+#define  	CM_ICLKEN1_CORE_GP7	0x00000200
+#define  	CM_ICLKEN1_CORE_GP8	0x00000400
+#define  	CM_ICLKEN1_CORE_GP9	0x00000800
+#define  	CM_ICLKEN1_CORE_GP10	0x00001000
+#define  	CM_ICLKEN1_CORE_GP11	0x00002000
+#define  	CM_ICLKEN1_CORE_GP12	0x00004000
+#define  	CM_ICLKEN1_CORE_MCBSP1	0x00008000
+#define  	CM_ICLKEN1_CORE_MCBSP2	0x00010000
+#define  	CM_ICLKEN1_CORE_MCSPI1	0x00020000
+#define  	CM_ICLKEN1_CORE_MCSPI2	0x00040000
+#define  	CM_ICLKEN1_CORE_I2C1	0x00080000
+#define  	CM_ICLKEN1_CORE_I2C2	0x00100000
+#define  	CM_ICLKEN1_CORE_UART1	0x00200000
+#define  	CM_ICLKEN1_CORE_UART2	0x00400000
+#define  	CM_ICLKEN1_CORE_HDQ	0x00800000
+#define  	CM_ICLKEN1_CORE_EAC	0x01000000
+#define  	CM_ICLKEN1_CORE_FAC	0x02000000
+#define  	CM_ICLKEN1_CORE_MMC	0x04000000
+#define  	CM_ICLKEN1_CORE_MSPR0	0x08000000
+#define  	CM_ICLKEN1_CORE_WDT3	0x10000000
+#define  	CM_ICLKEN1_CORE_WDT4	0x20000000
+#define  	CM_ICLKEN1_CORE_MAILBOX	0x40000000
+#define  	CM_ICLKEN1_CORE_CAM	0x80000000
+#define  CM_ICLKEN2_CORE	0x214
+#define  CM_ICLKEN4_CORE	0x21C
+#define  CM_IDLEST1_CORE	0x220
+#define  CM_IDLEST2_CORE	0x224
+#define  CM_IDLEST4_CORE	0x22C
+#define  CM_AUTOIDLE1_CORE	0x230
+#define  CM_AUTOIDLE2_CORE	0x234
+#define  CM_AUTOIDLE3_CORE	0x238
+#define  CM_AUTOIDLE4_CORE	0x23C
+#define  CM_CLKSEL1_CORE	0x240
+#define  CM_CLKSEL2_CORE	0x244
+#define  CM_CLKSTCTRL_CORE	0x248
+#define  PM_WKEN1_CORE		0x2A0
+#define  PM_WKEN2_CORE		0x2A4
+#define  PM_WKST1_CORE		0x2B0
+#define  PM_WKST2_CORE		0x2B4
+#define  PM_WKDEP_CORE		0x2C8
+#define  PM_PWSTCTRL_CORE	0x2E0
+#define  PM_PWSTST_CORE		0x2E4
+#define  CM_FCLKEN_GFX		0x300
+#define  CM_ICLKEN_GFX		0x310
+
+#define CM_IDLEST_GFX		0x320
+#define CM_CLKSEL_GFX		0x340
+#define CM_CLKSTCTRL_GFX	0x348
+#define RM_RSTCTRL_GFX		0x350
+#define RM_RSTST_GFX		0x358
+#define PM_WKDEP_GFX		0x3C8
+#define PM_PWSTCTRL_GFX		0x3E0
+#define PM_PWSTST_GFX		0x3E4
+#define CM_FCLKEN_WKUP		0x400
+#define		CM_FCLKEN_WKUP_GPT1	1
+#define		CM_FCLKEN_WKUP_GPIOS	4
+#define		CM_FCLKEN_WKUP_MPU_WDT	8
+#define CM_ICLKEN_WKUP		0x410
+#define		CM_ICLKEN_WKUP_GPT1	0x01
+#define		CM_ICLKEN_WKUP_32KSYNC	0x02
+#define		CM_ICLKEN_WKUP_GPIOS	0x04
+#define		CM_ICLKEN_WKUP_MPU_WDT	0x08
+#define		CM_ICLKEN_WKUP_WDT1	0x10
+#define		CM_ICLKEN_WKUP_OMAPCTRL	0x20
+#define	CM_IDLEST_WKUP		0x420
+#define CM_AUTOIDLE_WKUP	0x430
+#define CM_CLKSEL_WKUP		0x440
+#define RM_RSTCTRL_WKUP		0x450
+#define RM_RSTTIME_WKUP		0x454
+#define RM_RSTST_WKUP		0x458
+#define PM_WKEN_WKUP		0x4A0
+#define PM_WKST_WKUP		0x4B0
+#define CM_CLKEN_PLL		0x500
+#define CM_IDLEST_CKGEN		0x520
+#define CM_AUTOIDLE_PLL		0x530
+#define CM_CLKSEL1_PLL		0x540
+#define CM_CLKSEL2_PLL		0x544
+#define CM_FCLKEN_DSP		0x800
+#define CM_ICLKEN_DSP		0x810
+#define CM_IDLEST_DSP		0x820
+#define CM_AUTOIDLE_DSP		0x830
+#define CM_CLKSEL_DSP		0x840
+#define CM_CLKSTCTRL_DSP	0x848
+#define RM_RSTCTRL_DSP		0x850
+#define RM_RSTST_DSP		0x858
+#define PM_WKEN_DSP		0x8A0
+#define PM_WKDEP_DSP		0x8C8
+#define PM_PWSTCTRL_DSP		0x8E0
+#define PM_PWSTST_DSP		0x8E4
+#define PRCM_IRQSTATUS_DSP	0x8F0
+#define PRCM_IRQENABLE_DSP	0x8F4
+#define PRCM_IRQSTATUS_IVA	0x8F8
+#define PRCM_IRQENABLE_IVA	0x8FC
+#define PRCM_SIZE	0x1000
+
+bus_space_tag_t prcm_iot;
+bus_space_handle_t prcm_ioh;
+int prcm_attached;
+
+int     prcm_match(struct device *, void *, void *);
+void    prcm_attach(struct device *, struct device *, void *);
+
+
+
+struct cfattach	prcm_ca = {
+	sizeof (struct device), prcm_match, prcm_attach
+};
+
+struct cfdriver prcm_cd = {
+	NULL, "prcm", DV_DULL
+};
+
+int
+prcm_match(struct device *parent, void *v, void *aux)
+{
+	/* only attach once */
+	if (prcm_attached != 0)
+		return (0);
+	return (1);
+}
+
+void
+prcm_attach(struct device *parent, struct device *self, void *args)
+{
+        struct ahb_attach_args *aa = args;
+	prcm_iot = aa->aa_iot;
+	u_int32_t reg;
+
+	if (bus_space_map(prcm_iot, aa->aa_addr, PRCM_SIZE, 0, &prcm_ioh))
+		panic("prcm_attach: bus_space_map failed!");
+
+	reg = bus_space_read_4(prcm_iot, prcm_ioh, PRCM_REVISION);
+	printf(" rev %d.%d\n", reg >> 4 & 0xf, reg & 0xf);
+	
+	prcm_attached = 1;
+
+	/* XXX */
+#if 1
+	printf("CM_FCLKEN1_CORE %x\n", bus_space_read_4(prcm_iot, prcm_ioh, CM_FCLKEN1_CORE));
+	printf("CM_ICLKEN1_CORE %x\n", bus_space_read_4(prcm_iot, prcm_ioh, CM_ICLKEN1_CORE));
+	printf("CM_AUTOIDLE1_CORE %x\n", bus_space_read_4(prcm_iot, prcm_ioh, CM_AUTOIDLE1_CORE));
+
+	printf("CM_FCLKEN_WKUP %x\n", bus_space_read_4(prcm_iot, prcm_ioh, CM_FCLKEN_WKUP));
+	printf(" CM_IDLEST_WKUP %x\n", bus_space_read_4(prcm_iot, prcm_ioh,  CM_IDLEST_WKUP));
+//	bus_space_write_4(prcm_iot, prcm_ioh, 
+#endif
+
+	reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_FCLKEN1_CORE);
+	reg |= CM_FCLKEN1_CORE_GP3|CM_FCLKEN1_CORE_GP2;
+	bus_space_write_4(prcm_iot, prcm_ioh, CM_FCLKEN1_CORE, reg);
+	reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_ICLKEN1_CORE);
+	reg |= CM_ICLKEN1_CORE_GP3|CM_ICLKEN1_CORE_GP2;
+	bus_space_write_4(prcm_iot, prcm_ioh, CM_ICLKEN1_CORE, reg);
+
+	reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_FCLKEN_WKUP);
+	reg |= CM_FCLKEN_WKUP_MPU_WDT | CM_FCLKEN_WKUP_GPT1;
+	bus_space_write_4(prcm_iot, prcm_ioh, CM_FCLKEN_WKUP, reg);
+
+	reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_ICLKEN_WKUP);
+	reg |= CM_ICLKEN_WKUP_MPU_WDT | CM_ICLKEN_WKUP_GPT1;
+	bus_space_write_4(prcm_iot, prcm_ioh, CM_ICLKEN_WKUP, reg);
+}
+
+void
+prcm_setclock(int clock, int speed)
+{
+#if 0
+	u_int32_t reg;
+	if (clock == 0) {
+		reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_CLKSEL_WKUP);
+		reg &= ~( 3 << ((clock -1) *2 ));
+		reg |=  ( speed << ((clock -1) *2 ));
+		bus_space_write_4(prcm_iot, prcm_ioh, CM_CLKSEL_WKUP, reg);
+	} else if (clock > 0 && clock < 13) {
+		reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_CLKSEL2_CORE);
+
+		reg &= ~( 3 << (clock * 2));
+		reg |=  ( speed << ((clock -1) *2 ));
+
+		bus_space_write_4(prcm_iot, prcm_ioh, CM_CLKSEL2_CORE, reg);
+	} else
+		panic("prcm_setclock invalid clock %d\n", clock);
+#endif
+}
+
+void
+prcm_enableclock(int bit)
+{
+#if 0
+	u_int32_t fclk, iclk;
+	int freg, ireg;
+
+	if (bit < 31){
+		freg = CM_FCLKEN1_CORE;
+		ireg = CM_ICLKEN1_CORE;
+	} else {
+		freg = CM_FCLKEN2_CORE;
+		ireg = CM_ICLKEN2_CORE;
+	}
+
+	fclk = bus_space_read_4(prcm_iot, prcm_ioh, freg);
+	iclk = bus_space_read_4(prcm_iot, prcm_ioh, ireg);
+	fclk |=  1 << (bit & 0x1f);
+	iclk |=  1 << (bit & 0x1f);
+
+	/* mask reserved bits (XXX?) */
+	if (bit > 31){
+		fclk &= 0xbfffffff;
+		iclk &= 0xfffffff9;
+	} else {
+		fclk &= 0x00000007;
+		iclk &= 0x00000007;
+	}
+	bus_space_write_4(prcm_iot, prcm_ioh, freg, fclk);
+	bus_space_write_4(prcm_iot, prcm_ioh, ireg, iclk);
+#endif
+}
diff --git a/sys/arch/beagle/dev/prcmvar.h b/sys/arch/beagle/dev/prcmvar.h
new file mode 100644
index 00000000000..559117258ca
--- /dev/null
+++ b/sys/arch/beagle/dev/prcmvar.h
@@ -0,0 +1,61 @@
+/* $OpenBSD: prcmvar.h,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/*
+ * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+void prcm_setclock(int clock, int speed);
+#define PRCM_CLK_SPEED_32	0
+#define PRCM_CLK_SPEED_SYS	1
+#define PRCM_CLK_SPEED_EXT	2
+
+void prcm_enableclock(int bit);
+
+#define  	PRCM_CLK_EN_DSS1	0
+#define  	PRCM_CLK_EN_DSS2	1
+#define  	PRCM_CLK_EN_TV		2
+#define  	PRCM_CLK_EN_VLYNQ	3
+#define  	PRCM_CLK_EN_GP2		4
+#define  	PRCM_CLK_EN_GP		5
+#define  	PRCM_CLK_EN_GP4		6
+#define  	PRCM_CLK_EN_GP5		7
+#define  	PRCM_CLK_EN_GP6		8
+#define  	PRCM_CLK_EN_GP7		9
+#define  	PRCM_CLK_EN_GP8		10
+#define  	PRCM_CLK_EN_GP9		11
+#define  	PRCM_CLK_EN_GP10	12
+#define  	PRCM_CLK_EN_GP11	13
+#define  	PRCM_CLK_EN_GP12	14
+#define  	PRCM_CLK_EN_MCBSP1	15
+#define  	PRCM_CLK_EN_MCBSP2	16
+#define  	PRCM_CLK_EN_MCSPI1	17
+#define  	PRCM_CLK_EN_MCSPI2	18
+#define  	PRCM_CLK_EN_I2C1	19
+#define  	PRCM_CLK_EN_I2C2	20
+#define  	PRCM_CLK_EN_UART1	21
+#define  	PRCM_CLK_EN_UART2	22
+#define  	PRCM_CLK_EN_HDQ		23
+#define  	PRCM_CLK_EN_EAC		24
+#define  	PRCM_CLK_EN_FAC		25
+#define  	PRCM_CLK_EN_MMC		26
+#define  	PRCM_CLK_EN_MSPR0	27
+#define  	PRCM_CLK_EN_WDT3	28
+#define  	PRCM_CLK_EN_WDT4	29
+#define  	PRCM_CLK_EN_MAILBOX	30
+#define  	PRCM_CLK_EN_CAM		31
+#define  	PRCM_CLK_EN_USB		32
+#define  	PRCM_CLK_EN_SSI		33
+#define  	PRCM_CLK_EN_UART3	34
+
+/* need interface for CM_AUTOIDLE */
diff --git a/sys/arch/beagle/include/_types.h b/sys/arch/beagle/include/_types.h
new file mode 100644
index 00000000000..85f3a260435
--- /dev/null
+++ b/sys/arch/beagle/include/_types.h
@@ -0,0 +1,11 @@
+/* 	$OpenBSD: _types.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: types.h,v 1.4 2002/02/28 03:17:26 simonb Exp $	*/
+
+#ifndef _ARMISH__TYPES_H_
+#define	_ARMISH__TYPES_H_
+
+#include <arm/_types.h>
+#define __HAVE_GENERIC_SOFT_INTERRUPTS
+#define __HAVE_TIMECOUNTER
+
+#endif /* _ARMISH__TYPES_H_ */
diff --git a/sys/arch/beagle/include/apmvar.h b/sys/arch/beagle/include/apmvar.h
new file mode 100644
index 00000000000..dfce83ed6c6
--- /dev/null
+++ b/sys/arch/beagle/include/apmvar.h
@@ -0,0 +1 @@
+#include <arm/apmvar.h>
diff --git a/sys/arch/beagle/include/asm.h b/sys/arch/beagle/include/asm.h
new file mode 100644
index 00000000000..0b7b4d32bea
--- /dev/null
+++ b/sys/arch/beagle/include/asm.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: asm.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: asm.h,v 1.3 2001/11/25 15:55:54 thorpej Exp $	*/
+
+#include <arm/asm.h>
diff --git a/sys/arch/beagle/include/atomic.h b/sys/arch/beagle/include/atomic.h
new file mode 100644
index 00000000000..ecff4e22093
--- /dev/null
+++ b/sys/arch/beagle/include/atomic.h
@@ -0,0 +1,10 @@
+/*	$OpenBSD: atomic.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+
+/* Public Domain */
+
+#ifndef __ARMISH_ATOMIC_H__
+#define __ARMISH_ATOMIC_H__
+
+#include <arm/atomic.h>
+
+#endif /* __ARMISH_ATOMIC_H__ */
diff --git a/sys/arch/beagle/include/beagle_intr.h b/sys/arch/beagle/include/beagle_intr.h
new file mode 100644
index 00000000000..8a97a26401b
--- /dev/null
+++ b/sys/arch/beagle/include/beagle_intr.h
@@ -0,0 +1,119 @@
+/*	$OpenBSD: beagle_intr.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: intr.h,v 1.12 2003/06/16 20:00:59 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 2001, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BEAGLEBOARD_INTR_H
+#define BEAGLEBOARD_INTR_H
+
+#ifndef _LKM
+
+#include <beagle/dev/intc.h>
+
+#endif
+
+#ifndef _LOCORE
+
+
+#if defined(_LKM)
+
+int	_splraise(int);
+int	_spllower(int);
+void	splx(int);
+void	_setsoftintr(int);
+
+#else	/* _LKM */
+
+/*
+ * Each board needs to define the following functions:
+ *
+ * int	_splraise(int);
+ * int	_spllower(int);
+ * void	splx(int);
+ * void	_setsoftintr(int);
+ *
+ * These may be defined as functions, static __inline functions, or macros,
+ * but there must be a _spllower() and splx() defined as functions callable
+ * from assembly language (for cpu_switch()).  However, since it's quite
+ * useful to be able to inline splx(), you could do something like the
+ * following:
+ *
+ * in <boardtype>_intr.h:
+ * 	static __inline int
+ *	boardtype_splx(int spl)
+ *	{...}
+ *
+ *	#define splx(nspl)	boardtype_splx(nspl)
+ *	...
+ * and in boardtype's machdep code:
+ *
+ *	...
+ *	#undef splx
+ *	int
+ *	splx(int spl)
+ *	{
+ *		return boardtype_splx(spl);
+ *	}
+ */
+
+
+#endif /* _LKM */
+
+
+#ifdef DIAGNOSTIC
+/*
+ * Although this function is implemented in MI code, it must be in this MD
+ * header because we don't want this header to include MI includes.
+ */
+void splassert_fail(int, int, const char *);
+extern int splassert_ctl;
+void i80321_splassert_check(int, const char *);
+#define splassert(__wantipl) do {                               \
+	if (splassert_ctl > 0) {                                \
+		i80321_splassert_check(__wantipl, __func__);    \
+	}                                                       \
+} while (0)
+#define splsoftassert(wantipl) splassert(wantipl)
+#else
+#define splassert(wantipl)      do { /* nothing */ } while (0)
+#define splsoftassert(wantipl)  do { /* nothing */ } while (0)
+#endif
+
+
+
+#endif /* ! _LOCORE */
+
+#endif /* BEAGLEBOARD_INTR_H */
diff --git a/sys/arch/beagle/include/bootconfig.h b/sys/arch/beagle/include/bootconfig.h
new file mode 100644
index 00000000000..42d695f5ab3
--- /dev/null
+++ b/sys/arch/beagle/include/bootconfig.h
@@ -0,0 +1,78 @@
+/*	$OpenBSD: bootconfig.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $	*/
+
+/*
+ * Copyright (c) 1994 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe
+ *	for the NetBSD Project.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * boot configuration structures
+ *
+ * Created      : 12/09/94
+ *
+ * Based on kate/boot/bootconfig.h
+ */
+
+typedef struct _PhysMem {
+	u_int address;
+	u_int pages;
+} PhysMem;
+
+#if defined(_KERNEL) || defined(_STANDALONE)
+
+#define	DRAM_BLOCKS	1
+
+typedef struct _BootConfig {
+	PhysMem dram[DRAM_BLOCKS];
+	u_int dramblocks;
+} BootConfig;
+
+extern BootConfig bootconfig;
+#define MAX_BOOT_STRING 255
+
+#define BOOTOPT_TYPE_BOOLEAN		0
+#define BOOTOPT_TYPE_STRING		1
+#define BOOTOPT_TYPE_INT		2
+#define BOOTOPT_TYPE_BININT		3
+#define BOOTOPT_TYPE_HEXINT		4
+#define BOOTOPT_TYPE_MASK		7
+
+#endif	/* _KERNEL || _STANDALONE */
+#if defined(_KERNEL) 
+int get_bootconf_option (char *string, char *option, int type, void *result);
+
+extern char *boot_args;
+extern char *boot_file;
+#endif	/* _KERNEL */
+
+/* End of bootconfig.h */
diff --git a/sys/arch/beagle/include/bus.h b/sys/arch/beagle/include/bus.h
new file mode 100644
index 00000000000..6b55d2f27bb
--- /dev/null
+++ b/sys/arch/beagle/include/bus.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: bus.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: bus.h,v 1.3 2001/11/25 15:55:55 thorpej Exp $	*/
+
+#include <arm/bus.h>
diff --git a/sys/arch/beagle/include/cdefs.h b/sys/arch/beagle/include/cdefs.h
new file mode 100644
index 00000000000..e167fce187e
--- /dev/null
+++ b/sys/arch/beagle/include/cdefs.h
@@ -0,0 +1,3 @@
+/*	$OpenBSD: cdefs.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+
+#include <arm/cdefs.h>
diff --git a/sys/arch/beagle/include/conf.h b/sys/arch/beagle/include/conf.h
new file mode 100644
index 00000000000..c696aef990c
--- /dev/null
+++ b/sys/arch/beagle/include/conf.h
@@ -0,0 +1,18 @@
+/*	$OpenBSD: conf.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: conf.h,v 1.8 2002/02/10 12:26:03 chris Exp $	*/
+
+#ifndef _BEAGLEBOARD_CONF_H
+#define	_BEAGLEBOARD_CONF_H
+
+#include <sys/conf.h>
+
+/*
+ * BEAGLEBOARD specific device includes go in here
+ */
+
+#define	CONF_HAVE_USB
+//#define	CONF_HAVE_GPIO
+
+#include <arm/conf.h>
+
+#endif	/* _BEAGLEBOARD_CONF_H */
diff --git a/sys/arch/beagle/include/cpu.h b/sys/arch/beagle/include/cpu.h
new file mode 100644
index 00000000000..69f0002995b
--- /dev/null
+++ b/sys/arch/beagle/include/cpu.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: cpu.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: cpu.h,v 1.3 2001/11/25 15:55:55 thorpej Exp $	*/
+
+#include <arm/cpu.h>
diff --git a/sys/arch/beagle/include/db_machdep.h b/sys/arch/beagle/include/db_machdep.h
new file mode 100644
index 00000000000..fb95a7557b9
--- /dev/null
+++ b/sys/arch/beagle/include/db_machdep.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: db_machdep.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: db_machdep.h,v 1.3 2001/11/25 15:55:55 thorpej Exp $	*/
+
+#include <arm/db_machdep.h>
diff --git a/sys/arch/beagle/include/disklabel.h b/sys/arch/beagle/include/disklabel.h
new file mode 100644
index 00000000000..fe5ccb6f38c
--- /dev/null
+++ b/sys/arch/beagle/include/disklabel.h
@@ -0,0 +1,3 @@
+/*	$OpenBSD: disklabel.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+
+#include <arm/disklabel.h>
diff --git a/sys/arch/beagle/include/elf_abi.h b/sys/arch/beagle/include/elf_abi.h
new file mode 100644
index 00000000000..69c105f6884
--- /dev/null
+++ b/sys/arch/beagle/include/elf_abi.h
@@ -0,0 +1,3 @@
+/*	$OpenBSD: elf_abi.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+
+#include <arm/elf_abi.h>
diff --git a/sys/arch/beagle/include/endian.h b/sys/arch/beagle/include/endian.h
new file mode 100644
index 00000000000..f64d927dcad
--- /dev/null
+++ b/sys/arch/beagle/include/endian.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: endian.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: endian.h,v 1.3 2001/11/25 15:55:56 thorpej Exp $	*/
+
+#include <arm/endian.h>
diff --git a/sys/arch/beagle/include/exec.h b/sys/arch/beagle/include/exec.h
new file mode 100644
index 00000000000..f6a7045e011
--- /dev/null
+++ b/sys/arch/beagle/include/exec.h
@@ -0,0 +1,3 @@
+/*	$OpenBSD: exec.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/* public domain */
+#include <arm/exec.h>
diff --git a/sys/arch/beagle/include/float.h b/sys/arch/beagle/include/float.h
new file mode 100644
index 00000000000..939d01cfada
--- /dev/null
+++ b/sys/arch/beagle/include/float.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: float.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: float.h,v 1.3 2001/11/25 15:55:56 thorpej Exp $	*/
+
+#include <arm/float.h>
diff --git a/sys/arch/beagle/include/fp.h b/sys/arch/beagle/include/fp.h
new file mode 100644
index 00000000000..4889497285b
--- /dev/null
+++ b/sys/arch/beagle/include/fp.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: fp.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: fp.h,v 1.3 2001/11/25 15:55:56 thorpej Exp $	*/
+
+#include <arm/fp.h>
diff --git a/sys/arch/beagle/include/frame.h b/sys/arch/beagle/include/frame.h
new file mode 100644
index 00000000000..11efab620eb
--- /dev/null
+++ b/sys/arch/beagle/include/frame.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: frame.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/* $NetBSD: frame.h,v 1.1 2001/06/08 22:23:00 chris Exp $ */
+
+#include <arm/frame.h>
diff --git a/sys/arch/beagle/include/ieee.h b/sys/arch/beagle/include/ieee.h
new file mode 100644
index 00000000000..f2607f2c3de
--- /dev/null
+++ b/sys/arch/beagle/include/ieee.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: ieee.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: ieee.h,v 1.3 2001/11/25 15:55:56 thorpej Exp $	*/
+
+#include <arm/ieee.h>
diff --git a/sys/arch/beagle/include/ieeefp.h b/sys/arch/beagle/include/ieeefp.h
new file mode 100644
index 00000000000..7349d3c60e8
--- /dev/null
+++ b/sys/arch/beagle/include/ieeefp.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: ieeefp.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: ieeefp.h,v 1.3 2001/11/25 15:55:56 thorpej Exp $	*/
+
+#include <arm/ieeefp.h>
diff --git a/sys/arch/beagle/include/internal_types.h b/sys/arch/beagle/include/internal_types.h
new file mode 100644
index 00000000000..84beb0f6819
--- /dev/null
+++ b/sys/arch/beagle/include/internal_types.h
@@ -0,0 +1,7 @@
+/* $OpenBSD: internal_types.h,v 1.1 2009/05/08 03:13:26 drahn Exp $ */
+/* Public domain */
+#ifndef _MACHINE_INTERNAL_TYPES_H_
+#define _MACHINE_INTERNAL_TYPES_H_
+
+#include "arm/internal_types.h"
+#endif
diff --git a/sys/arch/beagle/include/intr.h b/sys/arch/beagle/include/intr.h
new file mode 100644
index 00000000000..d21d190f868
--- /dev/null
+++ b/sys/arch/beagle/include/intr.h
@@ -0,0 +1,103 @@
+/*	$OpenBSD: intr.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: intr.h,v 1.12 2003/06/16 20:00:59 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 2001, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef	_BEAGLEBOARD_INTR_H_
+#define	_BEAGLEBOARD_INTR_H_
+
+#ifdef _KERNEL
+
+
+/* Interrupt priority "levels". */
+#define	IPL_NONE	0	/* nothing */
+#define	IPL_SOFT	1	/* generic software interrupts */
+#define	IPL_SOFTCLOCK	2	/* software clock interrupt */
+#define	IPL_SOFTNET	3	/* software network interrupt */
+#define	IPL_BIO		4	/* block I/O */
+#define	IPL_NET		5	/* network */
+#define	IPL_SOFTTTY	6	/* software serial interrupt */
+#define	IPL_TTY		7	/* terminals */
+#define	IPL_VM		8	/* memory allocation */
+#define	IPL_AUDIO	9	/* audio device */
+#define	IPL_CLOCK	10	/* clock interrupt */
+#define	IPL_STATCLOCK	11	/* statistics clock interrupt */
+#define	IPL_HIGH	12	/* everything */
+
+#define	NIPL		13
+
+/* Interrupt sharing types. */
+#define	IST_NONE	0	/* none */
+#define	IST_PULSE	1	/* pulsed */
+#define	IST_EDGE	2	/* edge-triggered */
+#define	IST_LEVEL	3	/* level-triggered */
+
+#define IST_LEVEL_LOW	 IST_LEVEL
+#define IST_LEVEL_HIGH   4
+#define IST_EDGE_FALLING IST_EDGE
+#define IST_EDGE_RISING  5
+#define IST_EDGE_BOTH    6
+
+#ifndef _LOCORE
+
+#include <sys/device.h>
+#include <sys/queue.h>
+
+#define	splhigh()	_splraise(IPL_HIGH)
+#define	splsoft()	_splraise(IPL_SOFT)
+#define	splsoftclock()	_splraise(IPL_SOFTCLOCK)
+#define	splsoftnet()	_splraise(IPL_SOFTNET)
+#define	splbio()	_splraise(IPL_BIO)
+#define	splnet()	_splraise(IPL_NET)
+#define	spltty()	_splraise(IPL_TTY)
+#define	splvm()		_splraise(IPL_VM)
+#define	splaudio()	_splraise(IPL_AUDIO)
+#define	splclock()	_splraise(IPL_CLOCK)
+#define	splstatclock()	_splraise(IPL_STATCLOCK)
+
+#define	spl0()		_spllower(IPL_NONE)
+
+#define	splsched()	splhigh()
+#define	spllock()	splhigh()
+
+#endif /* ! _LOCORE */
+
+#include "machine/beagle_intr.h"
+
+#endif /* _KERNEL */
+
+#endif	/* _BEAGLEBOARD_INTR_H_ */
+
diff --git a/sys/arch/beagle/include/irqhandler.h b/sys/arch/beagle/include/irqhandler.h
new file mode 100644
index 00000000000..58a2e53b2a2
--- /dev/null
+++ b/sys/arch/beagle/include/irqhandler.h
@@ -0,0 +1,4 @@
+/* 	$OpenBSD: irqhandler.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: irqhandler.h,v 1.4 2002/04/12 18:50:32 thorpej Exp $	*/
+
+#include <arm/footbridge/footbridge_irqhandler.h>
diff --git a/sys/arch/beagle/include/isa_machdep.h b/sys/arch/beagle/include/isa_machdep.h
new file mode 100644
index 00000000000..15aa3b0ac82
--- /dev/null
+++ b/sys/arch/beagle/include/isa_machdep.h
@@ -0,0 +1,13 @@
+/* 	$OpenBSD: isa_machdep.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/* $NetBSD: isa_machdep.h,v 1.4 2002/01/07 22:58:08 chris Exp $ */
+
+#ifndef _MPHONE_ISA_MACHDEP_H_
+#define _MPHONE_ISA_MACHDEP_H_
+#include <arm/isa_machdep.h>
+
+#ifdef _KERNEL
+#define ISA_FOOTBRIDGE_IRQ IRQ_IN_L2
+void	isa_footbridge_init(u_int, u_int);
+#endif /* _KERNEL */
+
+#endif /* _MPHONE_ISA_MACHDEP_H_ */
diff --git a/sys/arch/beagle/include/limits.h b/sys/arch/beagle/include/limits.h
new file mode 100644
index 00000000000..fa906684169
--- /dev/null
+++ b/sys/arch/beagle/include/limits.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: limits.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: limits.h,v 1.3 2001/11/25 15:55:57 thorpej Exp $	*/
+
+#include <arm/limits.h>
diff --git a/sys/arch/beagle/include/loadfile_machdep.h b/sys/arch/beagle/include/loadfile_machdep.h
new file mode 100644
index 00000000000..4adb2d36a35
--- /dev/null
+++ b/sys/arch/beagle/include/loadfile_machdep.h
@@ -0,0 +1,52 @@
+/*	$OpenBSD: loadfile_machdep.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: loadfile_machdep.h,v 1.1 1999/04/29 03:17:12 tsubai Exp $	*/
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Christos Zoulas.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define BOOT_ELF
+#define ELFSIZE 32
+
+#define LOAD_KERNEL	(LOAD_ALL & ~LOAD_TEXTA)
+#define COUNT_KERNEL	(COUNT_ALL & ~COUNT_TEXTA)
+
+#define LOADADDR(a)		((((u_long)(a)) + offset)&0xfffffff)
+#define ALIGNENTRY(a)		((u_long)(a))
+#define READ(f, b, c)		read((f), (void *)LOADADDR(b), (c))
+#define BCOPY(s, d, c)		memcpy((void *)LOADADDR(d), (void *)(s), (c))
+#define BZERO(d, c)		memset((void *)LOADADDR(d), 0, (c))
+#define	WARN(a)			(void)(printf a, \
+				    printf((errno ? ": %s\n" : "\n"), \
+				    strerror(errno)))
+#define PROGRESS(a)		(void) printf a
+#define ALLOC(a)		alloc(a)
+#define FREE(a, b)		free(a, b)
+#define OKMAGIC(a)		((a) == OMAGIC)
+
+void run_loadfile(u_long *, int);
diff --git a/sys/arch/beagle/include/lock.h b/sys/arch/beagle/include/lock.h
new file mode 100644
index 00000000000..71ba02fede2
--- /dev/null
+++ b/sys/arch/beagle/include/lock.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: lock.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: lock.h,v 1.3 2001/11/25 15:55:57 thorpej Exp $	*/
+
+#include <arm/lock.h>
diff --git a/sys/arch/beagle/include/machine_reg.h b/sys/arch/beagle/include/machine_reg.h
new file mode 100644
index 00000000000..7d9c6c87cab
--- /dev/null
+++ b/sys/arch/beagle/include/machine_reg.h
@@ -0,0 +1,57 @@
+/*	$OpenBSD: machine_reg.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+
+/*
+ * Copyright (c) 2002, 2003  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of Genetec Corporation may not be used to endorse or 
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _MACHINE_REG_H
+#define _MACHINE_REG_H
+
+/*
+ * Logical mapping for onboard/integrated peripherals
+ */
+#define	MACHINE_IO_AREA_VBASE	0xfd000000
+#define MACHINE_GPIO_VBASE	0xfd000000
+#define MACHINE_CLKMAN_VBASE 	0xfd100000
+#define MACHINE_INTCTL_VBASE 	0xfd200000
+#define MACHINE_AGPIO_VBASE	0xfd300000
+#define MACHINE_VBASE_FREE	0xfd400000
+/* FFUART and/or BTUART are mapped to this area when
+   used for console or kgdb port */
+
+#define ioreg_read(a)  (*(volatile unsigned *)(a))
+#define ioreg_write(a,v)  (*(volatile unsigned *)(a)=(v))
+
+#define ioreg16_read(a)  (*(volatile uint16_t *)(a))
+#define ioreg16_write(a,v)  (*(volatile uint16_t *)(a)=(v))
+
+#define ioreg8_read(a)  (*(volatile uint8_t *)(a))
+#define ioreg8_write(a,v)  (*(volatile uint8_t *)(a)=(v))
+
+#endif /* _MACHINE_REG_H */
diff --git a/sys/arch/beagle/include/math.h b/sys/arch/beagle/include/math.h
new file mode 100644
index 00000000000..e83f96ad786
--- /dev/null
+++ b/sys/arch/beagle/include/math.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: math.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: math.h,v 1.3 2001/11/25 15:55:57 thorpej Exp $	*/
+
+#include <arm/math.h>
diff --git a/sys/arch/beagle/include/mutex.h b/sys/arch/beagle/include/mutex.h
new file mode 100644
index 00000000000..f2956c0b2e3
--- /dev/null
+++ b/sys/arch/beagle/include/mutex.h
@@ -0,0 +1,3 @@
+/*	$OpenBSD: mutex.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/* public domain */
+#include <arm/mutex.h>
diff --git a/sys/arch/beagle/include/param.h b/sys/arch/beagle/include/param.h
new file mode 100644
index 00000000000..9307798c2fd
--- /dev/null
+++ b/sys/arch/beagle/include/param.h
@@ -0,0 +1,51 @@
+/*	$OpenBSD: param.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: param.h,v 1.4 2002/02/12 06:58:19 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1994,1995 Mark Brinicombe.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the RiscBSD team.
+ * 4. The name "RiscBSD" nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef	_MPHONE_PARAM_H_
+#define	_MPHONE_PARAM_H_
+
+/*
+ * 1 page should be enough
+ */
+#ifndef MSGBUFSIZE
+#define MSGBUFSIZE	(1*NBPG)
+#endif
+
+#include <arm/param.h>
+
+#define	_MACHINE	mphone
+#define	MACHINE		"mphone"
+
+#endif	/* _MPHONE_PARAM_H_ */
diff --git a/sys/arch/beagle/include/pcb.h b/sys/arch/beagle/include/pcb.h
new file mode 100644
index 00000000000..6c64664a214
--- /dev/null
+++ b/sys/arch/beagle/include/pcb.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: pcb.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: pcb.h,v 1.3 2001/11/25 15:55:57 thorpej Exp $	*/
+
+#include <arm/pcb.h>
diff --git a/sys/arch/beagle/include/pio.h b/sys/arch/beagle/include/pio.h
new file mode 100644
index 00000000000..b391a5e1180
--- /dev/null
+++ b/sys/arch/beagle/include/pio.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: pio.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/* $NetBSD: pio.h,v 1.3 2001/12/07 23:09:33 chris Exp $ */
+
+#include <arm/pio.h>
diff --git a/sys/arch/beagle/include/pmap.h b/sys/arch/beagle/include/pmap.h
new file mode 100644
index 00000000000..ccbd101418c
--- /dev/null
+++ b/sys/arch/beagle/include/pmap.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: pmap.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/* $NetBSD: pmap.h,v 1.2 2001/11/23 17:29:01 thorpej Exp $ */
+
+#include <arm/pmap.h>
diff --git a/sys/arch/beagle/include/proc.h b/sys/arch/beagle/include/proc.h
new file mode 100644
index 00000000000..a681b50f559
--- /dev/null
+++ b/sys/arch/beagle/include/proc.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: proc.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: proc.h,v 1.3 2001/11/25 15:55:57 thorpej Exp $	*/
+
+#include <arm/proc.h>
diff --git a/sys/arch/beagle/include/profile.h b/sys/arch/beagle/include/profile.h
new file mode 100644
index 00000000000..def15897ddd
--- /dev/null
+++ b/sys/arch/beagle/include/profile.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: profile.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: profile.h,v 1.3 2001/11/25 15:55:57 thorpej Exp $	*/
+
+#include <arm/profile.h>
diff --git a/sys/arch/beagle/include/psl.h b/sys/arch/beagle/include/psl.h
new file mode 100644
index 00000000000..76fc5be2e9b
--- /dev/null
+++ b/sys/arch/beagle/include/psl.h
@@ -0,0 +1 @@
+/*	$OpenBSD: psl.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
diff --git a/sys/arch/beagle/include/ptrace.h b/sys/arch/beagle/include/ptrace.h
new file mode 100644
index 00000000000..1b725a71c17
--- /dev/null
+++ b/sys/arch/beagle/include/ptrace.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: ptrace.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: ptrace.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/ptrace.h>
diff --git a/sys/arch/beagle/include/reg.h b/sys/arch/beagle/include/reg.h
new file mode 100644
index 00000000000..baafc964fe0
--- /dev/null
+++ b/sys/arch/beagle/include/reg.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: reg.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: reg.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/reg.h>
diff --git a/sys/arch/beagle/include/reloc.h b/sys/arch/beagle/include/reloc.h
new file mode 100644
index 00000000000..a0214f1521d
--- /dev/null
+++ b/sys/arch/beagle/include/reloc.h
@@ -0,0 +1,2 @@
+/*	$OpenBSD: reloc.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+#include <arm/reloc.h>
diff --git a/sys/arch/beagle/include/rtc.h b/sys/arch/beagle/include/rtc.h
new file mode 100644
index 00000000000..864b0d84d69
--- /dev/null
+++ b/sys/arch/beagle/include/rtc.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: rtc.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: rtc.h,v 1.2 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/rtc.h>
diff --git a/sys/arch/beagle/include/setjmp.h b/sys/arch/beagle/include/setjmp.h
new file mode 100644
index 00000000000..9c1920111ba
--- /dev/null
+++ b/sys/arch/beagle/include/setjmp.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: setjmp.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: setjmp.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/setjmp.h>
diff --git a/sys/arch/beagle/include/signal.h b/sys/arch/beagle/include/signal.h
new file mode 100644
index 00000000000..e1f6a5d4304
--- /dev/null
+++ b/sys/arch/beagle/include/signal.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: signal.h,v 1.1 2009/05/08 03:13:26 drahn Exp $	*/
+/*	$NetBSD: signal.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/signal.h>
diff --git a/sys/arch/beagle/include/spinlock.h b/sys/arch/beagle/include/spinlock.h
new file mode 100644
index 00000000000..e9adb3fd2f3
--- /dev/null
+++ b/sys/arch/beagle/include/spinlock.h
@@ -0,0 +1,6 @@
+
+/*	$OpenBSD: spinlock.h,v 1.1 2009/05/08 03:13:27 drahn Exp $	*/
+#ifndef _MPHONE_SPINLOCK_H_
+#define _MPHONE_SPINLOCK_H_
+#include <arm/spinlock.h>
+#endif /* _MPHONE_SPINLOCK_H_ */
diff --git a/sys/arch/beagle/include/stdarg.h b/sys/arch/beagle/include/stdarg.h
new file mode 100644
index 00000000000..98b6c33c95a
--- /dev/null
+++ b/sys/arch/beagle/include/stdarg.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: stdarg.h,v 1.1 2009/05/08 03:13:27 drahn Exp $	*/
+/*	$NetBSD: stdarg.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/stdarg.h>
diff --git a/sys/arch/beagle/include/sysarch.h b/sys/arch/beagle/include/sysarch.h
new file mode 100644
index 00000000000..d8849aa6928
--- /dev/null
+++ b/sys/arch/beagle/include/sysarch.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: sysarch.h,v 1.1 2009/05/08 03:13:27 drahn Exp $	*/
+/*	$NetBSD: sysarch.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/sysarch.h>
diff --git a/sys/arch/beagle/include/trap.h b/sys/arch/beagle/include/trap.h
new file mode 100644
index 00000000000..aafdc1a5c08
--- /dev/null
+++ b/sys/arch/beagle/include/trap.h
@@ -0,0 +1,4 @@
+/*	$OpenBSD: trap.h,v 1.1 2009/05/08 03:13:27 drahn Exp $	*/
+/*	$NetBSD: trap.h,v 1.3 2001/11/25 15:55:58 thorpej Exp $	*/
+
+#include <arm/trap.h>
diff --git a/sys/arch/beagle/include/types.h b/sys/arch/beagle/include/types.h
new file mode 100644
index 00000000000..ba9aca50695
--- /dev/null
+++ b/sys/arch/beagle/include/types.h
@@ -0,0 +1,10 @@
+/* 	$OpenBSD: types.h,v 1.1 2009/05/08 03:13:27 drahn Exp $	*/
+/*	$NetBSD: types.h,v 1.4 2002/02/28 03:17:26 simonb Exp $	*/
+
+#ifndef _ARM32_TYPES_H_
+#define	_ARM32_TYPES_H_
+
+#include <arm/types.h>
+#define __HAVE_GENERIC_SOFT_INTERRUPTS
+
+#endif
diff --git a/sys/arch/beagle/include/vmparam.h b/sys/arch/beagle/include/vmparam.h
new file mode 100644
index 00000000000..30f2a67679e
--- /dev/null
+++ b/sys/arch/beagle/include/vmparam.h
@@ -0,0 +1,97 @@
+/* 	$OpenBSD: vmparam.h,v 1.1 2009/05/08 03:13:27 drahn Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.23 2003/05/22 05:47:07 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1988 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef	_ARMISH_VMPARAM_H_
+#define	_ARMISH_VMPARAM_H_
+
+#define	ARM_KERNEL_BASE		0xc0000000
+
+/* Allow armish to have bigger DSIZ than generic arm, allow user to override */
+#ifndef	MAXDSIZ
+#define	MAXDSIZ		(1024*1024*1024)		/* max data size */
+#endif
+
+#include <arm/vmparam.h>
+
+#ifdef _KERNEL
+/*
+ * Address space constants
+ */
+
+/*
+ * The line between user space and kernel space
+ * Mappings >= KERNEL_BASE are constant across all processes
+ */
+#define	KERNEL_BASE		ARM_KERNEL_BASE
+
+/*
+ * Override the default pager_map size, there's not enough KVA.
+ */
+#define PAGER_MAP_SIZE		(4 * 1024 * 1024)
+
+/*
+ * Size of User Raw I/O map
+ */
+
+#define USRIOSIZE       300
+
+/* virtual sizes (bytes) for various kernel submaps */
+
+#define VM_PHYS_SIZE		(USRIOSIZE*PAGE_SIZE)
+
+/*
+ * max number of non-contig chunks of physical RAM you can have
+ */
+
+#define	VM_PHYSSEG_MAX		1
+#define	VM_PHYSSEG_STRAT	VM_PSTRAT_RANDOM
+
+/*
+ * this indicates that we can't add RAM to the VM system after the
+ * vm system is init'd.
+ */
+
+#define	VM_PHYSSEG_NOADD
+
+/*
+ * we support 2 free lists:
+ *
+ *	- DEFAULT for all systems
+ *	- ISADMA for the ISA DMA range on Sharks only
+ */
+#endif /* _KERNEL */
+
+#define	VM_NFREELIST		2
+#define	VM_FREELIST_DEFAULT	0
+
+
+#endif	/* _ARMISH_VMPARAM_H_ */