diff options
| author | Steve Murphree <smurph@cvs.openbsd.org> | 2001-12-22 19:15:41 +0000 |
|---|---|---|
| committer | Steve Murphree <smurph@cvs.openbsd.org> | 2001-12-22 19:15:41 +0000 |
| commit | 2be42eebc94841831305e8310f14b8b2476da576 (patch) | |
| tree | 6f209c510659cedcb45e52b2cf2baf6ea1d278ae /sys/arch | |
| parent | 48bd5ca25f2b374c9567ff48f769fdd0ad5e9909 (diff) | |
Bring in PSR bit definitions.
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/mvme88k/include/asm.h | 9 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/locore.S | 8 |
2 files changed, 12 insertions, 5 deletions
diff --git a/sys/arch/mvme88k/include/asm.h b/sys/arch/mvme88k/include/asm.h index 528264bd4ae..d5b13bec5fd 100644 --- a/sys/arch/mvme88k/include/asm.h +++ b/sys/arch/mvme88k/include/asm.h @@ -1,4 +1,4 @@ -/* $OpenBSD: asm.h,v 1.18 2001/12/16 23:49:46 miod Exp $ */ +/* $OpenBSD: asm.h,v 1.19 2001/12/22 19:15:40 smurph Exp $ */ /* * Mach Operating System @@ -241,6 +241,13 @@ #define PSR_FPU_DISABLE_BIT 3 #define PSR_BIG_ENDIAN_MODE 30 #define PSR_SUPERVISOR_MODE_BIT 31 +/* + * mc88110 PSR bit definitions (MVME197) + */ +#define PSR_GRAPHICS_DISABLE_BIT 4 +#define PSR_SERIAL_MODE_BIT 29 +#define PSR_CARRY_BIT 28 +#define PSR_SERIALIZE_BIT 25 /* * Status bits for an SXIP/SNIP/SFIP address. diff --git a/sys/arch/mvme88k/mvme88k/locore.S b/sys/arch/mvme88k/mvme88k/locore.S index 8fbce094c4f..aa1fc052434 100644 --- a/sys/arch/mvme88k/mvme88k/locore.S +++ b/sys/arch/mvme88k/mvme88k/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.23 2001/12/19 07:04:41 smurph Exp $ */ +/* $OpenBSD: locore.S,v 1.24 2001/12/22 19:15:40 smurph Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -214,9 +214,9 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ set r11, r0, 1<PSR_SUPERVISOR_MODE_BIT> set r11, r11, 1<PSR_INTERRUPT_DISABLE_BIT> - set r11, r11, 1<4> - set r11, r11, 1<29> - set r11, r11, 1<25> + set r11, r11, 1<PSR_GRAPHICS_DISABLE_BIT> +/* set r11, r11, 1<PSR_SERIAL_MODE_BIT> */ + set r11, r11, 1<PSR_SERIALIZE_BIT> stcr r11, PSR stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ FLUSH_PIPELINE |