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authorTheo de Raadt <deraadt@cvs.openbsd.org>2005-10-20 20:33:03 +0000
committerTheo de Raadt <deraadt@cvs.openbsd.org>2005-10-20 20:33:03 +0000
commit4b692b818c3922b51c0f83d6a769b147c37fb988 (patch)
treeccea12ab1d4d1d25a5faffb5d1dd83e4f6be83f0 /sys/arch
parentcbd628d68441b8b2d334621fdfb2482b357602a7 (diff)
cannot manipulate hid0 register yet in 64 bit mode (because we are running
in 32 bit mode, and ibm moves the bits....) ok drahn
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/macppc/macppc/cpu.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/sys/arch/macppc/macppc/cpu.c b/sys/arch/macppc/macppc/cpu.c
index ccfcc79c171..3ae29e807e1 100644
--- a/sys/arch/macppc/macppc/cpu.c
+++ b/sys/arch/macppc/macppc/cpu.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.c,v 1.29 2005/10/09 14:17:32 drahn Exp $ */
+/* $OpenBSD: cpu.c,v 1.30 2005/10/20 20:33:02 deraadt Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
@@ -241,8 +241,10 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
ppc_curfreq = clock_freq;
cpu_cpuspeed = ppc_cpuspeed;
}
+
/* power savings mode */
- hid0 = ppc_mfhid0();
+ if (ppc_proc_is_64b == 0)
+ hid0 = ppc_mfhid0();
switch (cpu) {
case PPC_CPU_MPC603:
case PPC_CPU_MPC603e:
@@ -273,7 +275,8 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
hid0 |= HID0_NAP | HID0_DPM;
break;
}
- ppc_mthid0(hid0);
+ if (ppc_proc_is_64b == 0)
+ ppc_mthid0(hid0);
/* if processor is G3 or G4, configure l2 cache */
if (cpu == PPC_CPU_MPC750 || cpu == PPC_CPU_MPC7400 ||