Adding support for MVME188 and MVME197

24 files changed, 1538 insertions, 354 deletions

diff --git a/sys/arch/mvme88k/include/asm.h b/sys/arch/mvme88k/include/asm.h
index b2500eb2d2b..60e4b5ae9bb 100644
--- a/sys/arch/mvme88k/include/asm.h
+++ b/sys/arch/mvme88k/include/asm.h
@@ -63,14 +63,14 @@
 
 #define RTE	NOP ; rte
 
-#define PID	cr0
-#define PSR	cr1
+#define PID    cr0
+#define PSR    cr1
 #define EPSR	cr2
 #define SSBR	cr3
 #define SXIP	cr4
 #define SNIP	cr5
 #define SFIP	cr6
-#define VBR	cr7
+#define VBR    cr7
 #define DMT0	cr8
 #define DMD0	cr9
 #define DMA0	cr10
@@ -80,10 +80,42 @@
 #define DMT2	cr14
 #define DMD2	cr15
 #define DMA2	cr16
-#define SR0	cr17
-#define SR1	cr18
-#define SR2	cr19
-#define SR3	cr20
+#define SRX    cr16 
+#define SR0    cr17
+#define SR1    cr18
+#define SR2    cr19
+#define SR3    cr20
+
+/* MVME197 only */
+#define SRX    cr16 
+#define EXIP	cr4
+#define ENIP	cr5
+#define ICMD   cr25
+#define ICTL   cr26
+#define ISAR   cr27
+#define ISAP   cr28
+#define IUAP   cr29
+#define IIR    cr30
+#define IBP    cr31
+#define IPPU   cr32
+#define IPPL   cr33
+#define ISR    cr34
+#define ILAR   cr35
+#define IPAR   cr36
+#define DCMD   cr40
+#define DCTL   cr41
+#define DSAR   cr42
+#define DSAP   cr43
+#define DUAP   cr44
+#define DIR    cr45
+#define DBP    cr46
+#define DPPU   cr47
+#define DPPL   cr48
+#define DSR    cr49
+#define DLAR   cr50
+#define DPAR   cr51
+/* end MVME197 only */
+
 #define FPECR	fcr0
 #define FPHS1	fcr1
 #define FPLS1	fcr2
@@ -120,6 +152,32 @@
                 or      r3, r0, ARG2	; \
 		addu	r31, r31, 32
 
+/* This define is similar to CALL, but accepts a function pointer XXX smurph */
+#define CALLP(NAME, ARG1, ARG2)              \
+  		subu	r31, r31, 32	   ; \
+                or.u	r5, r0, hi16(NAME) ; \
+                ld	r4, r5, lo16(NAME) ; \
+		or      r2, r0, ARG1       ; \
+                jsr.n   r4                 ; \
+                or      r3, r0, ARG2	   ; \
+		addu	r31, r31, 32
+
+/* This define can replace the xcr instruction XXX smurph */
+#define XCR(DR, SR, CR)         ; \
+      stcr   r13,    SR0   ; \
+      or      r13, r0, SR     ; \
+                ldcr   DR, CR      ; \
+      stcr   r13, CR      ; \
+      ldcr   r13, SR0
+
+/* This define can be used to debug sub routine returns XXX smurph*/
+#define STORE_R1(varname)               ; \
+      stcr   r13,    SR0   /* r13 now free */   ; \
+      /* save r1 to memory location varname */   ; \
+      or.u   r13, r0,  hi16(varname)         ; \
+      st   r1,  r13, lo16(varname)         ; \
+      ldcr   r13, SR0   /* retore r13   */   
+
 /*
  * SR1 - CPU FLAGS REGISTER
  * XXX clean this when the trap handler is reworked. Among the things
@@ -142,12 +200,14 @@
  *	in a rather precarious state and so special cautions must
  * 	be taken.
  */
-#define FLAG_CPU_FIELD_WIDTH		4	/* must be <= 12 */
-
-#define FLAG_IGNORE_DATA_EXCEPTION	5	/* bit number 5 */
-#define FLAG_INTERRUPT_EXCEPTION	6	/* bit number 6 */
-#define FLAG_ENABLING_FPU		7	/* bit number 7 */
-
+#define FLAG_CPU_FIELD_WIDTH		   4	/* must be <= 12 */
+#define FLAG_IGNORE_DATA_EXCEPTION	5	/* bit number 5  */
+#define FLAG_INTERRUPT_EXCEPTION	   6	/* bit number 6  */
+#define FLAG_ENABLING_FPU		      7	/* bit number 7  */
+#define FLAG_FROM_KERNEL            8  /* bit number 8  */
+#define FLAG_187 		               8	/* bit number 9  */
+#define FLAG_188 		               9	/* bit number 10 */
+#define FLAG_197 		              10	/* bit number 11 */
 
 /* REGister OFFset into the E.F. (exception frame) */
 #define REG_OFF(reg_num)  ((reg_num) * 4) /* (num * sizeof(register int))  */
@@ -202,19 +262,19 @@
 /*
  * Bits for eh_debug.
  */
-#define DEBUG_INTERRUPT_BIT		 0
-#define DEBUG_DATA_BIT			 1
-#define DEBUG_INSTRUCTION_BIT		 2
-#define DEBUG_MISALIGN_BIT		 3
-#define DEBUG_UNIMP_BIT			 4
-#define DEBUG_DIVIDE_BIT		 5
-#define DEBUG_OF_BIT			 6
-#define DEBUG_FPp_BIT			 7
-#define DEBUG_FPi_BIT			 8
-#define DEBUG_SYSCALL_BIT	 	 9
-#define DEBUG_MACHSYSCALL_BIT		10
-#define DEBUG_UNIMPLEMENTED_BIT		11
-#define DEBUG_PRIVILEGE_BIT		12
+#define DEBUG_INTERRUPT_BIT	0
+#define DEBUG_DATA_BIT			1
+#define DEBUG_INSTRUCTION_BIT	2
+#define DEBUG_MISALIGN_BIT		3
+#define DEBUG_UNIMP_BIT			4
+#define DEBUG_DIVIDE_BIT		5
+#define DEBUG_OF_BIT			   6
+#define DEBUG_FPp_BIT			7
+#define DEBUG_FPi_BIT			8
+#define DEBUG_SYSCALL_BIT	 	9
+#define DEBUG_MACHSYSCALL_BIT	10
+#define DEBUG_UNIMPLEMENTED_BIT	11
+#define DEBUG_PRIVILEGE_BIT	12
 #define DEBUG_BOUNDS_BIT		13
 #define DEBUG_OVERFLOW_BIT		14
 #define DEBUG_ERROR_BIT			15
@@ -225,6 +285,10 @@
 #define DEBUG_KDB_BIT			20
 #define DEBUG_JKDB_BIT			21
 #define DEBUG_BUGCALL_BIT		22
+#define DEBUG_NON_MASK_BIT	   23		/* MVME197 Non-Maskable Interrupt */
+#define DEBUG_197_READ_BIT    25    /* MVME198 Data Read Miss (Software Table Searches) */
+#define DEBUG_197_WRITE_BIT   26    /* MVME198 Data Write Miss (Software Table Searches) */
+#define DEBUG_197_INST_BIT    27    /* MVME198 Inst ATC Miss (Software Table Searches) */
 
 #define DEBUG_UNKNOWN_BIT		31
 
@@ -245,11 +309,19 @@
  */
 #define ERRATA__XXX_USR 	1
 
-#if !defined(CMMU_I)
-#define CMMU_I	0xFFF77000
-#endif
-#if !defined(CMMU_D)
-#define CMMU_D	0xFFF7F000
-#endif
+#ifndef CMMU_DEFS
+#define CMMU_DEFS
+#define SBC_CMMU_I		0xFFF77000 	/* Single Board Computer code CMMU */
+#define SBC_CMMU_D		0xFFF7F000 	/* Single Board Computer data CMMU */
+
+#define VME_CMMU_I0		0xFFF7E000 	/* MVME188 code CMMU 0 */
+#define VME_CMMU_I1		0xFFF7D000 	/* MVME188 code CMMU 1 */
+#define VME_CMMU_I2		0xFFF7B000 	/* MVME188 code CMMU 2 */
+#define VME_CMMU_I3		0xFFF77000 	/* MVME188 code CMMU 3 */
+#define VME_CMMU_D0		0xFFF6F000 	/* MVME188 data CMMU 0 */
+#define VME_CMMU_D1		0xFFF5F000 	/* MVME188 data CMMU 1 */
+#define VME_CMMU_D2		0xFFF3F000 	/* MVME188 data CMMU 2 */
+#define VME_CMMU_D3		0xFFF7F000 	/* MVME188 data CMMU 3 */
+#endif /* CMMU_DEFS */
 
 #endif /* __M88K_ASM_H__ */
diff --git a/sys/arch/mvme88k/include/asm_macro.h b/sys/arch/mvme88k/include/asm_macro.h
index 6cd9e4d6a5b..385ce20475d 100644
--- a/sys/arch/mvme88k/include/asm_macro.h
+++ b/sys/arch/mvme88k/include/asm_macro.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: asm_macro.h,v 1.5 1999/02/09 12:49:38 deraadt Exp $ */
+/*	$OpenBSD: asm_macro.h,v 1.6 1999/09/27 20:46:16 smurph Exp $ */
 /*
  * Mach Operating System
  * Copyright (c) 1993-1991 Carnegie Mellon University
@@ -59,13 +59,12 @@ typedef unsigned long m88k_psr_type;
  */
 static inline m88k_psr_type disable_interrupts_return_psr(void)
 {
-    m88k_psr_type temp, oldpsr;
-    asm volatile (
-	"ldcr %0, cr1      \n"
-	"set  %1, %0, 1<1> \n"
-	"stcr %1, cr1      \n"
-	"tcnd ne0, r0, 0     " : "=r" (oldpsr), "=r" (temp));
-    return oldpsr;
+   m88k_psr_type temp, oldpsr;
+   asm volatile ("ldcr %0, cr1" : "=r" (oldpsr));
+   asm volatile ("set  %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp));
+	asm volatile ("stcr %0, cr1" : "=r" (temp));
+	asm volatile ("tcnd ne0, r0, 0");
+   return oldpsr;
 }
 #define disable_interrupt() (void)disable_interrupts_return_psr()
 
@@ -74,7 +73,7 @@ static inline m88k_psr_type disable_interrupts_return_psr(void)
  */
 static inline void set_psr(m88k_psr_type psr)
 {
-    asm volatile ("stcr %0, cr1" :: "r" (psr));
+   asm volatile ("stcr %0, cr1" :: "r" (psr));
 }
 
 /*
@@ -82,12 +81,11 @@ static inline void set_psr(m88k_psr_type psr)
  */
 static inline m88k_psr_type enable_interrupts_return_psr(void)
 {
-    m88k_psr_type temp, oldpsr; /* need a temporary register */
-    asm volatile (
-	"ldcr %0, cr1      \n"
-        "clr  %1, %0, 1<1> \n"
-        "stcr %1, cr1        " : "=r" (oldpsr), "=r" (temp));
-    return oldpsr;
+   m88k_psr_type temp, oldpsr; /* need a temporary register */
+   asm volatile ("ldcr %0, cr1" : "=r" (oldpsr));
+   asm volatile ("clr  %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp));
+	asm volatile ("stcr %0, cr1" : "=r" (temp));
+   return oldpsr;
 }
 #define enable_interrupt() (void)enable_interrupts_return_psr()
 
diff --git a/sys/arch/mvme88k/include/assym.s b/sys/arch/mvme88k/include/assym.s
index e394debb96f..cb53546adaf 100644
--- a/sys/arch/mvme88k/include/assym.s
+++ b/sys/arch/mvme88k/include/assym.s
@@ -11,14 +11,14 @@
 #define	SRUN 2
 #define	VM_PMAP 132
 #define	V_INTR 12
-#define	UPAGES 3
+#define	UPAGES 4
 #define	PGSHIFT 12
-#define	USIZE 12288
+#define	USIZE 16384
 #define	NBPG 4096
-#define	U_PROF 840
-#define	U_PROFSCALE 852
-#define	PCB_ONFAULT 336
-#define	SIZEOF_PCB 344
+#define	U_PROF 864
+#define	U_PROFSCALE 876
+#define	PCB_ONFAULT 360
+#define	SIZEOF_PCB 368
 #define	PCB_USER_STATE 80
 #define	SYS_exit 1
 #define	SYS_execve 59
@@ -30,6 +30,8 @@
 #define EF_EPSR 34
 #define EF_SXIP 35
 #define EF_SFIP 37
+#define EF_EXIP 35
+#define EF_EFIP 37
 #define EF_SNIP 36
 #define EF_SSBR 38
 #define EF_DMT0 39
@@ -42,6 +44,8 @@
 #define EF_DMD2 46
 #define EF_DMA2 47
 #define EF_FPECR 48
+#define EF_FPCR 33
+#define EF_FPSR 32
 #define EF_FPHS1 49
 #define EF_FPLS1 50
 #define EF_FPHS2 51
@@ -56,8 +60,15 @@
 #define EF_RET 60
 #define EF_IPFSR 61
 #define EF_DPFSR 62
-#define EF_NREGS 64
-#define SIZEOF_EF 256
+#define EF_DSR 63
+#define EF_DLAR 64
+#define EF_DPAR 65
+#define EF_ISR 63
+#define EF_ILAR 67
+#define EF_IPAR 68
+#define EF_SRX 62
+#define EF_NREGS 70
+#define SIZEOF_EF 280
 #define PCB_PC 0
 #define PCB_IPL 4
 #define PCB_R14 8
diff --git a/sys/arch/mvme88k/include/autoconf.h b/sys/arch/mvme88k/include/autoconf.h
index 872eee08278..32896fb5356 100644
--- a/sys/arch/mvme88k/include/autoconf.h
+++ b/sys/arch/mvme88k/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.h,v 1.5 1999/02/09 06:36:25 smurph Exp $ */
+/*	$OpenBSD: autoconf.h,v 1.6 1999/09/27 20:46:17 smurph Exp $ */
 /*
  * Copyright (c) 1999, Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -37,18 +37,6 @@
 #ifndef _MVME88K_AUTOCONF_H_
 #define _MVME88K_AUTOCONF_H_
 
-#if 0
-struct confargs {
-	int	ca_bustype;
-	caddr_t	ca_parent;
-	caddr_t	ca_vaddr;
-	caddr_t	ca_paddr;
-#define ca_len ca_size
-	int	ca_size;
-	int	ca_ipl;
-	int	ca_vec;
-};
-#else
 struct confargs {
 	int	ca_bustype;
 	void	*ca_vaddr;
@@ -60,26 +48,15 @@ struct confargs {
 	char	*ca_name;
 	void	*ca_master;	/* points to bus-dependent data */
 };
-#endif
-
-#define BUS_MAIN	0
-#define BUS_MC		1
-#define BUS_PCC		2
-#define BUS_PCCTWO	3
-#define BUS_VMES	4
-#define BUS_VMEL	5
 
-#if 0
-/* From mvme68k autoconf.h */
-#define BUS_MAIN	1
-#define BUS_PCC		2	/* VME147 PCC chip */
-#define BUS_MC		3	/* VME162 MC chip */
-#define BUS_PCCTWO	4	/* VME166/167/177 PCC2 chip */
-#define BUS_VMES	5	/* 16 bit VME access */
-#define BUS_VMEL	6	/* 32 bit VME access */
-#define BUS_IP		7	/* VME162 IP module bus */
-
-#endif
+#define BUS_MAIN      0
+#define BUS_MC        1
+#define BUS_PCC       2
+#define BUS_PCCTWO    3
+#define BUS_VMES      4
+#define BUS_VMEL      5
+#define BUS_SYSCON    6
+#define BUS_BUSSWITCH 7
 
 int always_match __P((struct device *, struct cfdata *, void *));
 
diff --git a/sys/arch/mvme88k/include/board.h b/sys/arch/mvme88k/include/board.h
index a42a6968acb..8ac89b00195 100644
--- a/sys/arch/mvme88k/include/board.h
+++ b/sys/arch/mvme88k/include/board.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: board.h,v 1.5 1999/05/29 04:41:45 smurph Exp $ */
+/*	$OpenBSD: board.h,v 1.6 1999/09/27 20:46:17 smurph Exp $ */
 /*
  * Copyright (c) 1996 Nivas Madhur
  * All rights reserved.
@@ -61,51 +61,63 @@
 #	define U(num)	num/**/U
 #  endif
 #endif
+#define UDEFINED
 
-#define MAX_CPUS	1		/* no. of CPUs */
-#define MAX_CMMUS	2		/* 2 CMMUs - 1 data and 1 code */
+#define MAX_CPUS	4		/* no. of CPUs */
+#define MAX_CMMUS	8		/* 2 CMMUs per CPU - 1 data and 1 code */
 
 #define SYSV_BASE			U(0x00000000) 	/* system virtual base */
 
 #define MAXU_ADDR			U(0x40000000) 	/* size of user virtual space */
 #define MAXPHYSMEM		U(0x10000000) 	/* max physical memory */
 
-#define BUGROM_START		U(0xFF800000)	/* start of BUG PROM */
-#define BUGROM_SIZE		U(0x003FFFFF)	/* size of BUG PROM */
-#define SRAM_START		U(0xFFE00000)	/* start of sram used by bug */
-#define SRAM_SIZE			U(0x0001FFFF)	/* size of sram */
-#define OBIO_START		U(0xFFF00000)	/* start of local IO */
-#define OBIO_SIZE			U(0x000EFFFF)	/* size of obio space */
-
-#define INT_PRI_LEVEL	U(0xFFF4203E)	/* interrupt priority level */
-#define INT_MASK_LEVEL	U(0xFFF4203F)	/* interrupt mask level */
-
-#define LOCAL_IO_DEVS	U(0xFFF00000)	/* local IO devices */
-
 #define VMEA16				U(0xFFFF0000)	/* VMEbus A16 */
 #define VMEA16_SIZE		U(0x0000EFFF)	/* VMEbus A16 size */
 #define VMEA32D16    	U(0xFF000000)  /* VMEbus A32/D16 */
 #define VMEA32D16_SIZE	U(0x007FFFFF)	/* VMEbus A32/D16 size */
 
-#define PCC2_ADDR			U(0xFFF42000)	/* PCCchip2 Regs */
-#define MEM_CTLR			U(0xFFF43000)	/* MEMC040 mem controller */
-#define SCC_ADDR			U(0xFFF45000) 	/* Cirrus Chip */
-#define LANCE_ADDR		U(0xFFF46000) 	/* 82596CA */
-#define SCSI_ADDR			U(0xFFF47000) 	/* NCR 710 address */
-#define NCR710_SIZE		U(0x00000040) 	/* NCR 710 size */
-#define MK48T08_ADDR		U(0xFFFC0000) 	/* BBRAM, TOD */
-
-#define	TOD_CAL_CTL		U(0xFFFC1FF8) 	/* calendar control register */
-#define TOD_CAL_SEC		U(0xFFFC1FF9) 	/* seconds */
-#define TOD_CAL_MIN		U(0xFFFC1FFA) 	/* minutes */
-#define TOD_CAL_HOUR		U(0xFFFC1FFB) 	/* hours */
-#define TOD_CAL_DOW		U(0xFFFC1FFC) 	/* Day Of the Week */
-#define TOD_CAL_DAY		U(0xFFFC1FFD) 	/* days */
-#define TOD_CAL_MON		U(0xFFFC1FFE) 	/* months */
-#define TOD_CAL_YEAR		U(0xFFFC1FFF) 	/* years */
 
-#define CMMU_I				U(0xFFF77000) 	/* CMMU instruction  */
-#define CMMU_D				U(0xFFF7F000) 	/* CMMU data */
+/* These need to be here because of the way m18x_cmmu.c 
+   handles the CMMU's. */
 #define CMMU_SIZE			0x1000
 
+#ifndef CMMU_DEFS
+#define CMMU_DEFS
+#define SBC_CMMU_I		U(0xFFF77000) 	/* Single Board Computer code CMMU */
+#define SBC_CMMU_D		U(0xFFF7F000) 	/* Single Board Computer data CMMU */
+
+#define VME_CMMU_I0		U(0xFFF7E000) 	/* MVME188 code CMMU 0 */
+#define VME_CMMU_I1		U(0xFFF7D000) 	/* MVME188 code CMMU 1 */
+#define VME_CMMU_I2		U(0xFFF7B000) 	/* MVME188 code CMMU 2 */
+#define VME_CMMU_I3		U(0xFFF77000) 	/* MVME188 code CMMU 3 */
+#define VME_CMMU_D0		U(0xFFF6F000) 	/* MVME188 data CMMU 0 */
+#define VME_CMMU_D1		U(0xFFF5F000) 	/* MVME188 data CMMU 1 */
+#define VME_CMMU_D2		U(0xFFF3F000) 	/* MVME188 data CMMU 2 */
+#define VME_CMMU_D3		U(0xFFF7F000) 	/* MVME188 data CMMU 3 */
+#endif /* CMMU_DEFS */
+
+/* These are the hardware exceptions. */
+#define INT_BIT      0x1		/* interrupt exception		*/
+#define IACC_BIT     0x2		/* instruction access exception	*/
+#define DACC_BIT     0x4		/* data access exception	*/
+#define MACC_BIT     0x8		/* misaligned access exception	*/
+#define UOPC_BIT     0x10		/* unimplemented opcode exception*/
+#define PRIV_BIT     0x20		/* priviledge violation exception*/
+#define BND_BIT      0x40		/* bounds check violation	*/
+#define IDE_BIT      0x80		/* illegal integer divide	*/
+#define IOV_BIT      0x100		/* integer overflow exception	*/
+#define ERR_BIT      0x200		/* error exception		*/
+#define FPUP_BIT     0x400		/* FPU precise exception	*/
+#define FPUI_BIT     0x800		/* FPU imprecise exception	*/
+
+#if defined(MVME187) || defined(MVME197)
+#include <machine/mvme1x7.h>
+#endif
+
+#ifdef MVME188
+#include <machine/mvme188.h>
+#endif
+
 #endif /* _MACHINE_BOARD_H */
+
+
diff --git a/sys/arch/mvme88k/include/cmmu.h b/sys/arch/mvme88k/include/cmmu.h
new file mode 100644
index 00000000000..7a8a2a3e803
--- /dev/null
+++ b/sys/arch/mvme88k/include/cmmu.h
@@ -0,0 +1,130 @@
+/*	$OpenBSD: cmmu.h,v 1.1 1999/09/27 20:46:17 smurph Exp $ */
+/* 
+ * Mach Operating System
+ * Copyright (c) 1993-1992 Carnegie Mellon University
+ * All Rights Reserved.
+ * 
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ * 
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ * 
+ * any improvements or extensions that they make and grant Carnegie Mellon 
+ * the rights to redistribute these changes.
+ */
+/*
+ * HISTORY
+ * 
+ */
+
+
+#ifndef	__MACHINE_CMMU_H__
+#define	__MACHINE_CMMU_H__
+
+#ifndef ASSEMBLER
+#include <machine/mmu.h>		 /* batc_template_t */
+#endif
+
+#include <machine/board.h>
+
+/* Area Description */
+#define AREA_D_WT	0x00000200	/* write through */
+#define AREA_D_G	0x00000080	/* global */
+#define AREA_D_CI	0x00000040	/* cache inhibit */
+#define AREA_D_TE	0x00000001	/* translation enable */
+
+/* Segment Description */
+#define SEG_D_WT	0x00000200	/* write through */
+#define SEG_D_SP	0x00000100	/* supervisor protection */
+#define SEG_D_G		0x00000080	/* global */
+#define SEG_D_CI	0x00000040	/* cache inhibit */
+#define SEG_D_WP	0x00000004	/* write protect */
+#define SEG_D_V		0x00000001	/* valid */
+
+/*
+ * Flags for cmmu_flush_tlb
+ */
+#define FLUSH_KERNEL    1
+#define FLUSH_USER      0
+#define FLUSH_ALL       ((vm_offset_t)~0)
+
+
+#ifndef	ASSEMBLER
+/*
+ * Prototypes and stuff for cmmu.c.
+ */
+extern unsigned cpu_sets[MAX_CPUS];
+extern int cpu_cmmu_ratio;
+extern unsigned ncpus;
+extern unsigned cache_policy;
+
+#ifdef CMMU_DEBUG
+ void show_apr(unsigned value);
+ void show_sctr(unsigned value);
+#endif
+
+/*
+ * Prototypes from "mvme88k/mvme88k/cmmu.c"
+ */
+unsigned cmmu_cpu_number(void);
+#if !DDB
+static
+#endif /* !DDB */
+unsigned cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
+unsigned cmmu_get_idr(unsigned data);
+void cmmu_init(void);
+void cmmu_shutdown_now(void);
+void cmmu_parity_enable(void);
+#if !DDB
+static
+#endif /* !DDB */
+void cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
+void cmmu_set_sapr(unsigned ap);
+void cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
+void cmmu_set_uapr(unsigned ap);
+void cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
+void cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
+void cmmu_flush_cache(vm_offset_t physaddr, int size);
+void cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
+void cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
+void cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
+void cmmu_flush_data_cache(vm_offset_t physaddr, int size);
+
+void cmmu_pmap_activate(
+    unsigned cpu,
+    unsigned uapr,
+    batc_template_t i_batc[BATC_MAX],
+    batc_template_t d_batc[BATC_MAX]);
+
+void cmmu_flush_remote_tlb(
+	unsigned cpu,
+	unsigned kernel,
+	vm_offset_t vaddr,
+	int size);
+
+void cmmu_set_batc_entry(
+     unsigned cpu,
+     unsigned entry_no,
+     unsigned data,   /* 1 = data, 0 = instruction */
+     unsigned value);  /* the value to stuff into the batc */
+
+void cmmu_set_pair_batc_entry(
+     unsigned cpu,
+     unsigned entry_no,
+     unsigned value);  /* the value to stuff into the batc */
+
+#endif	/* ASSEMBLER */
+
+#endif	/* __MACHINE_CMMU_H__ */
diff --git a/sys/arch/mvme88k/include/cpu.h b/sys/arch/mvme88k/include/cpu.h
index 0f89b8fd389..d2146c1156b 100644
--- a/sys/arch/mvme88k/include/cpu.h
+++ b/sys/arch/mvme88k/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.5 1999/02/09 06:36:26 smurph Exp $ */
+/*	$OpenBSD: cpu.h,v 1.6 1999/09/27 20:46:17 smurph Exp $ */
 /*
  * Copyright (c) 1996 Nivas Madhur
  * Copyright (c) 1992, 1993
@@ -180,5 +180,18 @@ struct switchframe {
 	void	*sf_proc;		/* proc pointer */
 };
 
+/* This struct defines the machine dependant function pointers */
+
+struct funcp {
+	void (*clock_init_func)();      /* interval clock init function */
+	void (*statclock_init_func)();  /* statistics clock init function */
+	void (*delayclock_init_func)(); /* delay clock init function */
+	void (*delay_func)();           /* delay clock function */
+   void (*interrupt_func)();       /* interrupt func */
+   void (*fp_precise_func)();      /* floating point precise function */
+};
+
+extern struct funcp mdfp;
+
 #endif /* _KERNEL */
 #endif /* _CPU_H_ */
diff --git a/sys/arch/mvme88k/include/cpu_number.h b/sys/arch/mvme88k/include/cpu_number.h
new file mode 100644
index 00000000000..e26ddfe6eb4
--- /dev/null
+++ b/sys/arch/mvme88k/include/cpu_number.h
@@ -0,0 +1,48 @@
+/* 
+ * Mach Operating System
+ * Copyright (c) 1993-1992 Carnegie Mellon University
+ * All Rights Reserved.
+ * 
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ * 
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ * 
+ * any improvements or extensions that they make and grant Carnegie Mellon 
+ * the rights to redistribute these changes.
+ */
+
+#ifndef	_M88K_CPU_NUMBER_
+#define _M88K_CPU_NUMBER_
+ 
+#ifdef	KERNEL
+#include <machine/param.h>
+extern unsigned number_cpus;
+#define cpu_number() 0
+
+#if 0 /* This seems to not work correctly. Hmm.... smurph */
+unsigned cpu_number(void);
+static inline unsigned cpu_number(void)
+{
+	unsigned cpu;
+   extern int cputyp;
+	if (cputyp != CPU_188 || number_cpus == 1) return 0;
+   asm("ldcr %0, cr18" : "=r" (cpu));
+	asm("clr  %0, %0, 0<4>" : "=r" (cpu));
+	return (cpu & 3);
+}
+#endif /* 0 */
+#endif /* KERNEL */
+#endif /* _M88K_CPU_NUMBER_ */
diff --git a/sys/arch/mvme88k/include/cpus.h b/sys/arch/mvme88k/include/cpus.h
index 7724aaff5e6..d41e7211469 100644
--- a/sys/arch/mvme88k/include/cpus.h
+++ b/sys/arch/mvme88k/include/cpus.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpus.h,v 1.4 1999/02/09 06:36:26 smurph Exp $ */
+/*	$OpenBSD: cpus.h,v 1.5 1999/09/27 20:46:17 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
@@ -40,26 +40,26 @@
  */
 #ifndef ASSEMBLER
 union cpupid {
-    unsigned cpupid;
-    struct {
-	unsigned
-	    /*empty*/:16,
-	    arc:8,
-	    version:7,
-	    master:1;
-    } m88100;
-    struct {
-	unsigned
-	    id:8,
-	    type:3,
-	    version:5,
-	    /*empty*/:16;
-    } m88200;
+   unsigned cpupid;
+   struct {
+      unsigned
+      /*empty*/:16,
+      arc:8,
+      version:7,
+      master:1;
+   } m88100;
+   struct {
+      unsigned
+      id:8,
+      type:3,
+      version:5,
+      /*empty*/:16;
+   } m88200;
 };
 #endif ASSEMBLER
 
-#define	M88100		0
-#define M88200		5
-#define M88204		6
+#define M88100 0
+#define M88200 5
+#define M88204 6
 
 #endif  _M88K_CPUS_
diff --git a/sys/arch/mvme88k/include/exception_vectors.h b/sys/arch/mvme88k/include/exception_vectors.h
index 33cc037c2e5..29a2f4fe731 100644
--- a/sys/arch/mvme88k/include/exception_vectors.h
+++ b/sys/arch/mvme88k/include/exception_vectors.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: exception_vectors.h,v 1.5 1999/02/09 06:36:26 smurph Exp $ */
+/*	$OpenBSD: exception_vectors.h,v 1.6 1999/09/27 20:46:17 smurph Exp $ */
 /*
  * Mach Operating System
  * Copyright (c) 1991, 1992 Carnegie Mellon University
@@ -25,9 +25,10 @@
  * any improvements or extensions that they make and grant Carnegie the
  * rights to redistribute these changes.
  */
+
+#define UNDEFINED PREDEFINED_BY_ROM
 #ifndef UNDEFINED
 # define UNDEFINED _unknown_handler
-/* vector 0x00 (#0)     word   _address_handler */
 #endif
 /* vector 0x00 (#0)   */  word   _reset_handler
 /* vector 0x01 (#1)   */  word   _interrupt_handler
@@ -166,3 +167,4 @@
 /* vector 0x85 (#133) */  word   user_raw_putstr /* for USER raw_printf() */
 /* vector 0x85 (#134) */  word   user_raw_xpr 	 /* for USER raw_xpr() */
 #endif
+
diff --git a/sys/arch/mvme88k/include/exception_vectors2.h b/sys/arch/mvme88k/include/exception_vectors2.h
new file mode 100644
index 00000000000..6cc623cd816
--- /dev/null
+++ b/sys/arch/mvme88k/include/exception_vectors2.h
@@ -0,0 +1,165 @@
+/*	$OpenBSD: exception_vectors2.h,v 1.1 1999/09/27 20:46:17 smurph Exp $ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991, 1992 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+/*#define M197_UNDEFINED PREDEFINED_BY_ROM*/
+#ifndef M197_M197_UNDEFINED
+#define M197_UNDEFINED _m197_unknown_handler
+#endif
+/* vector 0x00 (#0)   */  word   _m197_reset_handler
+/* vector 0x01 (#1)   */  word   _m197_interrupt_handler
+/* vector 0x02 (#2)   */  word   _m197_instruction_access_handler
+/* vector 0x03 (#3)   */  word   _m197_data_exception_handler
+/* vector 0x04 (#4)   */  word   _m197_misaligned_handler
+/* vector 0x05 (#5)   */  word   _m197_unimplemented_handler
+/* vector 0x06 (#6)   */  word   _m197_privilege_handler
+/* vector 0x07 (#7)   */  word   _m197_bounds_handler
+/* vector 0x08 (#8)   */  word   _m197_divide_handler
+/* vector 0x09 (#9)   */  word   _m197_overflow_handler
+/* vector 0x0a (#10)  */  word   _m197_error_handler
+/* vector 0x0b (#11)  */  word   _m197_nonmaskable
+/* vector 0x0c (#12)  */  word   _m197_data_read_miss
+/* vector 0x0d (#13)  */  word   _m197_data_write_miss
+/* vector 0x0e (#14)  */  word   _m197_inst_atc_miss
+/* vector 0x0f (#15)  */  word   _m197_trace
+/* vector 0x10 (#16)  */  word   M197_UNDEFINED
+/* vector 0x11 (#17)  */  word   M197_UNDEFINED
+/* vector 0x12 (#18)  */  word   M197_UNDEFINED
+/* vector 0x13 (#19)  */  word   M197_UNDEFINED
+/* vector 0x14 (#20)  */  word   M197_UNDEFINED
+/* vector 0x15 (#21)  */  word   M197_UNDEFINED
+/* vector 0x16 (#22)  */  word   M197_UNDEFINED
+/* vector 0x17 (#23)  */  word   M197_UNDEFINED
+/* vector 0x18 (#24)  */  word   M197_UNDEFINED
+/* vector 0x19 (#25)  */  word   M197_UNDEFINED
+/* vector 0x1a (#26)  */  word   M197_UNDEFINED
+/* vector 0x1b (#27)  */  word   M197_UNDEFINED
+/* vector 0x1c (#28)  */  word   M197_UNDEFINED
+/* vector 0x1d (#29)  */  word   M197_UNDEFINED
+/* vector 0x1e (#30)  */  word   M197_UNDEFINED
+/* vector 0x1f (#31)  */  word   M197_UNDEFINED
+/* vector 0x20 (#32)  */  word   M197_UNDEFINED
+/* vector 0x21 (#33)  */  word   M197_UNDEFINED
+/* vector 0x22 (#34)  */  word   M197_UNDEFINED
+/* vector 0x23 (#35)  */  word   M197_UNDEFINED
+/* vector 0x24 (#36)  */  word   M197_UNDEFINED
+/* vector 0x25 (#37)  */  word   M197_UNDEFINED
+/* vector 0x26 (#38)  */  word   M197_UNDEFINED
+/* vector 0x27 (#39)  */  word   M197_UNDEFINED
+/* vector 0x28 (#40)  */  word   M197_UNDEFINED
+/* vector 0x29 (#41)  */  word   M197_UNDEFINED
+/* vector 0x2a (#42)  */  word   M197_UNDEFINED
+/* vector 0x2b (#43)  */  word   M197_UNDEFINED
+/* vector 0x2c (#44)  */  word   M197_UNDEFINED
+/* vector 0x2d (#45)  */  word   M197_UNDEFINED
+/* vector 0x2e (#46)  */  word   M197_UNDEFINED
+/* vector 0x2f (#47)  */  word   M197_UNDEFINED
+/* vector 0x30 (#48)  */  word   M197_UNDEFINED
+/* vector 0x31 (#49)  */  word   M197_UNDEFINED
+/* vector 0x32 (#50)  */  word   M197_UNDEFINED
+/* vector 0x33 (#51)  */  word   M197_UNDEFINED
+/* vector 0x34 (#52)  */  word   M197_UNDEFINED
+/* vector 0x35 (#53)  */  word   M197_UNDEFINED
+/* vector 0x36 (#54)  */  word   M197_UNDEFINED
+/* vector 0x37 (#55)  */  word   M197_UNDEFINED
+/* vector 0x38 (#56)  */  word   M197_UNDEFINED
+/* vector 0x39 (#57)  */  word   M197_UNDEFINED
+/* vector 0x3a (#58)  */  word   M197_UNDEFINED
+/* vector 0x3b (#59)  */  word   M197_UNDEFINED
+/* vector 0x3c (#60)  */  word   M197_UNDEFINED
+/* vector 0x3d (#61)  */  word   M197_UNDEFINED
+/* vector 0x3e (#62)  */  word   M197_UNDEFINED
+/* vector 0x3f (#63)  */  word   M197_UNDEFINED
+/* vector 0x40 (#64)  */  word   M197_UNDEFINED
+/* vector 0x41 (#65)  */  word   M197_UNDEFINED
+/* vector 0x42 (#66)  */  word   M197_UNDEFINED
+/* vector 0x43 (#67)  */  word   M197_UNDEFINED
+/* vector 0x44 (#68)  */  word   M197_UNDEFINED
+/* vector 0x45 (#69)  */  word   M197_UNDEFINED
+/* vector 0x46 (#70)  */  word   M197_UNDEFINED
+/* vector 0x47 (#71)  */  word   M197_UNDEFINED
+/* vector 0x48 (#72)  */  word   M197_UNDEFINED
+/* vector 0x49 (#73)  */  word   M197_UNDEFINED
+/* vector 0x4a (#74)  */  word   M197_UNDEFINED
+/* vector 0x4b (#75)  */  word   M197_UNDEFINED
+/* vector 0x4c (#76)  */  word   M197_UNDEFINED
+/* vector 0x4d (#77)  */  word   M197_UNDEFINED
+/* vector 0x4e (#78)  */  word   M197_UNDEFINED
+/* vector 0x4f (#79)  */  word   M197_UNDEFINED
+/* vector 0x50 (#80)  */  word   M197_UNDEFINED
+/* vector 0x51 (#81)  */  word   M197_UNDEFINED
+/* vector 0x52 (#82)  */  word   M197_UNDEFINED
+/* vector 0x53 (#83)  */  word   M197_UNDEFINED
+/* vector 0x54 (#84)  */  word   M197_UNDEFINED
+/* vector 0x55 (#85)  */  word   M197_UNDEFINED
+/* vector 0x56 (#86)  */  word   M197_UNDEFINED
+/* vector 0x57 (#87)  */  word   M197_UNDEFINED
+/* vector 0x58 (#88)  */  word   M197_UNDEFINED
+/* vector 0x59 (#89)  */  word   M197_UNDEFINED
+/* vector 0x5a (#90)  */  word   M197_UNDEFINED
+/* vector 0x5b (#91)  */  word   M197_UNDEFINED
+/* vector 0x5c (#92)  */  word   M197_UNDEFINED
+/* vector 0x5d (#93)  */  word   M197_UNDEFINED
+/* vector 0x5e (#94)  */  word   M197_UNDEFINED
+/* vector 0x5f (#95)  */  word   M197_UNDEFINED
+/* vector 0x60 (#96)  */  word   M197_UNDEFINED
+/* vector 0x61 (#97)  */  word   M197_UNDEFINED
+/* vector 0x62 (#98)  */  word   M197_UNDEFINED
+/* vector 0x63 (#99)  */  word   M197_UNDEFINED
+/* vector 0x64 (#100) */  word   M197_UNDEFINED
+/* vector 0x65 (#101) */  word   M197_UNDEFINED
+/* vector 0x66 (#102) */  word   M197_UNDEFINED
+/* vector 0x67 (#103) */  word   M197_UNDEFINED
+/* vector 0x68 (#104) */  word   M197_UNDEFINED
+/* vector 0x69 (#105) */  word   M197_UNDEFINED
+/* vector 0x6a (#106) */  word   M197_UNDEFINED
+/* vector 0x6b (#107) */  word   M197_UNDEFINED
+/* vector 0x6c (#108) */  word   M197_UNDEFINED
+/* vector 0x6d (#109) */  word   M197_UNDEFINED
+/* vector 0x6e (#110) */  word   M197_UNDEFINED
+/* vector 0x6f (#111) */  word   M197_UNDEFINED
+/* vector 0x70 (#112) */  word   M197_UNDEFINED
+/* vector 0x71 (#113) */  word   M197_UNDEFINED
+/* vector 0x72 (#114) */  word   _m197_fp_precise_handler
+/* vector 0x73 (#115) */  word   M197_UNDEFINED
+/* vector 0x74 (#116) */  word   _m197_unimplemented_handler
+/* vector 0x75 (#117) */  word   M197_UNDEFINED
+/* vector 0x76 (#118) */  word   _m197_unimplemented_handler
+/* vector 0x77 (#119) */  word   M197_UNDEFINED
+/* vector 0x78 (#120) */  word   _m197_unimplemented_handler
+/* vector 0x79 (#121) */  word   M197_UNDEFINED
+/* vector 0x7a (#122) */  word   _m197_unimplemented_handler
+/* vector 0x7b (#123) */  word   M197_UNDEFINED
+/* vector 0x7c (#124) */  word   _m197_unimplemented_handler
+/* vector 0x7d (#125) */  word   M197_UNDEFINED
+/* vector 0x7e (#126) */  word   _m197_unimplemented_handler
+/* vector 0x7f (#127) */  word   M197_UNDEFINED
+/* vector 0x80 (#128) */  word   _m197_syscall_handler
+/* vector 0x81 (#129) */  word   _m197_syscall_handler
+/* vector 0x82 (#130) */  word   _m197_break
+/* vector 0x83 (#131) */  word   _m197_trace
+/* vector 0x84 (#132) */  word   _m197_entry
+
diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h
new file mode 100644
index 00000000000..9d15b060fc0
--- /dev/null
+++ b/sys/arch/mvme88k/include/m88110.h
@@ -0,0 +1,229 @@
+/*	$OpenBSD: m88110.h,v 1.1 1999/09/27 20:46:18 smurph Exp $ */
+
+#ifndef	__MACHINE_M88110_H__
+#define	__MACHINE_M88110_H__
+
+#ifndef ASSEMBLER
+# include <machine/mmu.h>		 /* batc_template_t */
+#endif
+
+#include <machine/board.h>
+#include <machine/cmmu.h>
+#include <vm/vm.h>
+
+/*
+ *	88110 CMMU definitions
+ */
+#define CMMU_ICMD 0
+#define CMMU_ICTL 1
+#define CMMU_ISAR 2
+#define CMMU_ISAP 3
+#define CMMU_IUAP 4
+#define CMMU_IIR  5
+#define CMMU_IBP  6
+#define CMMU_IPPU 7
+#define CMMU_IPPL 8
+#define CMMU_ISR  9
+#define CMMU_ILAR 10
+#define CMMU_IPAR 11
+
+#define CMMU_DCMD 12
+#define CMMU_DCTL 13
+#define CMMU_DSAR 14
+#define CMMU_DSAP 15
+#define CMMU_DUAP 16
+#define CMMU_DIR  17
+#define CMMU_DBP  18
+#define CMMU_DPPU 19
+#define CMMU_DPPL 20
+#define CMMU_DSR  21
+#define CMMU_DLAR 22
+#define CMMU_DPAR 23
+
+#define CMMU_ICMD_INV_ITIC       0x001    /* Invalidate Inst Cache & TIC */
+#define CMMU_ICMD_INV_TIC        0x002    /* Invalidate TIC */
+#define CMMU_ICMD_INV_LINE       0x005    /* Invalidate Inst Cache Line */
+#define CMMU_ICMD_PRB_SUPR       0x008    /* MMU Probe Supervisor */
+#define CMMU_ICMD_PRB_USER       0x009    /* MMU Probe User */
+#define CMMU_ICMD_INV_SATC       0x00A    /* Invalidate All Supervisor ATCs */
+#define CMMU_ICMD_INV_UATC       0x00B    /* Invalidate All User ATCs */
+
+#define CMMU_ICTL_DID            0x8000   /* Double instruction disable */
+#define CMMU_ICTL_PREN           0x4000   /* Branch Prediction Enable */
+#define CMMU_ICTL_FRZ0           0x0100   /* Inst Cache Freeze Bank 0 */
+#define CMMU_ICTL_FRZ1           0x0080   /* Inst Cache Freeze Bank 1 */
+#define CMMU_ICTL_HTEN           0x0040   /* Hardware Table Search Enable */
+#define CMMU_ICTL_MEN            0x0020   /* Inst MMU Enable */
+#define CMMU_ICTL_BEN            0x0004   /* TIC Cache Enable */
+#define CMMU_ICTL_CEN            0x0001   /* Inst Cache Enable */
+
+#define CMMU_ISR_TBE             0x200000 /* Table Search Bus Error */
+#define CMMU_ISR_SI              0x100000 /* Segment Fault*/
+#define CMMU_ISR_PI              0x080000 /* Page Fault */
+#define CMMU_ISR_SP              0x040000 /* Supervisor Protection Violation */
+#define CMMU_ISR_PH              0x000800 /* PATC Hit */
+#define CMMU_ISR_BH              0x000400 /* BATC Hit */
+#define CMMU_ISR_SU              0x000200 /* Supervisor Bit */
+#define CMMU_ISR_BE              0x000001 /* Bus Error */
+
+#define CMMU_DCMD_FLUSH_PG       0x000    /* Flush Data Cache Page (sync) */
+#define CMMU_DCMD_INV_ALL        0x001    /* Invalidate Data Cache All */
+#define CMMU_DCMD_FLUSH_ALL      0x002    /* Flush Data Cache All (sync) */
+#define CMMU_DCMD_FLUSH_ALL_INV  0x003    /* Flush Data Cache All (sync & inval) */
+#define CMMU_DCMD_FLUSH_PG_INV   0x004    /* Flush Data Cache Page (sync & inval) */
+#define CMMU_DCMD_INV_LINE       0x005    /* Invalidate Data Cache Line */
+#define CMMU_DCMD_FLUSH_LINE     0x006    /* Flush Data Cache Line (sync)*/
+#define CMMU_DCMD_FLUSH_LINE_INV 0x007    /* Flush Data Cache Line (sync & inval)*/
+#define CMMU_DCMD_PRB_SUPR       0x008    /* MMU Probe Supervisor */
+#define CMMU_DCMD_PRB_USER       0x009    /* MMU Probe User */
+#define CMMU_DCMD_INV_SATC       0x00A    /* Invalidate All Supervisor ATCs */
+#define CMMU_DCMD_INV_UATC       0x00B    /* Invalidate All User ATCs */
+
+#define CMMU_DCTL_XMEM           0x2000   /* store -> load sequence */
+#define CMMU_DCTL_DEN            0x1000   /* Decoupled Cache Access Enable */
+#define CMMU_DCTL_FWT            0x0800   /* Force Write Through */
+#define CMMU_DCTL_BPEN1          0x0400   /* Break Point Enable 1 */
+#define CMMU_DCTL_BPEN0          0x0200   /* Break Point Enable 0 */
+#define CMMU_DCTL_FRZ0           0x0100   /* Data Cache Freeze Bank 0 */
+#define CMMU_DCTL_FRZ1           0x0080   /* Data Cache Freeze Bank 1 */
+#define CMMU_DCTL_HTEN           0x0040   /* Hardware Table Search Enable */
+#define CMMU_DCTL_MEN            0x0020   /* Data MMU Enable */
+#define CMMU_DCTL_SEN            0x0002   /* Data Cache Snoop Enable */
+#define CMMU_DCTL_CEN            0x0001   /* Data Cache Enable */
+
+#define CMMU_DSR_TBE             0x200000 /* Table Search Bus Error */
+#define CMMU_DSR_SI              0x100000 /* Segment Fault*/
+#define CMMU_DSR_PI              0x080000 /* Page Fault */
+#define CMMU_DSR_SP              0x040000 /* Supervisor Protection Violation */
+#define CMMU_DSR_WE              0x020000 /* Write Protection Violation */
+#define CMMU_DSR_BPE             0x010000 /* Break Point Exception */
+#define CMMU_DSR_PH              0x000800 /* PATC Hit */
+#define CMMU_DSR_BH              0x000400 /* BATC Hit */
+#define CMMU_DSR_SU              0x000200 /* Supervisor Bit */
+#define CMMU_DSR_RW              0x000100 /* Read Bit */
+#define CMMU_DSR_CP              0x000004 /* Copyback Error */
+#define CMMU_DSR_WA              0x000002 /* Write-Allocate Bus Error */
+#define CMMU_DSR_BE              0x000001 /* Bus Error */
+
+#define CMMU_READ 0
+#define CMMU_WRITE 1
+#define CMMU_DATA 1
+#define CMMU_INST 0
+
+#ifndef	ASSEMBLER
+/*
+ * Prototypes from "mvme88k/mvme88k/m197_cmmu.c"
+ */
+
+#ifdef CMMU_DEBUG
+ void m197_show_apr(unsigned value);
+ void m197_show_sctr(unsigned value);
+#endif
+
+unsigned m197_cmmu_cpu_number(void);
+#if !DDB
+static
+#endif /* !DDB */
+unsigned m197_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
+unsigned m197_cmmu_get_idr(unsigned data);
+void m197_cmmu_init(void);
+void m197_cmmu_shutdown_now(void);
+void m197_cmmu_parity_enable(void);
+#if !DDB
+static
+#endif /* !DDB */
+void m197_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
+void m197_cmmu_set_sapr(unsigned ap);
+void m197_cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
+void m197_cmmu_set_uapr(unsigned ap);
+void m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
+void m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
+void m197_cmmu_flush_cache(vm_offset_t physaddr, int size);
+void m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
+void m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
+void m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
+void m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size);
+
+void m197_cmmu_pmap_activate(
+    unsigned cpu,
+    unsigned uapr,
+    batc_template_t i_batc[BATC_MAX],
+    batc_template_t d_batc[BATC_MAX]);
+
+void m197_cmmu_flush_remote_tlb(
+	unsigned cpu,
+	unsigned kernel,
+	vm_offset_t vaddr,
+	int size);
+
+void m197_cmmu_set_batc_entry(
+     unsigned cpu,
+     unsigned entry_no,
+     unsigned data,   /* 1 = data, 0 = instruction */
+     unsigned value);    /* the value to stuff into the batc */
+
+void m197_cmmu_set_pair_batc_entry(
+     unsigned cpu,
+     unsigned entry_no,
+     unsigned value);    /* the value to stuff into the batc */
+
+int m197_table_search(
+     pmap_t map, 
+     vm_offset_t virt, 
+     int write, 
+     int user, int data);
+
+void set_icmd (unsigned value);
+void set_ictl (unsigned value);
+void set_isar (unsigned value);
+void set_isap (unsigned value);
+void set_iuap (unsigned value);
+void set_iir  (unsigned value);
+void set_ibp  (unsigned value);
+void set_ippu (unsigned value);
+void set_ippl (unsigned value);
+void set_isr  (unsigned value);
+void set_ilar (unsigned value);
+void set_ipar (unsigned value);
+void set_dcmd (unsigned value);
+void set_dctl (unsigned value);
+void set_dsar (unsigned value);
+void set_dsap (unsigned value);
+void set_duap (unsigned value);
+void set_dir  (unsigned value);
+void set_dbp  (unsigned value);
+void set_dppu (unsigned value);
+void set_dppl (unsigned value);
+void set_dsr  (unsigned value);
+void set_dlar (unsigned value);
+void set_dpar (unsigned value);
+
+/* get routines */
+unsigned get_icmd (void);
+unsigned get_ictl (void);
+unsigned get_isar (void);
+unsigned get_isap (void);
+unsigned get_iuap (void);
+unsigned get_iir  (void);
+unsigned get_ibp  (void);
+unsigned get_ippu (void);
+unsigned get_ippl (void);
+unsigned get_isr  (void);
+unsigned get_ilar (void);
+unsigned get_ipar (void);
+unsigned get_dcmd (void);
+unsigned get_dctl (void);
+unsigned get_dsar (void);
+unsigned get_dsap (void);
+unsigned get_duap (void);
+unsigned get_dir  (void);
+unsigned get_dbp  (void);
+unsigned get_dppu (void);
+unsigned get_dppl (void);
+unsigned get_dsr  (void);
+unsigned get_dlar (void);
+unsigned get_dpar (void);
+
+#endif	/* ASSEMBLER */
+
+#endif	/* __MACHINE_M88110_H__ */
diff --git a/sys/arch/mvme88k/include/m882xx.h b/sys/arch/mvme88k/include/m882xx.h
index 70c541ec52f..2898ccff594 100644
--- a/sys/arch/mvme88k/include/m882xx.h
+++ b/sys/arch/mvme88k/include/m882xx.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m882xx.h,v 1.4 1999/02/09 06:36:26 smurph Exp $ */
+/*	$OpenBSD: m882xx.h,v 1.5 1999/09/27 20:46:18 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
@@ -38,6 +38,7 @@
 #endif
 
 #include <machine/board.h>
+#include <machine/cmmu.h>
 
 /*
  *	88200 CMMU definitions
@@ -69,6 +70,23 @@
 #define CMMU_CTP3	0x84C	/* cache tag port 3 */
 #define CMMU_CSSP	0x880	/* cache set status register */
 
+#define CMMU_BWP(_X_) \
+	(((_X_) < 7) ? \
+	 (((_X_) < 6) ? \
+	  (((_X_) < 5) ? \
+	   (((_X_) < 4) ? \
+	    (((_X_) < 3) ? \
+	     (((_X_) < 2) ? \
+	      (((_X_) < 1) ? \
+	       CMMU_BWP0 : \
+	       CMMU_BWP1) : \
+	      CMMU_BWP2) : \
+	     CMMU_BWP3) : \
+	    CMMU_BWP4) : \
+	   CMMU_BWP5) : \
+	  CMMU_BWP6) : \
+	 CMMU_BWP7)
+
 /* 88204 CMMU definitions  */
 #define CMMU_CSSP0	0x880	/* cache set status register */
 #define CMMU_CSSP1	0x890	/* cache set status register */
@@ -112,148 +130,113 @@
 #define CMMU_PFSR_SUPER		6	/* supervisor violation */
 #define CMMU_PFSR_WRITE		7	/* writer violation */
 
-/* Area Description */
-#define AREA_D_WT	0x00000200	/* write through */
-#define AREA_D_G	0x00000080	/* global */
-#define AREA_D_CI	0x00000040	/* cache inhibit */
-#define AREA_D_TE	0x00000001	/* translation enable */
-
-/* Segment Description */
-#define SEG_D_WT	0x00000200	/* write through */
-#define SEG_D_SP	0x00000100	/* supervisor protection */
-#define SEG_D_G		0x00000080	/* global */
-#define SEG_D_CI	0x00000040	/* cache inhibit */
-#define SEG_D_WP	0x00000004	/* write protect */
-#define SEG_D_V		0x00000001	/* valid */
-
-/*
- * Flags for cmmu_flush_tlb
- */
-#define FLUSH_KERNEL    1
-#define FLUSH_USER      0
-#define FLUSH_ALL       ((vm_offset_t)~0)
-
-
 #ifndef	ASSEMBLER
-/*
- * This file defines the data structures for the mmu.
- * One major data structure, the page descriptor, is not defined here
- * but rather in pte.h as struct pte.
- */
-
-struct area_d {		/* area descriptor */
-    unsigned
-	ad_addr:20,	/* segment table base address */
-	       : 2,
-	ad_wt  : 1,	/* write through */
-	       : 1,
-	ad_g   : 1,	/* global */
-	ad_ci  : 1,	/* cache inhibit */
-	       : 5,
-	ad_te  : 1;	/* translation enable */
-};
-
-struct segment_d {	/* segment descriptor */
-    unsigned
-	sd_addr:20,	/* page table base address */
-	       : 2,
-	sd_wt  : 1,	/* write through */ 
-	sd_sp  : 1,	/* supervisor protection */
-	sd_g   : 1,	/* global */
-	sd_ci  : 1,	/* cache inhibit */
-	       : 3,
-	sd_wp  : 1,	/* write protect */
-	       : 1,
-	sd_v   : 1;	/* valid */
-};
-
-typedef	struct segment_d segment_d_t;
-
-struct pfsr {		/* P bus fault status register */
-    unsigned
-	       :13,
-	pfsr_fc: 3,	/* falut code */
-	       :16;
-};
-
-struct batc {		/* block address translation register */
-    unsigned
-	batc_lba:13,	/* logical block address */
-	batc_pba:13,	/* physical block address */
-	batc_s  : 1,	/* supervisor */
-	batc_wt : 4,	/* write through */
-	batc_g  : 1,	/* global */
-	batc_ci : 1,	/* cache inhibit */
-	batc_wp : 1,	/* write protect */
-	batc_v  : 1;	/* valid */
-};
 
 /*
- * Prototypes and stuff for cmmu.c.
+ * Prototypes from "mvme88k/mvme88k/m18x_cmmu.c"
  */
-extern unsigned cpu_sets[MAX_CPUS];
-extern unsigned ncpus;
-extern unsigned cache_policy;
 
 #ifdef CMMU_DEBUG
- void show_apr(unsigned value);
- void show_sctr(unsigned value);
+ void m18x_show_apr(unsigned value);
+ void m18x_show_sctr(unsigned value);
 #endif
 
-/*
- * Prototypes from "motorola/m88k/m88100/cmmu.c"
- */
-unsigned cmmu_cpu_number(void);
+unsigned m18x_cmmu_cpu_number(void);
 #if !DDB
 static
 #endif /* !DDB */
-unsigned cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
-unsigned cmmu_get_idr(unsigned data);
-void cmmu_init(void);
-void cmmu_shutdown_now(void);
-void cmmu_parity_enable(void);
+unsigned m18x_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
+unsigned m18x_cmmu_get_idr(unsigned data);
+void m18x_cmmu_init(void);
+void m18x_cmmu_shutdown_now(void);
+void m18x_cmmu_parity_enable(void);
 #if !DDB
 static
 #endif /* !DDB */
-void cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
-void cmmu_set_sapr(unsigned ap);
-void cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
-void cmmu_set_uapr(unsigned ap);
-void cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
-void cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
-void cmmu_flush_cache(vm_offset_t physaddr, int size);
-void cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
-void cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
-void cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
-void cmmu_flush_data_cache(vm_offset_t physaddr, int size);
-
-void cmmu_pmap_activate(
+void m18x_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
+void m18x_cmmu_set_sapr(unsigned ap);
+void m18x_cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
+void m18x_cmmu_set_uapr(unsigned ap);
+void m18x_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
+void m18x_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
+void m18x_cmmu_flush_cache(vm_offset_t physaddr, int size);
+void m18x_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
+void m18x_cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
+void m18x_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
+void m18x_cmmu_flush_data_cache(vm_offset_t physaddr, int size);
+
+void m18x_cmmu_pmap_activate(
     unsigned cpu,
     unsigned uapr,
     batc_template_t i_batc[BATC_MAX],
     batc_template_t d_batc[BATC_MAX]);
 
-void cmmu_flush_remote_tlb(
+void m18x_cmmu_flush_remote_tlb(
 	unsigned cpu,
 	unsigned kernel,
 	vm_offset_t vaddr,
 	int size);
 
-void cmmu_set_batc_entry(
+void m18x_cmmu_set_batc_entry(
      unsigned cpu,
      unsigned entry_no,
      unsigned data,   /* 1 = data, 0 = instruction */
      unsigned value);  /* the value to stuff into the batc */
 
-void cmmu_set_pair_batc_entry(
+void m18x_cmmu_set_pair_batc_entry(
      unsigned cpu,
      unsigned entry_no,
      unsigned value);  /* the value to stuff into the batc */
 
 #endif	/* ASSEMBLER */
 
+/*
+ * Possible MVME188 board configurations
+ */
+#define CONFIG_0		0x0
+#define CONFIG_1		0x1
+#define CONFIG_2		0x2
+#define CONFIG_5		0x5
+#define CONFIG_6		0x6
+#define CONFIG_A		0xA
+
+/*
+ * Address masks for MMU configs
+ */
+#define CMMU_SRAM		      (1<<31)
+#define CMMU_A12_MASK		(1<<12)
+#define CMMU_A14_MASK		(1<<14)
+#define CMMU_SRAM_MASK		((1<<31)|(1<<30))
+
 #define INST_CMMU 0
 #define DATA_CMMU 1
+#define BOTH_CMMU 2
+
+#define CMMU_MODE_INST		0
+#define CMMU_MODE_DATA		1
+#define CMMU_MODE_BOTH		2
+
+#define CMMU_ACS_USER		0
+#define CMMU_ACS_SUPER		1
+#define CMMU_ACS_BOTH		2
+
+#define CMMU_SPLIT_ADDRESS	0x0
+#define CMMU_SPLIT_SPV		0x1
+#define CMMU_SPLIT_SRAM_SPV	0x2
+#define CMMU_SPLIT_SRAM_ALL	0x3
+
+#define CMMU_SPLIT_MASK		0x3
+
+#define CMMU_NSTRATEGIES	4
+
+/*
+ * Flags passed to cmmu_set()
+ */
+#define NUM_CMMU		0x01
+#define NUM_CPU			0x02 /* notyetused */
+#define MODE_VAL		0x04
+#define ACCESS_VAL		0x08
+#define ADDR_VAL		0x10
 
 #define NBSG    (4*1024*1024) /* segment size */
 
diff --git a/sys/arch/mvme88k/include/mvme188.h b/sys/arch/mvme88k/include/mvme188.h
new file mode 100644
index 00000000000..e64198e232f
--- /dev/null
+++ b/sys/arch/mvme88k/include/mvme188.h
@@ -0,0 +1,399 @@
+/*	$OpenBSD: mvme188.h,v 1.1 1999/09/27 20:46:18 smurph Exp $ */
+/*
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ */
+
+#ifndef	_MACHINE_MVME188_H
+#define	_MACHINE_MVME188_H
+
+/*
+ * Something to put append a 'U' to a long constant if it's C so that
+ * it'll be unsigned in both ANSI and traditional.
+ */
+#ifndef UDEFINED
+#if defined(ASSEMBLER)
+#	define U(num)	num
+#else
+#  if defined(__STDC__)
+#	define U(num)	num ## U
+#  else
+#	define U(num)	num/**/U
+#  endif
+#endif
+#endif
+
+
+#define MVME188_EPROM		   U(0xFFC00000)
+#define MVME188_EPROM_SIZE	   U(0x00080000)
+#define MVME188_SRAM		      U(0xFFE00000)
+#define MVME188_SRAM_SIZE	   U(0x00020000)
+#define MVME188_UTILITY		   U(0xFF000000)
+#define MVME188_UTILITY_SIZE	U(0x01000000)
+#define UTIL_START            U(0xFFC00000)  /* start of MVME188 utility space */
+#define UTIL_SIZE             U(0x003FFFFF)  /* size of MVME188 utility space */
+
+/*
+ * MVME188 declarations for hardware level device registers and such.
+ */
+
+/* base address for the interrupt control registers */
+#define INTR_CONTROL_BASE	U(0xfff84000)
+#define VMEA24SPACE 	   U(0xEEC00000) 	/*  VMEA24 master addr space (4 Meg) */
+
+/* per-processor interrupt enable registers */
+#define MVME188_IEN0	   U(0xFFF84004)	/* interrupt enable CPU 0 */
+#define MVME188_IEN1	   U(0xFFF84008)	/* interrupt enable CPU 1 */
+#define MVME188_IEN2	   U(0xFFF84010)	/* interrupt enable CPU 2 */
+#define MVME188_IEN3	   U(0xFFF84020)	/* interrupt enable CPU 3 */
+
+/* same as above */
+#define IEN0_REG        U(0xfff84004)
+#define IEN1_REG        U(0xfff84008)
+#define IEN2_REG        U(0xfff84010)
+#define IEN3_REG        U(0xfff84020)
+
+#define IENALL_REG      U(0xfff8403c)
+
+#define MVME188_IST	   U(0xFFF84040) 	/* interrupt status register */
+#define IST_REG         U(0xfff84040)	/* same as above */
+
+#define MVME188_SETSWI	U(0xFFF84080) 	/* generate soft interrupt */
+#define MVME188_CLRSWI	U(0xFFF84084) 	/* reset soft interrupt */
+#define MVME188_ISTATE	U(0xFFF84088) 	/* HW interrupt status */
+#define MVME188_CLRINT	U(0xFFF8408C) 	/* reset HW interrupt */
+
+/* same as above */
+#define SETSWI_REG   U(0xfff84080)	/* SETSWI register addr */
+#define CLRSWI_REG   U(0xfff84084)	/* CLRSWI register addr */
+#define ISTATE_REG   U(0xfff84088)
+#define CLRINT_REG   U(0xfff8408C)
+
+#define MVME188_GCSR 	U(0xFFF86000)	/* 188 global control and status reg */
+#define MVME188_UCSR 	U(0xFFF87000)	/* 188 utility control and status reg */
+#define MVME188_BASAD 	U(0xFFF87004)	/* 188 base address reg */
+#define MVME188_GLBRES 	U(0xFFF8700C)	/* 188 global reset reg */
+
+#define GCSR_BASE    U(0xfff86000)
+#define GLOBAL0      GCSR_BASE + 0x01
+#define GLOBAL1      GCSR_BASE + 0x03
+#define GLOBAL2      GCSR_BASE + 0x05
+#define GLOBAL3      GCSR_BASE + 0x07
+#define GLB0         U(0xfff86001)
+#define GLB1         U(0xfff86003)
+#define GLB2         U(0xfff86005)
+#define GLB3         U(0xfff86007)
+#define M188_SYSCON  U(0x00000040)
+#define UCSR_REG     U(0xfff87000)
+#define GLBRES_REG   U(0xfff8700C)
+
+#define MVME188_CCSR 	U(0xFFF88000)	/* 188 CPU board control status reg */
+#define MVME188_ERROR 	U(0xFFF88004)	/* 188 Mbus fault reg */
+#define MVME188_PCNFA 	U(0xFFF88008)	/* 188 Pbus A decoder reg */
+#define MVME188_PCNFB 	U(0xFFF8800C)	/* 188 Pbus B decoder reg */
+#define MVME188_EXTAD 	U(0xFFF88010)	/* 188 A24 master A24-A31 addr reg */
+#define MVME188_WHOAMI 	U(0xFFF88018)	/* 188 whoami reg */
+#define MVME188_WMAD 	U(0xFFF88020)	/* 188 write mbus addr decoder reg */
+#define MVME188_RMAD 	U(0xFFF88024)	/* 188 read mbus addr decoder reg */
+#define MVME188_WVAD 	U(0xFFF88028)	/* 188 write vmebus addr decoder reg */
+#define MVME188_RVAD 	U(0xFFF8802C)	/* 188 read vmebus adds decoder reg */
+
+/* duplicates of above */
+#define CCSR_REG     U(0xfff88000)
+#define ERROR_REG    U(0xfff88004)	/* ERROR register addr */
+#define PCNFA_REG    U(0xfff88008)
+#define PCNFB_REG    U(0xfff8800c)
+#define EXTAD_REG    U(0xfff88010)
+#define EXTAM_REG    U(0xfff88014)
+#define WHOAMI_REG   U(0xfff88018)	/* WHOAMI register addr */
+#define WMAD_REG     U(0xfff88020)
+#define RMAD_REG     U(0xfff88024)
+#define WVAD_REG     U(0xfff88028)
+#define RVAD_REG     U(0xfff8802c)
+
+#define MAD_MDS		   0x07	/* 188 MAD Device Select bits */
+
+#define VMEA24 		   0x5	/* Mbus addess decode select for VMEA24 */
+#define VADV		      0x1	/* vmeaddres decode enable */
+#define VBDSELBIT 	   0 	   /* bit to enable vme slave response low true */
+#define VBDISABLE	      0x1	/* VME BUS Disable */
+#define VSDBIT    	   1 	   /* bit number to enable snooping low true */
+#define VSDISABLE	      0x2	/* VME Snoop Disable */
+#define VASPBIT	 	   21 	/* addr space 0 = A32, 1 = A24 bit */
+#define VASP		      0x00200000 /* A24 VME address space */
+#define VPN		         0x00400000 /* Page Number LSB */
+#define PAGECNT		   0x400	/* number of (4 meg) pages to map */
+
+#define UCSR_PWRUPBIT 	0x4000	/* 188 UCSR powerup indicator */
+#define UCSR_DRVSFBIT 	0x2000	/* 188 UCSR Board system fail */
+#define UCSR_BRIRQBIT 	0x1000	/* 188 UCSR drives VME IRQ1 broadcast int */
+#define UCSR_ROBINBIT 	0x800	   /* 188 UCSR sel round robin VME arbiter mode */
+#define UCSR_BRLVBITS 	0x600	   /* 188 UCSR VME bus request level 0-3 */
+#define UCSR_RNEVERBIT  0x100	   /* 188 UCSR VME bus never release once req'd */
+#define UCSR_RONRBIT	   0x80	   /* 188 UCSR VME bus req release on no request */
+#define UCSR_RWDBIT		0x40	   /* 188 UCSR VME bus request release when done */
+#define UCSR_EARBTOBIT  0x20	   /* 188 UCSR enable VME arbiter bus timeout */
+
+/* MVME188 VMEbus data transfer timeout select */
+#define VTOSELBITS 	0x18	/* 188 UCSR VMEbus timeout select bits */
+#define VTO32US 	   0x00	/* VMEbus timeout length - 32 MicroSec */
+#define VTO64US 	   0x01	/* VMEbus timeout length - 64 MicroSec */
+#define VTO128US 	   0x10	/* VMEbus timeout length - 128 MicroSec */
+#define VTODISABLE 	0x18	/* VMEbus timeout length - disabled */
+
+/*
+ * processor dependend code section
+ * main goal is to concentrate HW dependencies into a few lines
+ */
+#define ISR_LOW_SOFTINT_MASK(cpu)	(1<<cpu)
+#define ISR_HIGH_SOFTINT_MASK(cpu)	(1<<(cpu + 24))
+#define ISR_LOW_SOFTMASK		0xf
+#define ISR_HIGH_SOFTMASK		(0xf<<24)
+#define ISR_SOFTINT_EXCEPT_MASK(cpu)	(ISR_LOW_SOFTINT_MASK(cpu) | ISR_HIGH_SOFTINT_MASK(cpu) | 0xf0fffff0)
+#define ISR_CLOCKINT_MASK		(1<<IEN_CIOI_LOG)
+
+#define ISR_RESET_NMI			*(volatile int *)MVME188_CLRINT = 1<<CLRINT_CLRABRTI_LOG
+#define ISR_RESET_SYSFAIL		*(volatile int *)MVME188_CLRINT = 1<<CLRINT_CLRSFI_LOG
+#define ISR_RESET_ACFAIL		*(volatile int *)MVME188_CLRINT = 1<<CLRINT_CLRACFI_LOG
+#define ISR_RESET_LOW_SOFTINT(cpu)	*(int *)MVME188_CLRSWI = ISR_LOW_SOFTINT_MASK(cpu)
+#define ISR_RESET_HIGH_SOFTINT(cpu)	*(int *)MVME188_CLRSWI = (1<<(cpu + MAX_CPUS))
+#define ISR_DETERMINE_LOW_SOFTINT(cpu)	*(volatile unsigned int *)MVME188_IST & ISR_LOW_SOFTINT_MASK(cpu)
+#define ISR_DETERMINE_HIGH_SOFTINT(cpu)	*(volatile unsigned int *)MVME188_IST & ISR_HIGH_SOFTINT_MASK(cpu)
+#define ISR_GENERATE_LOW_SOFTINT(cpu)	*((volatile unsigned int *)MVME188_SETSWI) = ISR_LOW_SOFTINT_MASK(cpu)
+#define ISR_GENERATE_HIGH_SOFTINT(cpu)	*((volatile unsigned int *)MVME188_SETSWI) = (1<<(cpu + MAX_CPUS))
+#define ISR_RESET_MACHINE		*((volatile unsigned *) MVME188_GLBRES) = 1
+#define ISR_GET_CURRENT_MASK(cpu)	*int_mask_reg[cpu] & *(volatile int *)MVME188_IST
+
+#define IST_STRING "\20\40ABRT\37ACF\36ARBTO\35DTI\34SWI7\33SWI6\32SWI5\31SWI4\30IRQ7\27res\26CIOI\25SF\24IRQ6\23res\22DI\21SIGHPI\20res\17IRQ5\16res\15IRQ4\14res\13IRQ3\12res\11LWI\10SIGLPI\7IRQ2\6res\5IRQ1\4SWI3\3SWI2\2SWI1\1SWI0"
+
+#define INT_LEVEL	        8		/* # of interrupt level + 1 */
+
+/*
+ * masks and offsets for IST
+ */
+#define HW_FAILURE_MASK		   U(0x60100000)	/* HW failure bits */
+#define HW_FAILURE_ACF		   U(0x40000000)  /* AC failure */
+#define HW_FAILURE_ABRTO	   U(0x20000000)  /* Arbiter timeout */
+#define HW_FAILURE_SYSFAIL	   U(0x00100000) 	/* SYSFAIL asserted */
+
+#define SOFT_INTERRUPT_MASK	U(0x0F00000F)	/* software irq bits */
+#define VME_INTERRUPT_MASK	   U(0x00885450)	/* vme irq bits */
+#define OBIO_INTERRUPT_MASK	U(0xF0320100)  /* on board I/O */
+
+#define IEN_ABRT_LOG		31
+#define IEN_CIOI_LOG		21
+#define IEN_DTI_LOG		28
+#define IEN_DI_LOG		17
+
+#define CLRINT_CLRABRTI_LOG	2		/* offset into CLRSWI */
+#define CLRINT_CLRACFI_LOG	1		/* offset into CLRSWI */
+#define CLRINT_CLRSFI_LOG	0		/* offset into CLRSWI */
+
+/* the following codes are the INT exception enable and status bits. */
+/* Refer to MVME188 RISC Microcomputer User's Manual, 4-10. */
+#define ABRT_BIT     U(0x80000000)
+#define ACF_BIT      U(0x40000000)
+#define ARBTO_BIT    U(0x20000000)
+#define DTI_BIT      U(0x10000000)
+#define SWI7_BIT     U(0x08000000)
+#define SWI6_BIT     U(0x04000000)
+#define SWI5_BIT     U(0x02000000)
+#define SWI4_BIT     U(0x01000000)
+#define IRQ7_BIT     U(0x00800000)
+#define CIOI_BIT     U(0x00200000)
+#define SF_BIT       U(0x00100000)
+#define IRQ6_BIT     U(0x00080000)
+#define DI_BIT       U(0x00020000)
+#define SIGHPI_BIT   U(0x00010000)
+#define IRQ5_BIT     U(0x00004000)
+#define IRQ4_BIT     U(0x00001000)
+#define IRQ3_BIT     U(0x00000400)
+#define LMI_BIT      U(0x00000100)
+#define SIGLPI_BIT   U(0x00000080)
+#define IRQ2_BIT     U(0x00000040)
+#define IRQ1_BIT     U(0x00000010)
+#define SWI3_BIT     U(0x00000008)
+#define SWI2_BIT     U(0x00000004)
+#define SWI1_BIT     U(0x00000002)
+#define SWI0_BIT     U(0x00000001)
+
+#define ABRT_BIT     U(0x80000000)
+#define ACF_BIT      U(0x40000000)
+#define ARBTO_BIT    U(0x20000000)
+#define DTI_BIT      U(0x10000000)
+#define CIOI_BIT     U(0x00200000)
+#define SF_BIT       U(0x00100000)
+#define DI_BIT       U(0x00020000)
+#define LMI_BIT      U(0x00000100)
+
+#define LVL7 (ABRT_BIT | ACF_BIT | IRQ7_BIT | SF_BIT)
+#define LVL6 (IRQ6_BIT)
+#define LVL5 (IRQ5_BIT | DTI_BIT | CIOI_BIT)
+#define LVL4 (IRQ4_BIT)
+#define LVL3 (IRQ3_BIT | DI_BIT)
+#define LVL2 (IRQ2_BIT)
+#define LVL1 (IRQ1_BIT)
+#define LVL0 (0x0)
+#define SLAVE_MASK (LVL6 | LVL1)
+
+#define MASK_LVL_0 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1)
+#define MASK_LVL_1 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2) 
+#define MASK_LVL_2 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3)  
+#define MASK_LVL_3 (LVL7 | LVL6 | LVL5 | LVL4)    
+#define MASK_LVL_4 (LVL7 | LVL6 | LVL5)    
+#define MASK_LVL_5 (LVL7 | LVL6)
+#define MASK_LVL_6 (LVL7)
+#define MASK_LVL_7 U(0x00000000) /* all ints disabled */
+
+/* these are the various Z8536 CIO counter/timer registers */
+#define CIO_BASE     U(0xfff83000)
+#define CIO_PORTC    U(0xfff83000)
+#define CIO_PORTB    U(0xfff83004)
+#define CIO_PORTA    U(0xfff83008)
+#define CIO_CTRL     U(0xfff8300c)
+
+#define CIO_MICR        0x00	/* Master interrupt control register */
+#define CIO_MICR_MIE    0x80
+#define CIO_MICR_DLC    0x40
+#define CIO_MICR_NV     0x20
+#define CIO_MICR_PAVIS  0x10
+#define CIO_MICR_PBVIS  0x08
+#define CIO_MICR_CTVIS  0x04
+#define CIO_MICR_RJA    0x02
+#define CIO_MICR_RESET  0x01
+
+#define CIO_MCCR        0x01	/* Master configuration control register */
+#define CIO_MCCR_PBE    0x80
+#define CIO_MCCR_CT1E   0x40
+#define CIO_MCCR_CT2E   0x20
+#define CIO_MCCR_CT3E   0x10
+#define CIO_MCCR_PLC    0x08
+#define CIO_MCCR_PAE    0x04
+
+#define CIO_CTMS1       0x1c	/* Counter/timer mode specification #1 */
+#define CIO_CTMS2       0x1d	/* Counter/timer mode specification #2 */
+#define CIO_CTMS3       0x1e	/* Counter/timer mode specification #3 */
+#define CIO_CTMS_CSC    0x80  /* Continuous Single Cycle */
+#define CIO_CTMS_EOE    0x40  /* External Output Enable  */
+#define CIO_CTMS_ECE    0x20  /* External Count Enable   */
+#define CIO_CTMS_ETE    0x10  /* External Trigger Enable */
+#define CIO_CTMS_EGE    0x08  /* External Gate Enable    */
+#define CIO_CTMS_REB    0x04  /* Retrigger Enable Bit    */
+#define CIO_CTMS_PO     0x00  /* Pulse Output            */
+#define CIO_CTMS_OSO    0x01  /* One Shot Output         */
+#define CIO_CTMS_SWO    0x02  /* Square Wave Output      */
+
+#define CIO_IVR         0x04	/* Interrupt vector register */
+
+#define CIO_CSR1        0x0a	/* Command and status register CTC #1 */
+#define CIO_CSR2        0x0b	/* Command and status register CTC #2 */
+#define CIO_CSR3        0x0c	/* Command and status register CTC #3 */
+
+#define CIO_CT1MSB      0x16	/* CTC #1 Timer constant - MSB */
+#define CIO_CT1LSB      0x17	/* CTC #1 Timer constant - LSB */
+#define CIO_CT2MSB      0x18	/* CTC #2 Timer constant - MSB */
+#define CIO_CT2LSB      0x19	/* CTC #2 Timer constant - LSB */
+#define CIO_CT3MSB      0x1a	/* CTC #3 Timer constant - MSB */
+#define CIO_CT3LSB      0x1b	/* CTC #3 Timer constant - LSB */
+#define CIO_PDCA        0x23	/* Port A data direction control */
+#define CIO_PDCB        0x2b	/* Port B data direction control */
+
+#define CIO_GCB         0x04	/* CTC Gate command bit */
+#define CIO_TCB         0x02	/* CTC Trigger command bit */
+#define CIO_IE          0xc0	/* CTC Interrupt enable (set) */
+#define CIO_CIP         0x20	/* CTC Clear interrupt pending */
+#define CIO_IP          0x20	/* CTC Interrupt pending */
+
+/* these are the DART read registers */
+#define DART_BASE    U(0xfff82000)
+#define DART_MRA     U(0xfff82000)	/* mode A */
+#define DART_SRA     U(0xfff82004)	/* status A */
+#define DART_RBA     U(0xfff8200c)	/* receive buffer A */
+#define DART_IPCR    U(0xfff82010)	/* input port change */
+#define DART_ISR     U(0xfff82014)	/* interrupt status */
+#define DART_CUR     U(0xfff82018)	/* count upper */
+#define DART_CLR     U(0xfff8201c)	/* count lower */
+#define DART_MR1B    U(0xfff82020)	/* mode B */
+#define DART_SRB     U(0xfff82024)	/* status B */
+#define DART_RBB     U(0xfff8202c)	/* receive buffer B */
+#define DART_IVR     U(0xfff82030)	/* interrupt vector */
+#define DART_INP     U(0xfff82034)	/* input port */
+#define DART_STARTC  U(0xfff82038)	/* start counter cmd */
+#define DART_STOPC   U(0xfff8203c)	/* stop counter cmd */
+
+/* these are the DART write registers */
+#define DART_CSRA    U(0xfff82004)	/* clock select A */
+#define DART_CRA     U(0xfff82008)	/* command A */
+#define DART_TBA     U(0xfff8200c)	/* transmit buffer A */
+#define DART_ACR     U(0xfff82010)	/* auxiliary control */
+#define DART_IMR     U(0xfff82014)	/* interrupt mask reg*/
+#define DART_CTUR    U(0xfff82018)	/* counter/timer MSB */
+#define DART_CTLR    U(0xfff8201c)	/* counter/timer LSB */
+#define DART_MRB     U(0xfff82020)	/* mode B */
+#define DART_CSRB    U(0xfff82024)	/* clock select B */
+#define DART_CRB     U(0xfff82028)	/* command B */
+#define DART_TBB     U(0xfff8202c)	/* transmit buffer B */
+#define DART_OPCR    U(0xfff82034)	/* output port config*/
+#define DART_OPRS    U(0xfff82038)	/* output port set */
+#define DART_OPRR    U(0xfff8203c)	/* output port reset */
+
+#ifndef ASSEMBLER
+
+/*
+ * Externals
+ */
+
+extern unsigned int m188_curspl[MAX_CPUS];
+extern unsigned int int_mask_val[INT_LEVEL];
+extern unsigned int int_mask_shadow[MAX_CPUS];
+extern volatile unsigned int *int_mask_reg[MAX_CPUS];
+/*
+ * Prototypes
+ */
+void block_obio_interrupt(unsigned mask);
+void unblock_obio_interrupt(unsigned mask);
+#endif 
+#define M188_IACK        U(0xFFF85000)
+
+#endif	/* _MACHINE_MVME188_H */
+
+
diff --git a/sys/arch/mvme88k/include/mvme1x7.h b/sys/arch/mvme88k/include/mvme1x7.h
new file mode 100644
index 00000000000..d65d59726c2
--- /dev/null
+++ b/sys/arch/mvme88k/include/mvme1x7.h
@@ -0,0 +1,105 @@
+/*	$OpenBSD: mvme1x7.h,v 1.1 1999/09/27 20:46:18 smurph Exp $ */
+/*
+ * Copyright (c) 1996 Nivas Madhur
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ */
+#ifndef _MACHINE_MVME1X7_H
+#define _MACHINE_MVME1X7_H
+/*
+ *      VME1x7 CPU board constants - derived from Luna88k
+ */
+
+/*
+ * Something to put append a 'U' to a long constant if it's C so that
+ * it'll be unsigned in both ANSI and traditional.
+ */
+#ifndef UDEFINED
+#if defined(ASSEMBLER)
+#	define U(num)	num
+#else
+#  if defined(__STDC__)
+#	define U(num)	num ## U
+#  else
+#	define U(num)	num/**/U
+#  endif
+#endif
+#endif
+
+#define BUGROM_START		U(0xFF800000)	/* start of BUG PROM */
+#define BUGROM_SIZE		U(0x003FFFFF)	/* size of BUG PROM */
+#define SRAM_START		U(0xFFE00000)	/* start of sram used by bug */
+#define SRAM_SIZE			U(0x0001FFFF)	/* size of sram */
+#define OBIO_START		U(0xFFF00000)	/* start of local IO */
+#define OBIO_SIZE			U(0x000EFFFF)	/* size of obio space */
+#define UTIL_START      U(0xFFC00000)  /* start of MVME188 utility space */
+#define UTIL_SIZE       U(0x003FFFFF)  /* size of MVME188 utility space */
+
+#define INT_PRI_LEVEL	U(0xFFF4203E)	/* interrupt priority level */
+#define INT_MASK_LEVEL	U(0xFFF4203F)	/* interrupt mask level */
+
+#define LOCAL_IO_DEVS	U(0xFFF00000)	/* local IO devices */
+
+#define PCC2_ADDR			U(0xFFF42000)	/* PCCchip2 Regs */
+#define UTIL_ADDR			U(0xFFC02000)	/* PCCchip2 Regs */
+#define MEM_CTLR			U(0xFFF43000)	/* MEMC040 mem controller */
+#define SCC_ADDR			U(0xFFF45000) 	/* Cirrus Chip */
+#define LANCE_ADDR		U(0xFFF46000) 	/* 82596CA */
+#define SCSI_ADDR			U(0xFFF47000) 	/* NCR 710 address */
+#define NCR710_SIZE		U(0x00000040) 	/* NCR 710 size */
+#define MK48T08_ADDR		U(0xFFFC0000) 	/* BBRAM, TOD */
+
+#define TOD_CAL_CTL		U(0xFFFC1FF8) 	/* calendar control register */
+#define TOD_CAL_SEC		U(0xFFFC1FF9) 	/* seconds */
+#define TOD_CAL_MIN		U(0xFFFC1FFA) 	/* minutes */
+#define TOD_CAL_HOUR		U(0xFFFC1FFB) 	/* hours */
+#define TOD_CAL_DOW		U(0xFFFC1FFC) 	/* Day Of the Week */
+#define TOD_CAL_DAY		U(0xFFFC1FFD) 	/* days */
+#define TOD_CAL_MON		U(0xFFFC1FFE) 	/* months */
+#define TOD_CAL_YEAR		U(0xFFFC1FFF) 	/* years */
+
+#define M187_IACK       U(0xFFFE0000)
+#define M197_IACK       U(0xFFF00100)
+
+#endif /* _MACHINE_MVME1X7_H */
+
+
diff --git a/sys/arch/mvme88k/include/param.h b/sys/arch/mvme88k/include/param.h
index fced74b83d1..aab7bff3cc4 100644
--- a/sys/arch/mvme88k/include/param.h
+++ b/sys/arch/mvme88k/include/param.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: param.h,v 1.9 1999/05/29 04:41:45 smurph Exp $ */
+/*	$OpenBSD: param.h,v 1.10 1999/09/27 20:46:18 smurph Exp $ */
 /*
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1988 University of Utah.
@@ -40,16 +40,16 @@
  * from: Utah $Hdr: machparam.h 1.11 89/08/14$
  *
  *	@(#)param.h	7.8 (Berkeley) 6/28/91
- *	$Id: param.h,v 1.9 1999/05/29 04:41:45 smurph Exp $
+ *	$Id: param.h,v 1.10 1999/09/27 20:46:18 smurph Exp $
  */
 #ifndef _MACHINE_PARAM_H_
 #define _MACHINE_PARAM_H_
 
-#define	_MACHINE 	mvme88k
-#define	MACHINE 	"mvme88k"
-#define	_MACHINE_ARCH	m88k
-#define	MACHINE_ARCH	"m88k"
-#define	MID_MACHINE	MID_M88K
+#define  _MACHINE       mvme88k
+#define  MACHINE        "mvme88k"
+#define  _MACHINE_ARCH  m88k
+#define  MACHINE_ARCH   "m88k"
+#define  MID_MACHINE    MID_M88K
 
 /*
  * Round p (pointer or byte index) down to a correctly-aligned value
@@ -59,20 +59,20 @@
  * 88k.
  */
 
-#define ALIGNBYTES	15	/* 64 bit alignment */
-#define	ALIGN(p)		(((u_int)(p) + ALIGNBYTES) & ~ALIGNBYTES)
-#define ALIGNED_POINTER(p,t)	((((u_long)(p)) & (sizeof(t)-1)) == 0)
+#define  ALIGNBYTES           15	/* 64 bit alignment */
+#define  ALIGN(p)             (((u_int)(p) + ALIGNBYTES) & ~ALIGNBYTES)
+#define  ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0)
 
-#ifndef NBPG
-#define	NBPG		4096		/* bytes/page */
+#ifndef  NBPG
+#define  NBPG                 4096     /* bytes/page */
 #endif /* NBPG */
-#define	PGOFSET		(NBPG-1)	/* byte offset into page */
-#define	PGSHIFT		12		/* LOG2(NBPG) */
-#define	NPTEPG		(NBPG/(sizeof(u_int)))
+#define  PGOFSET              (NBPG-1) /* byte offset into page */
+#define  PGSHIFT              12       /* LOG2(NBPG) */
+#define  NPTEPG               (NBPG/(sizeof(u_int)))
 
-#define NBSEG		(1<<22)		/* bytes/segment */
-#define	SEGOFSET	(NBSEG-1)	/* byte offset into segment */
-#define	SEGSHIFT	22		/* LOG2(NBSEG) */
+#define  NBSEG                (1<<22)  /* bytes/segment */
+#define  SEGOFSET             (NBSEG-1)/* byte offset into segment */
+#define  SEGSHIFT             22       /* LOG2(NBSEG) */
 
 /*
  * 187 Bug uses the bottom 64k. We allocate ptes to map this into the
@@ -80,32 +80,32 @@
  * past this 64k. How does this change KERNBASE? XXX
  */
 
-#define	KERNBASE	0x0		/* start of kernel virtual */
-#define	BTOPKERNBASE	((u_long)KERNBASE >> PGSHIFT)
+#define  KERNBASE             0x0      /* start of kernel virtual */
+#define  BTOPKERNBASE         ((u_long)KERNBASE >> PGSHIFT)
 
-#define	DEV_BSIZE	512
-#define	DEV_BSHIFT	9		/* log2(DEV_BSIZE) */
-#define BLKDEV_IOSIZE	2048		/* Should this be changed? XXX */
-#define	MAXPHYS		(64 * 1024)	/* max raw I/O transfer size */
+#define  DEV_BSIZE            512
+#define  DEV_BSHIFT           9        /* log2(DEV_BSIZE) */
+#define  BLKDEV_IOSIZE        2048     /* Should this be changed? XXX */
+#define  MAXPHYS              (64 * 1024)	/* max raw I/O transfer size */
 
-#define	CLSIZE		1
-#define	CLSIZELOG2	0
+#define  CLSIZE               1
+#define  CLSIZELOG2           0
 
 /* NOTE: SSIZE, SINCR and UPAGES must be multiples of CLSIZE */
-#define	SSIZE		1		/* initial stack size/NBPG */
-#define	SINCR		1		/* increment of stack/NBPG */
-#define USPACE		ctob(UPAGES)
+#define  SSIZE                1        /* initial stack size/NBPG */
+#define  SINCR                1        /* increment of stack/NBPG */
+#define  USPACE               ctob(UPAGES)
 
-#define	UPAGES		4		/* pages of u-area */
-#define	UADDR		0xEEE00000	/* address of u */
-#define	UVPN		(UADDR>>PGSHIFT)/* virtual page number of u */
-#define	KERNELSTACK	(UADDR+UPAGES*NBPG)	/* top of kernel stack */
+#define  UPAGES               4                    /* pages of u-area */
+#define  UADDR                0xEEE00000	         /* address of u */
+#define  UVPN                 (UADDR>>PGSHIFT)     /* virtual page number of u */
+#define  KERNELSTACK          (UADDR+UPAGES*NBPG)  /* top of kernel stack */
 
-#define PHYSIO_MAP_START 	0xEEF00000
-#define PHYSIO_MAP_SIZE  	0x00100000
-#define IOMAP_MAP_START		0xEF000000 /* VME etc */
-#define IOMAP_SIZE		0x018F0000
-#define NIOPMAP			32
+#define  PHYSIO_MAP_START     0xEEF00000
+#define  PHYSIO_MAP_SIZE      0x00100000
+#define  IOMAP_MAP_START      0xEF000000 /* VME etc */
+#define  IOMAP_SIZE           0x018F0000
+#define  NIOPMAP              32
 
 /*
  * Constants related to network buffer management.
@@ -114,39 +114,39 @@
  * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
  * of the hardware page size.
  */
-#define	MSIZE		128		/* size of an mbuf */
-#define	MCLBYTES	1024
-#define	MCLSHIFT	10
-#define	MCLOFSET	(MCLBYTES - 1)
-#ifndef NMBCLUSTERS
-#ifdef GATEWAY
-#define	NMBCLUSTERS	1024		/* map size, max cluster allocation */
+#define  MSIZE                128      /* size of an mbuf */
+#define  MCLBYTES             1024
+#define  MCLSHIFT             10
+#define  MCLOFSET             (MCLBYTES - 1)
+#ifndef  NMBCLUSTERS
+#ifdef   GATEWAY
+#define  NMBCLUSTERS          1024     /* map size, max cluster allocation */
 #else
-#define	NMBCLUSTERS	512		/* map size, max cluster allocation */
+#define  NMBCLUSTERS          512      /* map size, max cluster allocation */
 #endif
 #endif
 
 /*
  * Size of kernel malloc arena in CLBYTES-sized logical pages
  */ 
-#ifndef NKMEMCLUSTERS
-#define	NKMEMCLUSTERS	(4096*1024/CLBYTES)
+#ifndef  NKMEMCLUSTERS
+#define  NKMEMCLUSTERS        (4096*1024/CLBYTES)
 #endif
 
 /* pages ("clicks") to disk blocks */
-#define	ctod(x)	((x)<<(PGSHIFT-DEV_BSHIFT))
-#define	dtoc(x)	((x)>>(PGSHIFT-DEV_BSHIFT))
-#define	dtob(x)	((x)<<DEV_BSHIFT)
+#define  ctod(x)              ((x)<<(PGSHIFT-DEV_BSHIFT))
+#define  dtoc(x)              ((x)>>(PGSHIFT-DEV_BSHIFT))
+#define  dtob(x)              ((x)<<DEV_BSHIFT)
 
 /* pages to bytes */
-#define	ctob(x)	((x)<<PGSHIFT)
+#define  ctob(x)              ((x)<<PGSHIFT)
 
 /* bytes to pages */
-#define	btoc(x)	(((unsigned)(x)+(NBPG-1))>>PGSHIFT)
+#define  btoc(x)              (((unsigned)(x)+(NBPG-1))>>PGSHIFT)
 
-#define	btodb(bytes)	 		/* calculates (bytes / DEV_BSIZE) */ \
+#define  btodb(bytes)         /* calculates (bytes / DEV_BSIZE) */ \
 	((unsigned)(bytes) >> DEV_BSHIFT)
-#define	dbtob(db)			/* calculates (db * DEV_BSIZE) */ \
+#define  dbtob(db)            /* calculates (db * DEV_BSIZE) */ \
 	((unsigned)(db) << DEV_BSHIFT)
 
 /*
@@ -155,18 +155,18 @@
  * field from the disk label.
  * For now though just use DEV_BSIZE.
  */
-#define	bdbtofsb(bn)	((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
+#define  bdbtofsb(bn)         ((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
 
 /*
  * Mach derived conversion macros
  */
-#define mvme88k_btop(x)	((unsigned)(x) >> PGSHIFT)
-#define mvme88k_ptob(x)	((unsigned)(x) << PGSHIFT)
+#define  mvme88k_btop(x)      ((unsigned)(x) >> PGSHIFT)
+#define  mvme88k_ptob(x)      ((unsigned)(x) << PGSHIFT)
 
 #include <machine/psl.h>
 
-#ifdef _KERNEL
-#define	DELAY(x)	delay(x)
+#ifdef   _KERNEL
+#define  DELAY(x)             delay(x)
 #endif
 
 #ifdef _KERNEL
@@ -176,7 +176,9 @@ extern int cpumod;
 /*
  * Values for the cputyp variable.
  */
-#define CPU_187		0x187
-#define CPU_188		0x188
-#define CPU_197		0x197
+#define  CPU_187              0x187
+#define  CPU_188              0x188
+#define  CPU_197              0x197
 #endif /* !_MACHINE_PARAM_H_ */
+
+
diff --git a/sys/arch/mvme88k/include/pcb.h b/sys/arch/mvme88k/include/pcb.h
index ac9901274d6..1765e127383 100644
--- a/sys/arch/mvme88k/include/pcb.h
+++ b/sys/arch/mvme88k/include/pcb.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pcb.h,v 1.4 1999/02/09 06:36:27 smurph Exp $ */
+/*	$OpenBSD: pcb.h,v 1.5 1999/09/27 20:46:19 smurph Exp $ */
 /*
  * Copyright (c) 1996 Nivas Madhur
  * Mach Operating System
@@ -88,11 +88,14 @@ struct m88100_pcb {
 /* This must always be an even number of words long */
 
 struct m88100_saved_state {
-    unsigned r[32];
+    unsigned r[32];  /* 0 - 31 */
+#define pcb_sp r[31]
+    unsigned epsr;   /* 32 */
     unsigned fpsr;
     unsigned fpcr;
-    unsigned epsr;
+#define exip sxip
     unsigned sxip;
+#define enip snip
     unsigned snip;
     unsigned sfip;
     unsigned ssbr;
@@ -114,13 +117,19 @@ struct m88100_saved_state {
     unsigned fprh;
     unsigned fprl;
     unsigned fpit;
-    unsigned vector;	/* exception vector number */
-    unsigned mask;	/* interrupt mask level */
-    unsigned mode;	/* interrupt mode */
-    unsigned scratch1;	/* used by locore trap handling code */
-    unsigned ipfsr;      /* P BUS status - used in inst fault handling */
-    unsigned dpfsr;      /* P BUS status - used in data fault handling */
-    unsigned pad;	/* alignment */
+    unsigned vector;	      /* exception vector number */
+    unsigned mask;	      /* interrupt mask level */
+    unsigned mode;	      /* interrupt mode */
+    unsigned scratch1;	   /* used by locore trap handling code */
+    unsigned ipfsr;        /* P BUS status - used in inst fault handling */
+    unsigned dpfsr;        /* P BUS status - used in data fault handling */
+    unsigned dsr;          /* MVME197 */
+    unsigned dlar;         /* MVME197 */
+    unsigned dpar;         /* MVME197 */
+    unsigned isr;          /* MVME197 */
+    unsigned ilar;         /* MVME197 */
+    unsigned ipar;         /* MVME197 */
+    unsigned pad;          /* alignment */
 };
 
 #define trapframe m88100_saved_state
diff --git a/sys/arch/mvme88k/include/pmap.h b/sys/arch/mvme88k/include/pmap.h
index 960e75a0e9c..16b92109900 100644
--- a/sys/arch/mvme88k/include/pmap.h
+++ b/sys/arch/mvme88k/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.8 1999/07/18 18:00:06 deraadt Exp $ */
+/*	$OpenBSD: pmap.h,v 1.9 1999/09/27 20:46:19 smurph Exp $ */
 /*
  * Mach Operating System
  * Copyright (c) 1991 Carnegie Mellon University
@@ -35,6 +35,9 @@ struct pmap {
     int			ref_count;	/* reference count */
     simple_lock_data_t	lock;
     struct pmap_statistics stats;	/* pmap statistics */
+    
+    /* cpus using of this pmap; NCPU must be <= 32 */
+    unsigned long      cpus_using;
 
 #ifdef DEBUG
     pmap_t		next;
@@ -91,8 +94,8 @@ extern	pmap_t	kernel_pmap;
 
 void _pmap_activate(pmap_t pmap, pcb_t, int my_cpu);
 void _pmap_deactivate(pmap_t pmap, pcb_t, int my_cpu);
-void pmap_activate(pmap_t my_pmap, pcb_t);
-void pmap_deactivate(pmap_t pmap, pcb_t);
+void pmap_activate(pmap_t my_pmap, pcb_t, int cpu);
+void pmap_deactivate(pmap_t pmap, pcb_t, int cpu);
 int pmap_check_transaction(pmap_t pmap, vm_offset_t va, vm_prot_t type);
 
 vm_offset_t pmap_map(
diff --git a/sys/arch/mvme88k/include/pmap_table.h b/sys/arch/mvme88k/include/pmap_table.h
index 074608d3e14..61b606bcefc 100644
--- a/sys/arch/mvme88k/include/pmap_table.h
+++ b/sys/arch/mvme88k/include/pmap_table.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap_table.h,v 1.4 1999/02/09 06:36:27 smurph Exp $ */
+/*	$OpenBSD: pmap_table.h,v 1.5 1999/09/27 20:46:19 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1992 Carnegie Mellon University
@@ -34,8 +34,8 @@
 /* end of list is indicated by pm_size 0xffffffff */
 
 typedef struct {
-  vm_offset_t	phys_start;   /* in bytes */
-  vm_offset_t   virt_start;   /* in bytes */
+  vm_offset_t phys_start;   /* in bytes */
+  vm_offset_t virt_start;   /* in bytes */
   unsigned int	size;      /* in bytes */
   unsigned int  prot;	      /* vm_prot_read, vm_prot_write */
   unsigned int  cacheability; /* none, writeback, normal */
@@ -43,3 +43,7 @@ typedef struct {
 
 typedef pmap_table_entry *pmap_table_t;
 
+pmap_table_t pmap_table_build __P((unsigned memory_size));
+
+
+
diff --git a/sys/arch/mvme88k/include/proc.h b/sys/arch/mvme88k/include/proc.h
index 31acf460704..8dbe04ff142 100644
--- a/sys/arch/mvme88k/include/proc.h
+++ b/sys/arch/mvme88k/include/proc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: proc.h,v 1.5 1999/05/29 04:41:45 smurph Exp $ */
+/*	$OpenBSD: proc.h,v 1.6 1999/09/27 20:46:19 smurph Exp $ */
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -43,7 +43,7 @@
  *	@(#)proc.h	8.1 (Berkeley) 6/11/93
  *
  * from: Header: proc.h,v 1.6 92/11/26 02:04:41 torek Exp  (LBL)
- * $Id: proc.h,v 1.5 1999/05/29 04:41:45 smurph Exp $
+ * $Id: proc.h,v 1.6 1999/09/27 20:46:19 smurph Exp $
  */
 
 #include <machine/pcb.h>
@@ -53,9 +53,11 @@
  * Machine-dependent part of the proc structure for VME1X7.
  */
 struct mdproc {
-	struct	trapframe *md_tf;	/* trap/syscall registers */
-	struct	fpstate *md_fpstate;	/* fpu state, if any; always resident */
-	int 	md_upte[UPAGES];	/* ptes for mapping u page */
-	int	md_ss_addr;		/* single step address for ptrace */
-	int	md_ss_instr;		/* single step instruction for ptrace */
+	struct   trapframe *md_tf;    /* trap/syscall registers */
+	struct   fpstate *md_fpstate; /* fpu state, if any; always resident */
+	int      md_upte[UPAGES];     /* ptes for mapping u page */
+	unsigned md_ss_addr;          /* single step address for ptrace */
+	unsigned md_ss_instr;         /* single step instruction for ptrace */
+	unsigned md_ss_taken_addr;    /* single step address for ptrace */
+	unsigned md_ss_taken_instr;   /* single step instruction for ptrace */
 };
diff --git a/sys/arch/mvme88k/include/reg.h b/sys/arch/mvme88k/include/reg.h
index 4908226d539..59827e812cb 100644
--- a/sys/arch/mvme88k/include/reg.h
+++ b/sys/arch/mvme88k/include/reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: reg.h,v 1.4 1999/02/09 06:36:27 smurph Exp $ */
+/*	$OpenBSD: reg.h,v 1.5 1999/09/27 20:46:19 smurph Exp $ */
 /*
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -32,6 +32,10 @@
  */
 #include <machine/pcb.h>
 
+#define reg m88100_saved_state
+#define r_
+
+#if 0
 struct reg {
     unsigned r_r[32];
     unsigned r_fpsr;
@@ -65,6 +69,7 @@ struct reg {
     unsigned r_scratch1; /* used by locore trap handling code */
     unsigned r_pad;      /* to make an even length */
 } ;
+#endif 
 
 struct fpreg {
     unsigned fp_fpecr;
diff --git a/sys/arch/mvme88k/include/spinlock.h b/sys/arch/mvme88k/include/spinlock.h
new file mode 100644
index 00000000000..31eac8b22bb
--- /dev/null
+++ b/sys/arch/mvme88k/include/spinlock.h
@@ -0,0 +1,10 @@
+/*	$OpenBSD: spinlock.h,v 1.1 1999/09/27 20:46:19 smurph Exp $	*/
+
+#ifndef _M88K_SPINLOCK_H_
+#define _M88K_SPINLOCK_H_
+
+#define _SPINLOCK_UNLOCKED	(0)
+#define _SPINLOCK_LOCKED	(1)
+typedef int _spinlock_lock_t;
+
+#endif
diff --git a/sys/arch/mvme88k/include/trap.h b/sys/arch/mvme88k/include/trap.h
index 9cf21334511..14eea437121 100644
--- a/sys/arch/mvme88k/include/trap.h
+++ b/sys/arch/mvme88k/include/trap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.h,v 1.4 1999/02/09 06:36:27 smurph Exp $ */
+/*	$OpenBSD: trap.h,v 1.5 1999/09/27 20:46:19 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1992 Carnegie Mellon University
@@ -41,32 +41,37 @@
 
 /* End of known constants */
 
-#define T_INSTFLT	3		/* instruction access exception */
-#define T_DATAFLT	4		/* data access exception */
-#define T_MISALGNFLT	5		/* misaligned access exception */
-#define T_ILLFLT	6		/* unimplemented opcode exception */
-#define T_BNDFLT	7		/* bounds check violation exception */
-#define T_ZERODIV	8		/* illegal divide exception */
-#define T_OVFFLT	9		/* integer overflow exception */
+#define T_INSTFLT    3		/* instruction access exception */
+#define T_DATAFLT    4		/* data access exception */
+#define T_MISALGNFLT 5		/* misaligned access exception */
+#define T_ILLFLT     6		/* unimplemented opcode exception */
+#define T_BNDFLT     7		/* bounds check violation exception */
+#define T_ZERODIV    8		/* illegal divide exception */
+#define T_OVFFLT     9		/* integer overflow exception */
 #define T_ERRORFLT	10		/* error exception */
-#define T_FPEPFLT	11		/* floating point precise exception */
-#define T_FPEIFLT	12		/* floating point imprecise exception */
-#define	T_ASTFLT	13		/* software trap */
+#define T_FPEPFLT    11		/* floating point precise exception */
+#define T_FPEIFLT    12		/* floating point imprecise exception */
+#define T_ASTFLT	   13		/* software trap */
 #if	DDB
 #define	T_KDB_ENTRY	14		/* force entry to kernel debugger */
 #define T_KDB_BREAK	15		/* break point hit */
 #define T_KDB_TRACE	16		/* trace */
 #endif /* DDB */
 #define T_UNKNOWNFLT	17		/* unknown exception */
-#define T_SIGTRAP	18		/* generate SIGTRAP */
-#define T_SIGSYS	19		/* generate SIGSYS */
-#define	T_STEPBPT	20		/* special breakpoint for single step */
-#define	T_USERBPT	21		/* user set breakpoint (for debugger) */
-#define	T_SYSCALL	22		/* Syscall */
-#define T_USER		23		/* user mode fault */
+#define T_SIGTRAP	   18		/* generate SIGTRAP */
+#define T_SIGSYS	   19		/* generate SIGSYS */
+#define T_STEPBPT	   20		/* special breakpoint for single step */
+#define T_USERBPT	   21		/* user set breakpoint (for debugger) */
+#define T_SYSCALL	   22		/* Syscall */
+#define T_NON_MASK	23		/* MVME197 Non-Maskable Interrupt */
 #if	DDB
 #define	T_KDB_WATCH	24		/* watchpoint hit */
 #endif /* DDB */
+#define T_197_READ   25    /* MVME197 Data Read Miss (Software Table Searches) */
+#define T_197_WRITE  26    /* MVME197 Data Write Miss (Software Table Searches) */
+#define T_197_INST   27    /* MVME197 Inst ATC Miss (Software Table Searches) */
+#define T_INT        28    /* interrupt exception */
+#define T_USER       29		/* user mode fault */
 
 #endif  _M88K_TRAP_H 
 
diff --git a/sys/arch/mvme88k/include/vmparam.h b/sys/arch/mvme88k/include/vmparam.h
index 44e13ded0b4..8823aaa8a62 100644
--- a/sys/arch/mvme88k/include/vmparam.h
+++ b/sys/arch/mvme88k/include/vmparam.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: vmparam.h,v 1.5 1999/02/09 06:36:27 smurph Exp $ */
+/*	$OpenBSD: vmparam.h,v 1.6 1999/09/27 20:46:19 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1992 Carnegie Mellon University
@@ -155,7 +155,7 @@
 #define	VM_MAX_ADDRESS	((vm_offset_t) 0xffc00000U)
 
 #define	VM_MIN_USER_ADDRESS	((vm_offset_t) 0)
-#define	VM_MAX_USER_ADDRESS	((vm_offset_t) 0xffc00000U)
+#define	VM_MAX_USER_ADDRESS  ((vm_offset_t) 0xffc00000U)
 
 /* on vme188, max = 0xf0000000 */