diff options
| author | Dale Rahn <drahn@cvs.openbsd.org> | 2009-05-24 00:36:42 +0000 |
|---|---|---|
| committer | Dale Rahn <drahn@cvs.openbsd.org> | 2009-05-24 00:36:42 +0000 |
| commit | b1b471866bd1bcf489ec3badc2924fb42b49e2e3 (patch) | |
| tree | 216daad8f9e3ff431633e888f403d41443469677 /sys/arch | |
| parent | 8d62c802920a9ab72bdb75d7853ad1454b204f8a (diff) | |
Rework for 3530.
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/beagle/dev/prcm.c | 360 | ||||
| -rw-r--r-- | sys/arch/beagle/dev/prcmvar.h | 68 |
2 files changed, 188 insertions, 240 deletions
diff --git a/sys/arch/beagle/dev/prcm.c b/sys/arch/beagle/dev/prcm.c index 01e54d42cdc..a5acb0bd073 100644 --- a/sys/arch/beagle/dev/prcm.c +++ b/sys/arch/beagle/dev/prcm.c @@ -1,4 +1,4 @@ -/* $OpenBSD: prcm.c,v 1.1 2009/05/08 03:13:26 drahn Exp $ */ +/* $OpenBSD: prcm.c,v 1.2 2009/05/24 00:36:41 drahn Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * @@ -28,188 +28,130 @@ #include <beagle/beagle/ahb.h> #include <beagle/dev/prcmvar.h> -#define PRCM_REVISION 0x000 -#define PRCM_SYSCONFIG 0x010 -#define PRCM_IRQSTATUS_MPU 0x018 -#define PRCM_IRQENABLE_MPU 0x01c -#define PRCM_VOLTCTRL 0x050 -#define PRCM_VOLTST 0x054 -#define PRCM_CLKSRC_CTRL 0x060 -#define PRCM_CLKOUT_CTRL 0x070 -#define PRCM_CLKEMUL_CTRL 0x078 -#define PRCM_CLKCFG_CTRL 0x080 -#define PRCM_CLKCFG_STATUS 0x084 -#define PRCM_VOLTSETUP 0x090 -#define PRCM_CLKSSETUP 0x094 -#define PRCM_POLCTRL 0x098 -#define PRCM_GP1 0x0b0 -#define PRCM_GP2 0x0b4 -#define PRCM_GP3 0x0b8 -#define PRCM_GP4 0x0bc -#define PRCM_GP5 0x0c0 -#define PRCM_GP6 0x0c4 -#define PRCM_GP7 0x0c8 -#define PRCM_GP8 0x0cc -#define PRCM_GP9 0x0d0 -#define PRCM_GP10 0x0d4 -#define PRCM_GP11 0x0d8 -#define PRCM_GP12 0x0dc -#define PRCM_GP13 0x0e0 -#define PRCM_GP14 0x0e4 -#define PRCM_GP15 0x0e8 -#define PRCM_GP16 0x0ec -#define PRCM_GP17 0x0f0 -#define PRCM_GP18 0x0f4 -#define PRCM_GP19 0x0f8 -#define PRCM_GP20 0x0fc - -#define CM_CLKSEL_MPU 0x140 -#define CM_CLKSTCTRL_MPU 0x148 -#define RM_RSTST_MPU 0x158 -#define PM_WKDEP_MPU 0x1C8 -#define PM_EVGENCTRL_MPU 0x1D4 -#define PM_EVEGENONTIM_MPU 0x1D8 -#define PM_EVEGENOFFTIM_MPU 0x1DC -#define PM_PWSTCTRL_MPU 0x1E0 -#define PM_PWSTST_MPU 0x1E4 -#define CM_FCLKEN1_CORE 0x200 -#define CM_FCLKEN1_CORE_DSS1 0x00000001 -#define CM_FCLKEN1_CORE_DSS2 0x00000002 -#define CM_FCLKEN1_CORE_TV 0x00000004 -#define CM_FCLKEN1_CORE_VLYNQ 0x00000008 -#define CM_FCLKEN1_CORE_GP2 0x00000010 -#define CM_FCLKEN1_CORE_GP3 0x00000020 -#define CM_FCLKEN1_CORE_GP4 0x00000040 -#define CM_FCLKEN1_CORE_GP5 0x00000080 -#define CM_FCLKEN1_CORE_GP6 0x00000100 -#define CM_FCLKEN1_CORE_GP7 0x00000200 -#define CM_FCLKEN1_CORE_GP8 0x00000400 -#define CM_FCLKEN1_CORE_GP9 0x00000800 -#define CM_FCLKEN1_CORE_GP10 0x00001000 -#define CM_FCLKEN1_CORE_GP11 0x00002000 -#define CM_FCLKEN1_CORE_GP12 0x00004000 -#define CM_FCLKEN1_CORE_MCBSP1 0x00008000 -#define CM_FCLKEN1_CORE_MCBSP2 0x00010000 -#define CM_FCLKEN1_CORE_MCSPI1 0x00020000 -#define CM_FCLKEN1_CORE_MCSPI2 0x00040000 -#define CM_FCLKEN1_CORE_I2C1 0x00080000 -#define CM_FCLKEN1_CORE_I2C2 0x00100000 -#define CM_FCLKEN1_CORE_UART1 0x00200000 -#define CM_FCLKEN1_CORE_UART2 0x00400000 -#define CM_FCLKEN1_CORE_HDQ 0x00800000 -#define CM_FCLKEN1_CORE_EAC 0x01000000 -#define CM_FCLKEN1_CORE_FAC 0x02000000 -#define CM_FCLKEN1_CORE_MMC 0x04000000 -#define CM_FCLKEN1_CORE_MSPR0 0x08000000 -#define CM_FCLKEN1_CORE_WDT3 0x10000000 -#define CM_FCLKEN1_CORE_WDT4 0x20000000 -#define CM_FCLKEN1_CORE_CAM 0x80000000 -#define CM_FCLKEN2_CORE 0x204 -#define CM_FCLKEN2_CORE_UART3 0x00000004 -#define CM_FCLKEN2_CORE_SSI 0x00000002 -#define CM_FCLKEN2_CORE_USB 0x00000001 -#define CM_ICLKEN1_CORE 0x210 -#define CM_ICLKEN1_CORE_DSS1 0x00000001 -#define CM_ICLKEN1_CORE_VLYNQ 0x00000008 -#define CM_ICLKEN1_CORE_GP2 0x00000010 -#define CM_ICLKEN1_CORE_GP3 0x00000020 -#define CM_ICLKEN1_CORE_GP4 0x00000040 -#define CM_ICLKEN1_CORE_GP5 0x00000080 -#define CM_ICLKEN1_CORE_GP6 0x00000100 -#define CM_ICLKEN1_CORE_GP7 0x00000200 -#define CM_ICLKEN1_CORE_GP8 0x00000400 -#define CM_ICLKEN1_CORE_GP9 0x00000800 -#define CM_ICLKEN1_CORE_GP10 0x00001000 -#define CM_ICLKEN1_CORE_GP11 0x00002000 -#define CM_ICLKEN1_CORE_GP12 0x00004000 -#define CM_ICLKEN1_CORE_MCBSP1 0x00008000 -#define CM_ICLKEN1_CORE_MCBSP2 0x00010000 -#define CM_ICLKEN1_CORE_MCSPI1 0x00020000 -#define CM_ICLKEN1_CORE_MCSPI2 0x00040000 -#define CM_ICLKEN1_CORE_I2C1 0x00080000 -#define CM_ICLKEN1_CORE_I2C2 0x00100000 -#define CM_ICLKEN1_CORE_UART1 0x00200000 -#define CM_ICLKEN1_CORE_UART2 0x00400000 -#define CM_ICLKEN1_CORE_HDQ 0x00800000 -#define CM_ICLKEN1_CORE_EAC 0x01000000 -#define CM_ICLKEN1_CORE_FAC 0x02000000 -#define CM_ICLKEN1_CORE_MMC 0x04000000 -#define CM_ICLKEN1_CORE_MSPR0 0x08000000 -#define CM_ICLKEN1_CORE_WDT3 0x10000000 -#define CM_ICLKEN1_CORE_WDT4 0x20000000 -#define CM_ICLKEN1_CORE_MAILBOX 0x40000000 -#define CM_ICLKEN1_CORE_CAM 0x80000000 -#define CM_ICLKEN2_CORE 0x214 -#define CM_ICLKEN4_CORE 0x21C -#define CM_IDLEST1_CORE 0x220 -#define CM_IDLEST2_CORE 0x224 -#define CM_IDLEST4_CORE 0x22C -#define CM_AUTOIDLE1_CORE 0x230 -#define CM_AUTOIDLE2_CORE 0x234 -#define CM_AUTOIDLE3_CORE 0x238 -#define CM_AUTOIDLE4_CORE 0x23C -#define CM_CLKSEL1_CORE 0x240 -#define CM_CLKSEL2_CORE 0x244 -#define CM_CLKSTCTRL_CORE 0x248 -#define PM_WKEN1_CORE 0x2A0 -#define PM_WKEN2_CORE 0x2A4 -#define PM_WKST1_CORE 0x2B0 -#define PM_WKST2_CORE 0x2B4 -#define PM_WKDEP_CORE 0x2C8 -#define PM_PWSTCTRL_CORE 0x2E0 -#define PM_PWSTST_CORE 0x2E4 -#define CM_FCLKEN_GFX 0x300 -#define CM_ICLKEN_GFX 0x310 - -#define CM_IDLEST_GFX 0x320 -#define CM_CLKSEL_GFX 0x340 -#define CM_CLKSTCTRL_GFX 0x348 -#define RM_RSTCTRL_GFX 0x350 -#define RM_RSTST_GFX 0x358 -#define PM_WKDEP_GFX 0x3C8 -#define PM_PWSTCTRL_GFX 0x3E0 -#define PM_PWSTST_GFX 0x3E4 -#define CM_FCLKEN_WKUP 0x400 +#define CM_FCLKEN_IVA2 0x0000 +#define CM_CLKEN_PLL_IVA2 0x0004 +#define CM_IDLEST_IVA2 0x0020 +#define CM_IDLEST_PLL_IVA2 0x0024 +#define CM_AUTOIDLE_PLL_IVA2 0x0034 +#define CM_CLKSEL1_PLL_IVA2 0x0040 +#define CM_CLKSEL2_PLL_IVA2 0x0044 +#define CM_CLKSTCTRL_IVA2 0x0048 +#define CM_CLKSTST_IVA2 0x004c + +#define PRCM_REVISION 0x0800 +#define PRCM_SYSCONFIG 0x0810 + +#define CM_CLKSEL_MPU 0x0940 +#define CM_CLKSTCTRL_MPU 0x0948 +#define RM_RSTST_MPU 0x0958 +#define PM_WKDEP_MPU 0x09C8 +#define PM_EVGENCTRL_MPU 0x09D4 +#define PM_EVEGENONTIM_MPU 0x09D8 +#define PM_EVEGENOFFTIM_MPU 0x09DC +#define PM_PWSTCTRL_MPU 0x09E0 +#define PM_PWSTST_MPU 0x09E4 +#define CM_FCLKEN1_CORE 0x0a00 +#define CM_FCLKEN1_CORE_MSK 0x41fffe00 + +#define CM_FCLKEN2_CORE 0x0a04 +#define CM_FCLKEN2_CORE_MSK 0x00000000 +#define CM_FCLKEN3_CORE 0x0a08 +#define CM_FCLKEN3_CORE_MSK 0x00000007 +#define CM_CORE_EN_USBTLL (2+64) +#define CM_CORE_EN_TS (1+64) +#define CM_CORE_EN_CPEFUSE (0+64) + +#define CM_ICLKEN1_CORE 0x0a10 +#define CM_ICLKEN1_CORE_MSK 0x7ffffed2 +#define CM_ICLKEN2_CORE 0x0a14 +#define CM_ICLKEN2_CORE_MSK 0x0000001f +#define CM_ICLKEN3_CORE 0x0a18 +#define CM_ICLKEN3_CORE_MSK 0x00000004 +#define CM_ICLKEN4_CORE 0x0a1C +#define CM_IDLEST1_CORE 0x0a20 +#define CM_IDLEST2_CORE 0x0a24 +#define CM_IDLEST4_CORE 0x0a2C +#define CM_AUTOIDLE1_CORE 0x0a30 +#define CM_AUTOIDLE2_CORE 0x0a34 +#define CM_AUTOIDLE3_CORE 0x0a38 +#define CM_AUTOIDLE4_CORE 0x0a3C +#define CM_CLKSEL1_CORE 0x0a40 +#define CM_CLKSEL2_CORE 0x0a44 +#define CM_CLKSTCTRL_CORE 0x0a48 +#define PM_WKEN1_CORE 0x0aA0 +#define PM_WKEN2_CORE 0x0aA4 +#define PM_WKST1_CORE 0x0aB0 +#define PM_WKST2_CORE 0x0aB4 +#define PM_WKDEP_CORE 0x0aC8 +#define PM_PWSTCTRL_CORE 0x0aE0 +#define PM_PWSTST_CORE 0x0aE4 +#define CM_FCLKEN_GFX 0x0b00 +#define CM_ICLKEN_GFX 0x0b10 + +#define CM_IDLEST_GFX 0x0b20 +#define CM_CLKSEL_GFX 0x0b40 +#define CM_CLKSTCTRL_GFX 0x0b48 +#define RM_RSTCTRL_GFX 0x0b50 +#define RM_RSTST_GFX 0x0b58 +#define PM_WKDEP_GFX 0x0bC8 +#define PM_PWSTCTRL_GFX 0x0bE0 +#define PM_PWSTST_GFX 0x0bE4 +#define CM_FCLKEN_WKUP 0x0c00 #define CM_FCLKEN_WKUP_GPT1 1 #define CM_FCLKEN_WKUP_GPIOS 4 #define CM_FCLKEN_WKUP_MPU_WDT 8 -#define CM_ICLKEN_WKUP 0x410 +#define CM_ICLKEN_WKUP 0xc10 #define CM_ICLKEN_WKUP_GPT1 0x01 #define CM_ICLKEN_WKUP_32KSYNC 0x02 #define CM_ICLKEN_WKUP_GPIOS 0x04 #define CM_ICLKEN_WKUP_MPU_WDT 0x08 #define CM_ICLKEN_WKUP_WDT1 0x10 #define CM_ICLKEN_WKUP_OMAPCTRL 0x20 -#define CM_IDLEST_WKUP 0x420 -#define CM_AUTOIDLE_WKUP 0x430 -#define CM_CLKSEL_WKUP 0x440 -#define RM_RSTCTRL_WKUP 0x450 -#define RM_RSTTIME_WKUP 0x454 -#define RM_RSTST_WKUP 0x458 -#define PM_WKEN_WKUP 0x4A0 -#define PM_WKST_WKUP 0x4B0 -#define CM_CLKEN_PLL 0x500 -#define CM_IDLEST_CKGEN 0x520 -#define CM_AUTOIDLE_PLL 0x530 -#define CM_CLKSEL1_PLL 0x540 -#define CM_CLKSEL2_PLL 0x544 -#define CM_FCLKEN_DSP 0x800 -#define CM_ICLKEN_DSP 0x810 -#define CM_IDLEST_DSP 0x820 -#define CM_AUTOIDLE_DSP 0x830 -#define CM_CLKSEL_DSP 0x840 -#define CM_CLKSTCTRL_DSP 0x848 -#define RM_RSTCTRL_DSP 0x850 -#define RM_RSTST_DSP 0x858 -#define PM_WKEN_DSP 0x8A0 -#define PM_WKDEP_DSP 0x8C8 -#define PM_PWSTCTRL_DSP 0x8E0 -#define PM_PWSTST_DSP 0x8E4 -#define PRCM_IRQSTATUS_DSP 0x8F0 -#define PRCM_IRQENABLE_DSP 0x8F4 -#define PRCM_IRQSTATUS_IVA 0x8F8 -#define PRCM_IRQENABLE_IVA 0x8FC -#define PRCM_SIZE 0x1000 +#define CM_IDLEST_WKUP 0x0c20 +#define CM_AUTOIDLE_WKUP 0x0c30 +#define CM_CLKSEL_WKUP 0x0c40 +#define RM_RSTCTRL_WKUP 0x0c50 +#define RM_RSTTIME_WKUP 0x0c54 +#define RM_RSTST_WKUP 0x0c58 +#define PM_WKEN_WKUP 0x0cA0 +#define PM_WKST_WKUP 0x0cB0 +#define CM_CLKEN_PLL 0x0d00 +#define CM_IDLEST_CKGEN 0x0d20 +#define CM_AUTOIDLE_PLL 0x0d30 +#define CM_CLKSEL1_PLL 0x0d40 +#define CM_CLKSEL2_PLL 0x0d44 +#define CM_FCLKEN_PER 0x1000 +#define CM_ICLKEN_PER 0x1010 +#define CM_IDLEST_PER 0x1020 +#define CM_AUTOIDLE_PER 0x1030 +#define CM_CLKSEL_PER 0x1040 +#define CM_SLEEPDEP_PER 0x1044 +#define CM_CLKSTCTRL_PER 0x1048 +#define CM_CLKSTST_PER 0x104C + +#define CM_CLKSEL1_EMU 0x5140 +#define CM_CLKSTCTRL_EMU 0x5148 +#define CM_CLKSTST_EMU 0x514C +#define CM_CLKSEL2_EMU 0x5150 +#define CM_CLKSEL3_EMU 0x5154 + +#define CM_POLCTRL 0x529C + +#define CM_IDLEST_NEON 0x5320 +#define CM_CLKSTCTRL_NEON 0x5348 + +#define CM_FCLKEN_USBHOST 0x5400 +#define CM_ICLKEN_USBHOST 0x5410 +#define CM_IDLEST_USBHOST 0x5420 +#define CM_AUTOIDLE_USBHOST 0x5430 +#define CM_SLEEPDEP_USBHOST 0x5444 +#define CM_CLKSTCTRL_USBHOST 0x5448 +#define CM_CLKSTST_USBHOST 0x544C + + + + +#define PRCM_SIZE 0x2000 bus_space_tag_t prcm_iot; bus_space_handle_t prcm_ioh; @@ -263,6 +205,7 @@ prcm_attach(struct device *parent, struct device *self, void *args) // bus_space_write_4(prcm_iot, prcm_ioh, #endif +#if 0 reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_FCLKEN1_CORE); reg |= CM_FCLKEN1_CORE_GP3|CM_FCLKEN1_CORE_GP2; bus_space_write_4(prcm_iot, prcm_ioh, CM_FCLKEN1_CORE, reg); @@ -277,25 +220,29 @@ prcm_attach(struct device *parent, struct device *self, void *args) reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_ICLKEN_WKUP); reg |= CM_ICLKEN_WKUP_MPU_WDT | CM_ICLKEN_WKUP_GPT1; bus_space_write_4(prcm_iot, prcm_ioh, CM_ICLKEN_WKUP, reg); +#endif } void prcm_setclock(int clock, int speed) { -#if 0 - u_int32_t reg; - if (clock == 0) { - reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_CLKSEL_WKUP); - reg &= ~( 3 << ((clock -1) *2 )); - reg |= ( speed << ((clock -1) *2 )); +#if 1 + u_int32_t oreg, reg, mask; + if (clock == 1) { + oreg = bus_space_read_4(prcm_iot, prcm_ioh, CM_CLKSEL_WKUP); + mask = 1; + reg = (oreg &~mask) | (speed & mask); + printf(" prcm_setclock old %08x new %08x", oreg, reg ); bus_space_write_4(prcm_iot, prcm_ioh, CM_CLKSEL_WKUP, reg); - } else if (clock > 0 && clock < 13) { - reg = bus_space_read_4(prcm_iot, prcm_ioh, CM_CLKSEL2_CORE); + } else if (clock >= 2 && clock <= 9) { + int shift = (clock-2); + oreg = bus_space_read_4(prcm_iot, prcm_ioh, CM_CLKSEL_PER); - reg &= ~( 3 << (clock * 2)); - reg |= ( speed << ((clock -1) *2 )); + mask = 1 << (mask); + reg = (oreg & ~mask) | ( (speed << shift) & mask); + printf(" prcm_setclock old %08x new %08x", oreg, reg); - bus_space_write_4(prcm_iot, prcm_ioh, CM_CLKSEL2_CORE, reg); + bus_space_write_4(prcm_iot, prcm_ioh, CM_CLKSEL_PER, reg); } else panic("prcm_setclock invalid clock %d\n", clock); #endif @@ -304,32 +251,39 @@ prcm_setclock(int clock, int speed) void prcm_enableclock(int bit) { -#if 0 - u_int32_t fclk, iclk; + u_int32_t fclk, iclk, fmask, imask, mbit; int freg, ireg; + printf("prcm_enableclock %d:", bit); - if (bit < 31){ + if (bit < 32){ freg = CM_FCLKEN1_CORE; ireg = CM_ICLKEN1_CORE; - } else { + fmask = CM_FCLKEN1_CORE_MSK; + imask = CM_ICLKEN1_CORE_MSK; + + } else if (bit < 64) { freg = CM_FCLKEN2_CORE; ireg = CM_ICLKEN2_CORE; + fmask = CM_FCLKEN2_CORE_MSK; + imask = CM_ICLKEN2_CORE_MSK; + } else { + freg = CM_FCLKEN3_CORE; + ireg = CM_ICLKEN3_CORE; + fmask = CM_FCLKEN3_CORE_MSK; + imask = CM_ICLKEN3_CORE_MSK; } - fclk = bus_space_read_4(prcm_iot, prcm_ioh, freg); - iclk = bus_space_read_4(prcm_iot, prcm_ioh, ireg); - fclk |= 1 << (bit & 0x1f); - iclk |= 1 << (bit & 0x1f); + mbit = 1 << (bit & 0x1f); + if (fmask & mbit) { /* dont access the register if bit isn't present */ + fclk = bus_space_read_4(prcm_iot, prcm_ioh, freg); + bus_space_write_4(prcm_iot, prcm_ioh, freg, fclk | mbit); + printf(" fclk %08x %08x", fclk, fclk | mbit); + } - /* mask reserved bits (XXX?) */ - if (bit > 31){ - fclk &= 0xbfffffff; - iclk &= 0xfffffff9; - } else { - fclk &= 0x00000007; - iclk &= 0x00000007; + if (imask & mbit) { /* dont access the register if bit isn't present */ + iclk = bus_space_read_4(prcm_iot, prcm_ioh, ireg); + bus_space_write_4(prcm_iot, prcm_ioh, ireg, iclk | mbit); + printf(" iclk %08x %08x", iclk, iclk | mbit); } - bus_space_write_4(prcm_iot, prcm_ioh, freg, fclk); - bus_space_write_4(prcm_iot, prcm_ioh, ireg, iclk); -#endif + printf ("\n"); } diff --git a/sys/arch/beagle/dev/prcmvar.h b/sys/arch/beagle/dev/prcmvar.h index 559117258ca..f449b994d85 100644 --- a/sys/arch/beagle/dev/prcmvar.h +++ b/sys/arch/beagle/dev/prcmvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: prcmvar.h,v 1.1 2009/05/08 03:13:26 drahn Exp $ */ +/* $OpenBSD: prcmvar.h,v 1.2 2009/05/24 00:36:41 drahn Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * @@ -18,44 +18,38 @@ void prcm_setclock(int clock, int speed); #define PRCM_CLK_SPEED_32 0 #define PRCM_CLK_SPEED_SYS 1 -#define PRCM_CLK_SPEED_EXT 2 void prcm_enableclock(int bit); -#define PRCM_CLK_EN_DSS1 0 -#define PRCM_CLK_EN_DSS2 1 -#define PRCM_CLK_EN_TV 2 -#define PRCM_CLK_EN_VLYNQ 3 -#define PRCM_CLK_EN_GP2 4 -#define PRCM_CLK_EN_GP 5 -#define PRCM_CLK_EN_GP4 6 -#define PRCM_CLK_EN_GP5 7 -#define PRCM_CLK_EN_GP6 8 -#define PRCM_CLK_EN_GP7 9 -#define PRCM_CLK_EN_GP8 10 -#define PRCM_CLK_EN_GP9 11 -#define PRCM_CLK_EN_GP10 12 -#define PRCM_CLK_EN_GP11 13 -#define PRCM_CLK_EN_GP12 14 -#define PRCM_CLK_EN_MCBSP1 15 -#define PRCM_CLK_EN_MCBSP2 16 -#define PRCM_CLK_EN_MCSPI1 17 -#define PRCM_CLK_EN_MCSPI2 18 -#define PRCM_CLK_EN_I2C1 19 -#define PRCM_CLK_EN_I2C2 20 -#define PRCM_CLK_EN_UART1 21 -#define PRCM_CLK_EN_UART2 22 -#define PRCM_CLK_EN_HDQ 23 -#define PRCM_CLK_EN_EAC 24 -#define PRCM_CLK_EN_FAC 25 -#define PRCM_CLK_EN_MMC 26 -#define PRCM_CLK_EN_MSPR0 27 -#define PRCM_CLK_EN_WDT3 28 -#define PRCM_CLK_EN_WDT4 29 -#define PRCM_CLK_EN_MAILBOX 30 -#define PRCM_CLK_EN_CAM 31 -#define PRCM_CLK_EN_USB 32 -#define PRCM_CLK_EN_SSI 33 -#define PRCM_CLK_EN_UART3 34 +#define PRCM_CLK_EN_MMC3 (30) +#define PRCM_CLK_EN_ICR (29) +#define PRCM_CLK_EN_AES2 (28) +#define PRCM_CLK_EN_SHA12 (27) +#define PRCM_CLK_EN_DES2 (26) +#define PRCM_CLK_EN_MMC2 (25) +#define PRCM_CLK_EN_MMC1 (24) +#define PRCM_CLK_EN_MSPRO (23) +#define PRCM_CLK_EN_HDQ (22) +#define PRCM_CLK_EN_MCSPI4 (21) +#define PRCM_CLK_EN_MCSPI3 (20) +#define PRCM_CLK_EN_MCSPI2 (19) +#define PRCM_CLK_EN_MCSPI1 (18) +#define PRCM_CLK_EN_I2C3 (17) +#define PRCM_CLK_EN_I2C2 (16) +#define PRCM_CLK_EN_I2C1 (15) +#define PRCM_CLK_EN_UART2 (14) +#define PRCM_CLK_EN_UART1 (13) +#define PRCM_CLK_EN_GPT11 (12) +#define PRCM_CLK_EN_GPT10 (11) +#define PRCM_CLK_EN_MCBSP5 (10) +#define PRCM_CLK_EN_MCBSP1 (9) +#define PRCM_CLK_EN_MAILBOXES (7) +#define PRCM_CLK_EN_OMAPCTRL (6) +#define PRCM_CLK_EN_HSOTGUSB (4) +#define PRCM_CLK_EN_SDRC (1) + +#define CM_CORE_EN_USBTLL (2+64) +#define CM_CORE_EN_TS (1+64) +#define CM_CORE_EN_CPEFUSE (0+64) /* need interface for CM_AUTOIDLE */ |