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authorMiod Vallat <miod@cvs.openbsd.org>2011-09-16 17:20:08 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2011-09-16 17:20:08 +0000
commitbec30f54520515e551ee413328bfc439c39f23b6 (patch)
treef87c2d6060aba265230a96f54ebd54a559ccae8a /sys/arch
parentba6aaeb5795a5f381673c75c9b5c3b4c3d26ca36 (diff)
Fix a bunch of typos: manaul, monnitor, machiune, autload.
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/hppa/gsc/lpt_gsc.c4
-rw-r--r--sys/arch/vax/include/mtpr.h6
2 files changed, 5 insertions, 5 deletions
diff --git a/sys/arch/hppa/gsc/lpt_gsc.c b/sys/arch/hppa/gsc/lpt_gsc.c
index 6a4a40ee190..5f31d065c51 100644
--- a/sys/arch/hppa/gsc/lpt_gsc.c
+++ b/sys/arch/hppa/gsc/lpt_gsc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: lpt_gsc.c,v 1.11 2004/09/14 22:32:01 mickey Exp $ */
+/* $OpenBSD: lpt_gsc.c,v 1.12 2011/09/16 17:20:07 miod Exp $ */
/*
* Copyright (c) 1998 Michael Shalayeff
@@ -83,7 +83,7 @@ struct cfattach lpt_gsc_ca = {
*
* 2) You should be able to write to and read back the same value
* to the control port lower 5 bits, the upper 3 bits are reserved
- * per the IBM PC technical reference manauls and different boards
+ * per the IBM PC technical reference manuals and different boards
* do different things with them. Do an alternating zeros, alternating
* ones, walking zero, and walking one test to check for stuck bits.
*
diff --git a/sys/arch/vax/include/mtpr.h b/sys/arch/vax/include/mtpr.h
index 9aa610f86ab..1cd7df195e8 100644
--- a/sys/arch/vax/include/mtpr.h
+++ b/sys/arch/vax/include/mtpr.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: mtpr.h,v 1.6 2011/03/23 16:54:37 pirofti Exp $ */
+/* $OpenBSD: mtpr.h,v 1.7 2011/09/16 17:20:07 miod Exp $ */
/* $NetBSD: mtpr.h,v 1.12 1999/06/06 19:06:29 ragge Exp $ */
/*
@@ -77,7 +77,7 @@
#define PR_TXDB 35 /* Console Transmit D/B */
#define PR_TBDR 36 /* Translation Buffer Group Disable Register 11/750 */
#define PR_CADR 37 /* Cache Disable Register 11/750 */
-#define PR_MCESR 38 /* Machiune Check Error Summary Register 11/750 */
+#define PR_MCESR 38 /* Machine Check Error Summary Register 11/750 */
#define PR_CAER 39 /* Cache Error Register 11/750 */
#define PR_ACCS 40 /* Accelerator control register */
#define PR_SAVISP 41 /* Console Saved ISP */
@@ -98,7 +98,7 @@
#define PR_TBIS 58 /* Trans. Buf. Invalidate Single */
#define PR_TBDATA 59 /* Translation Buffer Data */
#define PR_MBRK 60 /* Microprogram Break */
-#define PR_PMR 61 /* Performance Monnitor Enable */
+#define PR_PMR 61 /* Performance Monitor Enable */
#define PR_SID 62 /* System ID Register */
#define PR_TBCHK 63 /* Translation Buffer Check */