Introduce various CPU_### options to enable cpu-specific code or workarounds;

be sure to rerun config(8) on your kernel configuration files.

10 files changed, 65 insertions, 46 deletions

diff --git a/sys/arch/mips64/conf/files.mips64 b/sys/arch/mips64/conf/files.mips64
index a95e12538f3..f1e2eafb434 100644
--- a/sys/arch/mips64/conf/files.mips64
+++ b/sys/arch/mips64/conf/files.mips64
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.mips64,v 1.13 2009/11/25 17:39:51 syuu Exp $
+#	$OpenBSD: files.mips64,v 1.14 2009/12/12 20:06:50 miod Exp $
 
 file	arch/mips64/mips64/arcbios.c		arcbios
 file	arch/mips64/mips64/clock.c
@@ -14,8 +14,8 @@ file	arch/mips64/mips64/trap.c
 file	arch/mips64/mips64/vm_machdep.c
 
 file	arch/mips64/mips64/cache_loongson2.S	cpu_loongson2
-file	arch/mips64/mips64/cache_r5k.S
-file	arch/mips64/mips64/cache_r10k.S
+file	arch/mips64/mips64/cache_r5k.S		cpu_r5000 | cpu_rm7000
+file	arch/mips64/mips64/cache_r10k.S		cpu_r10000
 file	arch/mips64/mips64/context.S
 file	arch/mips64/mips64/cp0access.S
 file	arch/mips64/mips64/exception.S
diff --git a/sys/arch/mips64/mips64/context.S b/sys/arch/mips64/mips64/context.S
index 7ae09757bdb..919feb9eaa2 100644
--- a/sys/arch/mips64/mips64/context.S
+++ b/sys/arch/mips64/mips64/context.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: context.S,v 1.33 2009/12/08 22:14:43 miod Exp $ */
+/*	$OpenBSD: context.S,v 1.34 2009/12/12 20:07:10 miod Exp $ */
 
 /*
  * Copyright (c) 2002-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -72,27 +72,11 @@ LEAF(savectx, 0)
 END(savectx)
 
 LEAF(cpu_idle_enter, 0)
-#if defined(TGT_CP7000) || defined(TGT_CP7000G)
-	PTR_L	t2, misc_h		# if non zero, do Ocelot LEDs.
-	beqz	t2, 1f
-	li	t0, 0x40
-	sb	t0, 0x0d(t2)
-1:
-#endif
-
 	j	ra
 	nop
 END(cpu_idle_enter)
 
 LEAF(cpu_idle_leave, 0)
-#if defined(TGT_CP7000) || defined(TGT_CP7000G)
-	PTR_L	t2, misc_h		# if non zero, do Ocelot LEDs.
-	beqz	t2, 1f
-	li	t0, 0x40
-	sb	t0, 0x0c(t2)
-1:
-#endif
-
 	j	ra
 	nop
 END(cpu_idle_leave)
diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S
index 94ec5879e65..5db098abca8 100644
--- a/sys/arch/mips64/mips64/tlbhandler.S
+++ b/sys/arch/mips64/mips64/tlbhandler.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tlbhandler.S,v 1.24 2009/12/07 19:05:59 miod Exp $ */
+/*	$OpenBSD: tlbhandler.S,v 1.25 2009/12/12 20:07:10 miod Exp $ */
 
 /*
  * Copyright (c) 1995-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -56,6 +56,7 @@
  */
 	.set	noat
 
+#if defined(CPU_R5000) || defined(CPU_RM7000)
 	.globl	tlb_miss_err_r5k
 	.ent	tlb_miss_err_r5k, 0
 tlb_miss_err_r5k:
@@ -80,6 +81,7 @@ tlb_miss_err_r5k:
 	j	k_tlb_inv
 	 nop
 	.end	tlb_miss_err_r5k
+#endif	/* CPU_R5000 || CPU_RM7000 */
 
 	.globl	tlb_miss
 	.ent	tlb_miss, 0
diff --git a/sys/arch/sgi/conf/GENERIC-IP27 b/sys/arch/sgi/conf/GENERIC-IP27
index 155d6dfe607..e28f22e5550 100644
--- a/sys/arch/sgi/conf/GENERIC-IP27
+++ b/sys/arch/sgi/conf/GENERIC-IP27
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC-IP27,v 1.24 2009/11/18 19:03:25 miod Exp $
+#	$OpenBSD: GENERIC-IP27,v 1.25 2009/12/12 20:07:10 miod Exp $
 #
 # THIS KERNEL IS FOR Origin, Onyx, Fuel, Tezro (IP27, IP35) SYSTEMS ONLY.
 #
@@ -28,6 +28,7 @@ option		USBVERBOSE
 # Define what targets to support
 option		TGT_ORIGIN	# IP27/IP35
 option		TGT_COHERENT
+option		CPU_R10000	# R10000/R12000/R14000/R16000 support
 
 # Specify storage configuration (it's a joke..)
 config		bsd	swap generic
diff --git a/sys/arch/sgi/conf/GENERIC-IP30 b/sys/arch/sgi/conf/GENERIC-IP30
index 3bde7adfb49..7c526e581d5 100644
--- a/sys/arch/sgi/conf/GENERIC-IP30
+++ b/sys/arch/sgi/conf/GENERIC-IP30
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC-IP30,v 1.19 2009/11/10 15:50:09 jsing Exp $
+#	$OpenBSD: GENERIC-IP30,v 1.20 2009/12/12 20:07:10 miod Exp $
 #
 # THIS KERNEL IS FOR Octane and Octane 2 (IP30) SYSTEMS ONLY.
 #
@@ -28,6 +28,7 @@ option		USBVERBOSE
 # Define what targets to support
 option		TGT_OCTANE	# Octane, Octane 2
 option		TGT_COHERENT
+option		CPU_R10000	# R10000/R12000/R14000/R16000 support
 
 # Specify storage configuration (it's a joke..)
 config		bsd	swap generic
diff --git a/sys/arch/sgi/conf/GENERIC-IP32 b/sys/arch/sgi/conf/GENERIC-IP32
index af3a6e64838..86a6752f931 100644
--- a/sys/arch/sgi/conf/GENERIC-IP32
+++ b/sys/arch/sgi/conf/GENERIC-IP32
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC-IP32,v 1.12 2009/11/07 21:42:07 miod Exp $
+#	$OpenBSD: GENERIC-IP32,v 1.13 2009/12/12 20:07:10 miod Exp $
 #
 # THIS KERNEL IS FOR O2 (IP32) SYSTEMS ONLY.
 #
@@ -28,6 +28,9 @@ option		USER_PCICONF	# User-space PCI configuration
 
 # Define what targets to support
 option		TGT_O2		# O2, O2+
+option		CPU_R5000	# R5000/RM5200 support
+option		CPU_RM7000	# RM7000 support
+option		CPU_R10000	# R10000/R12000/R14000/R16000 support
 
 # Specify storage configuration (it's a joke..)
 config		bsd	swap generic
diff --git a/sys/arch/sgi/conf/RAMDISK-IP27 b/sys/arch/sgi/conf/RAMDISK-IP27
index 2b5b534684e..1dec8c299c4 100644
--- a/sys/arch/sgi/conf/RAMDISK-IP27
+++ b/sys/arch/sgi/conf/RAMDISK-IP27
@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK-IP27,v 1.15 2009/11/07 21:42:07 miod Exp $
+#	$OpenBSD: RAMDISK-IP27,v 1.16 2009/12/12 20:07:10 miod Exp $
 #
 # THIS KERNEL IS FOR Origin, Onyx, Fuel, Tezro (IP27, IP35) SYSTEMS ONLY.
 
@@ -36,6 +36,7 @@ option		RAMDISK_HOOKS
 # Define what targets to support
 option		TGT_ORIGIN	# IP27/IP35
 option		TGT_COHERENT
+option		CPU_R10000	# R10000/R12000/R14000/R16000 support
 
 # Specify storage configuration using ramdisk
 config		bsd	root on rd0a swap on rd0b
diff --git a/sys/arch/sgi/conf/RAMDISK-IP30 b/sys/arch/sgi/conf/RAMDISK-IP30
index 9dd3ae5e1f6..6015094a608 100644
--- a/sys/arch/sgi/conf/RAMDISK-IP30
+++ b/sys/arch/sgi/conf/RAMDISK-IP30
@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK-IP30,v 1.12 2009/11/07 21:42:07 miod Exp $
+#	$OpenBSD: RAMDISK-IP30,v 1.13 2009/12/12 20:07:10 miod Exp $
 #
 # THIS KERNEL IS FOR Octane and Octane 2 (IP30) SYSTEMS ONLY.
 
@@ -36,6 +36,7 @@ option		RAMDISK_HOOKS
 # Define what targets to support
 option		TGT_OCTANE	# Octane, Octane 2
 option		TGT_COHERENT
+option		CPU_R10000	# R10000/R12000/R14000/R16000 support
 
 # Specify storage configuration using ramdisk
 config		bsd	root on rd0a swap on rd0b
diff --git a/sys/arch/sgi/conf/RAMDISK-IP32 b/sys/arch/sgi/conf/RAMDISK-IP32
index cf7ac79e721..5d19f69a1fc 100644
--- a/sys/arch/sgi/conf/RAMDISK-IP32
+++ b/sys/arch/sgi/conf/RAMDISK-IP32
@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK-IP32,v 1.9 2009/11/07 21:42:07 miod Exp $
+#	$OpenBSD: RAMDISK-IP32,v 1.10 2009/12/12 20:07:10 miod Exp $
 #
 # THIS KERNEL IS FOR O2 (IP32) SYSTEMS ONLY.
 
@@ -35,6 +35,9 @@ option		RAMDISK_HOOKS
 
 # Define what targets to support
 option		TGT_O2		# O2, O2+
+option		CPU_R5000	# R5000/RM5200 support
+option		CPU_RM7000	# RM7000 support
+option		CPU_R10000	# R10000/R12000/R14000/R16000 support
 
 # Specify storage configuration using ramdisk
 config		bsd	root on rd0a swap on rd0b
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index b9f68be9280..185c4d2d9ef 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.93 2009/12/07 19:05:59 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.94 2009/12/12 20:07:10 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -61,7 +61,9 @@
 #include <machine/mnode.h>
 #endif
 
+#ifdef CPU_RM7000
 #include <mips64/rm7000.h>
+#endif
 
 #include <dev/cons.h>
 
@@ -144,10 +146,6 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	extern char start[], edata[], end[];
 	extern char exception[], e_exception[];
 	extern char *hw_vendor;
-	extern void tlb_miss;
-	extern void tlb_miss_err_r5k;
-	extern void xtlb_miss;
-	extern void xtlb_miss_err_r5k;
 
 	/*
 	 * Make sure we can access the extended address space.
@@ -355,6 +353,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		 * Configure TLB.
 		 */
 		switch(sys_config.cpu[0].type) {
+#ifdef CPU_RM7000
 		case MIPS_RM7000:
 			/*
 			 * Rev A (version >= 2) CPU's have 64 TLB entries.
@@ -398,13 +397,14 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 					sys_config.cpu[0].tlbsize = 64;
 			}
 			break;
-
+#endif
+#ifdef CPU_R10000
 		case MIPS_R10000:
 		case MIPS_R12000:
 		case MIPS_R14000:
 			sys_config.cpu[0].tlbsize = 64;
 			break;
-
+#endif
 		default:
 			sys_config.cpu[0].tlbsize = 48;
 			break;
@@ -419,17 +419,25 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	 * Configure cache.
 	 */
 	switch(sys_config.cpu[0].type) {
+#ifdef CPU_R10000
 	case MIPS_R10000:
 	case MIPS_R12000:
 	case MIPS_R14000:
 		cputype = MIPS_R10000;
 		break;
+#endif
+#ifdef CPU_R5000
 	case MIPS_R5000:
-	case MIPS_RM7000:
 	case MIPS_RM52X0:
+		cputype = MIPS_R5000;
+		break;
+#endif
+#ifdef CPU_RM7000
+	case MIPS_RM7000:
 	case MIPS_RM9000:
 		cputype = MIPS_R5000;
 		break;
+#endif
 	default:
 		/*
 		 * If we can't identify the cpu type, it must be
@@ -450,16 +458,8 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		break;
 	}
 	switch (cputype) {
-	case MIPS_R10000:
-		Mips10k_ConfigCache();
-		sys_config._SyncCache = Mips10k_SyncCache;
-		sys_config._InvalidateICache = Mips10k_InvalidateICache;
-		sys_config._SyncDCachePage = Mips10k_SyncDCachePage;
-		sys_config._HitSyncDCache = Mips10k_HitSyncDCache;
-		sys_config._IOSyncDCache = Mips10k_IOSyncDCache;
-		sys_config._HitInvalidateDCache = Mips10k_HitInvalidateDCache;
-		break;
 	default:
+#if defined(CPU_R5000) || defined(CPU_RM7000)
 	case MIPS_R5000:
 		Mips5k_ConfigCache();
 		sys_config._SyncCache = Mips5k_SyncCache;
@@ -469,6 +469,18 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		sys_config._IOSyncDCache = Mips5k_IOSyncDCache;
 		sys_config._HitInvalidateDCache = Mips5k_HitInvalidateDCache;
 		break;
+#endif
+#ifdef CPU_R10000
+	case MIPS_R10000:
+		Mips10k_ConfigCache();
+		sys_config._SyncCache = Mips10k_SyncCache;
+		sys_config._InvalidateICache = Mips10k_InvalidateICache;
+		sys_config._SyncDCachePage = Mips10k_SyncDCachePage;
+		sys_config._HitSyncDCache = Mips10k_HitSyncDCache;
+		sys_config._IOSyncDCache = Mips10k_IOSyncDCache;
+		sys_config._HitInvalidateDCache = Mips10k_HitInvalidateDCache;
+		break;
+#endif
 	}
 
 	/*
@@ -518,7 +530,9 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	 * Build proper TLB refill handler trampolines.
 	 */
 	switch (cputype) {
+#if defined(CPU_R5000) || defined(CPU_RM7000)
 	case MIPS_R5000:
+	    {
 		/*
 		 * R5000 processors need a specific chip bug workaround
 		 * in their tlb handlers.  Theoretically only revision 1
@@ -528,12 +542,20 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		 * This is also necessary on RM52x0 and most RM7k/RM9k,
 		 * and is a documented errata for these chips.
 		 */
+		extern void tlb_miss_err_r5k;
+		extern void xtlb_miss_err_r5k;
 		tlb_handler = (vaddr_t)&tlb_miss_err_r5k;
 		xtlb_handler = (vaddr_t)&xtlb_miss_err_r5k;
+	    }
 		break;
+#endif
 	default:
+	    {
+		extern void tlb_miss;
+		extern void xtlb_miss;
 		tlb_handler = (vaddr_t)&tlb_miss;
 		xtlb_handler = (vaddr_t)&xtlb_miss;
+	    }
 		break;
 	}
 
@@ -807,7 +829,7 @@ setregs(p, pack, stack, retval)
 	p->p_md.md_regs->t9 = pack->ep_entry & ~3; /* abicall req */
 	p->p_md.md_regs->sr = SR_FR_32 | SR_XX | SR_KSU_USER | SR_KX | SR_UX |
 	    SR_EXL | SR_INT_ENAB;
-#if !defined(TGT_COHERENT)
+#if defined(CPU_R10000) && !defined(TGT_COHERENT)
 	if (sys_config.cpu[0].type == MIPS_R12000)
 		p->p_md.md_regs->sr |= SR_DSD;
 #endif
@@ -1001,8 +1023,8 @@ initcpu()
 {
 }
 
+#ifdef CPU_RM7000
 #ifdef	RM7K_PERFCNTR
-
 /*
  * RM7000 Performance counter support.
  */
@@ -1075,6 +1097,7 @@ rm7k_watchintr(trapframe)
 }
 
 #endif	/* RM7K_PERFCNTR */
+#endif	/* CPU_RM7000 */
 
 #ifdef DEBUG
 /*