diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2021-09-02 10:48:53 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2021-09-02 10:48:53 +0000 |
| commit | fcf9d6c6b4c36edccff73c17180c86af6c71c50b (patch) | |
| tree | 118c9e398b89c07b834efeb16cc891f30ee22121 /sys/arch | |
| parent | 3c9a62f7021059b5e1475ec00887a23ab4d432a0 (diff) | |
Fix the TCR_TG0_xxx definitions and add TCR_TG0_4K to the initial setting
of TCR_EL1 in locore to make clear we use 4K pages for both userland and
the kernel.
ok patrick@
Diffstat (limited to 'sys/arch')
| -rw-r--r-- | sys/arch/arm64/arm64/locore.S | 4 | ||||
| -rw-r--r-- | sys/arch/arm64/include/armreg.h | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/sys/arch/arm64/arm64/locore.S b/sys/arch/arm64/arm64/locore.S index 857db50241a..5219af1bec8 100644 --- a/sys/arch/arm64/arm64/locore.S +++ b/sys/arch/arm64/arm64/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.38 2021/06/28 15:45:15 deraadt Exp $ */ +/* $OpenBSD: locore.S,v 1.39 2021/09/02 10:48:52 kettenis Exp $ */ /*- * Copyright (c) 2012-2014 Andrew Turner * All rights reserved. @@ -256,7 +256,7 @@ mair: MAIR_ATTR(0x88, 4) tcr: .quad (TCR_T1SZ(64 - VIRT_BITS) | TCR_T0SZ(64 - 48) | \ - TCR_AS | TCR_TG1_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS) + TCR_AS | TCR_TG1_4K | TCR_TG0_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS) sctlr_set: /* Bits to set */ .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h index fba285f3467..fe96344af2a 100644 --- a/sys/arch/arm64/include/armreg.h +++ b/sys/arch/arm64/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.16 2021/03/27 20:03:15 kettenis Exp $ */ +/* $OpenBSD: armreg.h,v 1.17 2021/09/02 10:48:52 kettenis Exp $ */ /*- * Copyright (c) 2013, 2014 Andrew Turner * Copyright (c) 2015 The FreeBSD Foundation @@ -631,9 +631,9 @@ #define TCR_A1 (1UL << 22) #define TCR_TG0_SHIFT 14 -#define TCR_TG0_16K (1UL << TCR_TG0_SHIFT) -#define TCR_TG0_4K (2UL << TCR_TG0_SHIFT) -#define TCR_TG0_64K (3UL << TCR_TG0_SHIFT) +#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) +#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) +#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) #define TCR_SH0_SHIFT 12 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) |