Implement fractional PLL frequencies for RK3328 and use them for APLL and

GPLL like the Linux kernel does.  Use NPLL for the CPU clock such that
adjusting the CPU frequency doesn't change the clock of other devices
anymore.  Implement the last clocks that are used in the assigned-clocks
property of clock controller.

Don't enable the assigned-clocks processing yet as it results in a sub-optimal
clock for for the SD and eMMC controllers.  This clock handling in dwmcc(4)
needs some further work before we can enable this.

1 files changed, 15 insertions, 0 deletions

diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 699a1df01e3..1b8e6687e3d 100644
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -47,23 +47,38 @@
 #define RK3328_PLL_NPLL			5
 #define RK3328_ARMCLK			6
 
+#define RK3328_CLK_RTC32K		30
 #define RK3328_CLK_SDMMC		33
 #define RK3328_CLK_SDIO			34
 #define RK3328_CLK_EMMC			35
 #define RK3328_CLK_UART0		38
 #define RK3328_CLK_UART1		39
 #define RK3328_CLK_UART2		40
+#define RK3328_CLK_WIFI			53
 #define RK3328_CLK_I2C0			55
 #define RK3328_CLK_I2C1			56
 #define RK3328_CLK_I2C2			57
 #define RK3328_CLK_I2C3			58
 #define RK3328_CLK_PDM			61
+#define RK3328_CLK_VDEC_CABAC		65
+#define RK3328_CLK_VDEC_CORE		66
+#define RK3328_CLK_VENC_DSP		67
+#define RK3328_CLK_VENC_CORE		68
+#define RK3328_CLK_TSP			92
 
+#define RK3328_DCLK_LCDC		120
 #define RK3328_HDMIPHY			122
 #define RK3328_USB480M			123
+#define RK3328_DCLK_LCDC_SRC		124
 
+#define RK3328_ACLK_VOP_PRE		131
+#define RK3328_ACLK_RGA_PRE		133
 #define RK3328_ACLK_BUS_PRE		136
 #define RK3328_ACLK_PERI_PRE		137
+#define RK3328_ACLK_RKVDEC_PRE		138
+#define RK3328_ACLK_RKVENC		140
+#define RK3328_ACLK_VPU_PRE		141
+#define RK3328_ACLK_VIO_PRE		142
 
 #define RK3328_PCLK_BUS_PRE		216
 #define RK3328_PCLK_PERI		230