diff options
| author | SASANO Takayoshi <uaa@cvs.openbsd.org> | 2020-03-23 21:40:02 +0000 |
|---|---|---|
| committer | SASANO Takayoshi <uaa@cvs.openbsd.org> | 2020-03-23 21:40:02 +0000 |
| commit | 0e48d6347d5a3f4e1db0331fa2044d822ee1b8a9 (patch) | |
| tree | 455db72b66f412d371ac729375c7bcc47b41f6ff /sys/dev/fdt | |
| parent | afd205eeb830141a7f637c03ad4d1f067fcc4084 (diff) | |
UART 1-3 support for Allwinner H3 (maybe H5/H2+).
- add reset signal definition
- add reset signal de-assert code
ok kettenis@
Diffstat (limited to 'sys/dev/fdt')
| -rw-r--r-- | sys/dev/fdt/com_fdt.c | 3 | ||||
| -rw-r--r-- | sys/dev/fdt/sxiccmu_clocks.h | 8 |
2 files changed, 10 insertions, 1 deletions
diff --git a/sys/dev/fdt/com_fdt.c b/sys/dev/fdt/com_fdt.c index a025d36f70d..29a6528bd6e 100644 --- a/sys/dev/fdt/com_fdt.c +++ b/sys/dev/fdt/com_fdt.c @@ -1,4 +1,4 @@ -/* $OpenBSD: com_fdt.c,v 1.3 2018/08/06 10:52:30 patrick Exp $ */ +/* $OpenBSD: com_fdt.c,v 1.4 2020/03/23 21:40:01 uaa Exp $ */ /* * Copyright (c) 2016 Patrick Wildt <patrick@blueri.se> * @@ -105,6 +105,7 @@ com_fdt_attach(struct device *parent, struct device *self, void *aux) return; clock_enable(faa->fa_node, NULL); + reset_deassert_all(faa->fa_node); /* * Determine the clock frequency after enabling the clock. diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h index cc545f40b9b..ba443c8185e 100644 --- a/sys/dev/fdt/sxiccmu_clocks.h +++ b/sys/dev/fdt/sxiccmu_clocks.h @@ -746,6 +746,10 @@ struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = { #define H3_RST_BUS_I2C0 46 #define H3_RST_BUS_I2C1 47 #define H3_RST_BUS_I2C2 48 +#define H3_RST_BUS_UART0 49 +#define H3_RST_BUS_UART1 50 +#define H3_RST_BUS_UART2 51 +#define H3_RST_BUS_UART3 52 struct sxiccmu_ccu_bit sun8i_h3_resets[] = { [H3_RST_USB_PHY0] = { 0x00cc, 0 }, @@ -769,6 +773,10 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[] = { [H3_RST_BUS_I2C0] = { 0x02d8, 0 }, [H3_RST_BUS_I2C1] = { 0x02d8, 1 }, [H3_RST_BUS_I2C2] = { 0x02d8, 2 }, + [H3_RST_BUS_UART0] = { 0x02d8, 16 }, + [H3_RST_BUS_UART1] = { 0x02d8, 17 }, + [H3_RST_BUS_UART2] = { 0x02d8, 18 }, + [H3_RST_BUS_UART3] = { 0x02d8, 19 }, }; #define H3_R_RST_APB0_RSB 2 |