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authorPatrick Wildt <patrick@cvs.openbsd.org>2019-01-11 08:00:35 +0000
committerPatrick Wildt <patrick@cvs.openbsd.org>2019-01-11 08:00:35 +0000
commit659fe99e9f9ec2ac49d30d3fee9c247db20de9e7 (patch)
tree7ce0831f32cab7d98309cd96f84660837c3417db /sys/dev/fdt
parent009291d30faeb45cf0142982979eeee0b21bf40e (diff)
Add support for changing the parent of the PCIe clocks. We will
use this for setting the PCIe clocks to the correct frequency. ok kettenis@
Diffstat (limited to 'sys/dev/fdt')
-rw-r--r--sys/dev/fdt/imxccm.c20
-rw-r--r--sys/dev/fdt/imxccm_clocks.h2
2 files changed, 21 insertions, 1 deletions
diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index e1e0ddd42cf..0ec5e31bb2c 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.11 2018/08/20 16:48:03 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.12 2019/01/11 08:00:34 patrick Exp $ */
/*
* Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
*
@@ -1243,6 +1243,24 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
mux |= (0x1 << sc->sc_muxs[idx].shift);
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
return 0;
+ case IMX8MQ_CLK_PCIE1_CTRL_SRC:
+ case IMX8MQ_CLK_PCIE2_CTRL_SRC:
+ if (pidx != IMX8MQ_SYS2_PLL_250M)
+ break;
+ mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+ mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);
+ mux |= (0x1 << sc->sc_muxs[idx].shift);
+ HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
+ return 0;
+ case IMX8MQ_CLK_PCIE1_PHY_SRC:
+ case IMX8MQ_CLK_PCIE2_PHY_SRC:
+ if (pidx != IMX8MQ_SYS2_PLL_100M)
+ break;
+ mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+ mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);
+ mux |= (0x1 << sc->sc_muxs[idx].shift);
+ HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
+ return 0;
}
}
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index 83d5a5056d8..145189e1707 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -297,6 +297,8 @@ struct imxccm_mux imx7d_muxs[] = {
#define IMX8MQ_SYS1_PLL_266M 0x4c
#define IMX8MQ_SYS1_PLL_400M 0x4d
#define IMX8MQ_SYS1_PLL_800M 0x4e
+#define IMX8MQ_SYS2_PLL_100M 0x50
+#define IMX8MQ_SYS2_PLL_250M 0x54
#define IMX8MQ_SYS2_PLL_500M 0x56
#define IMX8MQ_CLK_A53_SRC 0x58
#define IMX8MQ_CLK_A53_CG 0x59