diff options
| author | David Gwynne <dlg@cvs.openbsd.org> | 2023-04-18 05:27:05 +0000 |
|---|---|---|
| committer | David Gwynne <dlg@cvs.openbsd.org> | 2023-04-18 05:27:05 +0000 |
| commit | be628ed0b2eb16e5a58b9fa2480095f0d293ffdf (patch) | |
| tree | cdb717cf05562091e9fddc0c99befa73bafd099f /sys/dev/fdt | |
| parent | 00b00e0b966a36c6c14f4dfd8626cff172b9684a (diff) | |
add the emmc clocks on rk3568 (and rk3566)
Diffstat (limited to 'sys/dev/fdt')
| -rw-r--r-- | sys/dev/fdt/rkclock.c | 26 | ||||
| -rw-r--r-- | sys/dev/fdt/rkclock_clocks.h | 31 |
2 files changed, 44 insertions, 13 deletions
diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c index 8b38ee1e1b5..9f42d4b437b 100644 --- a/sys/dev/fdt/rkclock.c +++ b/sys/dev/fdt/rkclock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: rkclock.c,v 1.73 2023/04/06 21:17:01 kettenis Exp $ */ +/* $OpenBSD: rkclock.c,v 1.74 2023/04/18 05:27:04 dlg Exp $ */ /* * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org> * @@ -3081,6 +3081,22 @@ rk3399_pmu_reset(void *cookie, uint32_t *cells, int on) const struct rkclock rk3568_clocks[] = { { + RK3568_BCLK_EMMC, RK3568_CRU_CLKSEL_CON(28), + SEL(9, 8), 0, + { RK3568_GPLL_200M, RK3568_GPLL_150M, RK3568_CPLL_125M } + }, + { + RK3568_CCLK_EMMC, RK3568_CRU_CLKSEL_CON(28), + SEL(14, 12), 0, + { RK3568_XIN24M, RK3568_GPLL_200M, RK3568_GPLL_150M, + RK3568_CPLL_100M, RK3568_CPLL_50M, RK3568_CLK_OSC0_DIV_375K } + }, + { + RK3568_TCLK_EMMC, 0, 0, 0, + { RK3568_XIN24M } + }, + + { RK3568_ACLK_PHP, RK3568_CRU_CLKSEL_CON(30), SEL(1, 0), 0, { RK3568_GPLL_300M, RK3568_GPLL_200M, @@ -3331,6 +3347,11 @@ const struct rkclock rk3568_clocks[] = { { RK3568_PLL_GPLL } }, { + RK3568_GPLL_150M, RK3568_CRU_CLKSEL_CON(76), + 0, DIV(12, 5), + { RK3568_PLL_GPLL } + }, + { RK3568_GPLL_100M, RK3568_CRU_CLKSEL_CON(77), 0, DIV(4, 0), { RK3568_PLL_GPLL } @@ -3482,6 +3503,9 @@ rk3568_get_frequency(void *cookie, uint32_t *cells) case RK3568_SCLK_GMAC1_DIV_2: idx = RK3568_SCLK_GMAC1; return rk3568_get_frequency(sc, &idx) / 2; + case RK3568_CLK_OSC0_DIV_375K: + idx = RK3568_CLK_OSC0_DIV_750K; + return rk3568_get_frequency(sc, &idx) / 2; case RK3568_GMAC0_CLKIN: return rkclock_external_frequency("gmac0_clkin"); case RK3568_GMAC1_CLKIN: diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h index a0eff75641f..50769f112de 100644 --- a/sys/dev/fdt/rkclock_clocks.h +++ b/sys/dev/fdt/rkclock_clocks.h @@ -283,6 +283,11 @@ #define RK3568_PLL_VPLL 5 #define RK3568_PLL_NPLL 6 +#define RK3568_ACLK_EMMC 121 +#define RK3568_HCLK_EMMC 122 +#define RK3568_BCLK_EMMC 123 +#define RK3568_CCLK_EMMC 124 +#define RK3568_TCLK_EMMC 125 #define RK3568_ACLK_PHP 173 #define RK3568_PCLK_PHP 175 #define RK3568_CLK_SDMMC0 177 @@ -332,18 +337,20 @@ #define RK3568_CPLL_25M 416 #define RK3568_CPLL_100M 417 -#define RK3568_SCLK_GMAC0_DIV_50 1007 -#define RK3568_SCLK_GMAC0_DIV_5 1008 -#define RK3568_SCLK_GMAC0_DIV_20 1009 -#define RK3568_SCLK_GMAC0_DIV_2 1010 -#define RK3568_SCLK_GMAC1_DIV_50 1011 -#define RK3568_SCLK_GMAC1_DIV_5 1012 -#define RK3568_SCLK_GMAC1_DIV_20 1013 -#define RK3568_SCLK_GMAC1_DIV_2 1014 -#define RK3568_GPLL_400M 1015 -#define RK3568_GPLL_300M 1016 -#define RK3568_GPLL_200M 1017 -#define RK3568_GPLL_100M 1018 +#define RK3568_SCLK_GMAC0_DIV_50 1005 +#define RK3568_SCLK_GMAC0_DIV_5 1006 +#define RK3568_SCLK_GMAC0_DIV_20 1007 +#define RK3568_SCLK_GMAC0_DIV_2 1008 +#define RK3568_SCLK_GMAC1_DIV_50 1009 +#define RK3568_SCLK_GMAC1_DIV_5 1010 +#define RK3568_SCLK_GMAC1_DIV_20 1011 +#define RK3568_SCLK_GMAC1_DIV_2 1012 +#define RK3568_GPLL_400M 1013 +#define RK3568_GPLL_300M 1014 +#define RK3568_GPLL_200M 1015 +#define RK3568_GPLL_150M 1016 +#define RK3568_GPLL_100M 1017 +#define RK3568_CLK_OSC0_DIV_375K 1018 #define RK3568_CLK_OSC0_DIV_750K 1019 #define RK3568_GMAC0_CLKIN 1020 #define RK3568_GMAC1_CLKIN 1021 |