bye bye unportable bitfields

1 files changed, 135 insertions, 74 deletions

diff --git a/sys/dev/ic/ar5212.c b/sys/dev/ic/ar5212.c
index ec6e5bae051..796cdb7cf72 100644
--- a/sys/dev/ic/ar5212.c
+++ b/sys/dev/ic/ar5212.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212.c,v 1.12 2005/04/06 09:14:53 reyk Exp $	*/
+/*	$OpenBSD: ar5212.c,v 1.13 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -1276,24 +1276,31 @@ ar5k_ar5212_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	if (tx_tries0 == 0)
 		return (AH_FALSE);
 
-	if ((tx_desc->frame_len = packet_length) != packet_length)
+	if ((tx_desc->tx_control_0 = (packet_length &
+	    AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length)
 		return (AH_FALSE);
 
-	tx_desc->frame_type = type;
-	tx_desc->xmit_power = tx_power;
-	tx_desc->xmit_rate0 = tx_rate0;
-	tx_desc->xmit_tries0 = tx_tries0;
-	tx_desc->ant_mode_xmit = antenna_mode;
-
-#define _TX_FLAGS(_flag, _field) \
-	tx_desc->_field = flags & HAL_TXDESC_##_flag ? 1 : 0
-
-	_TX_FLAGS(CLRDMASK, clear_dest_mask);
-	_TX_FLAGS(VEOL, veol);
-	_TX_FLAGS(INTREQ, inter_req);
-	_TX_FLAGS(NOACK, no_ack);
-	_TX_FLAGS(RTSENA, rts_cts_enable);
-	_TX_FLAGS(CTSENA, cts_enable);
+	tx_desc->tx_control_0 |=
+	    AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) |
+	    AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT);
+	tx_desc->tx_control_1 =
+	    AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE);
+	tx_desc->tx_control_2 =
+	    AR5K_REG_SM(tx_tries0, AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0);
+	tx_desc->tx_control_3 =
+	    tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0;
+
+#define _TX_FLAGS(_c, _flag)	 					\
+	if (flags & HAL_TXDESC_##_flag)					\
+		tx_desc->tx_control_##_c |=    				\
+			AR5K_AR5212_DESC_TX_CTL##_c##_##_flag
+
+	_TX_FLAGS(0, CLRDMASK);
+	_TX_FLAGS(0, VEOL);
+	_TX_FLAGS(0, INTREQ);
+	_TX_FLAGS(0, RTSENA);
+	_TX_FLAGS(0, CTSENA);
+	_TX_FLAGS(1, NOACK);
 
 #undef _TX_FLAGS
 
@@ -1301,8 +1308,11 @@ ar5k_ar5212_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	 * WEP crap
 	 */
 	if (key_index != HAL_TXKEYIX_INVALID) {
-		tx_desc->encrypt_key_valid = 1;
-		tx_desc->encrypt_key_index = key_index;
+		tx_desc->tx_control_0 |=
+		    AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID;
+		tx_desc->tx_control_1 |=
+		    AR5K_REG_SM(key_index,
+		    AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX);
 	}
 
 	/*
@@ -1312,8 +1322,11 @@ ar5k_ar5212_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 		if ((flags & HAL_TXDESC_RTSENA) &&
 		    (flags & HAL_TXDESC_CTSENA))
 			return (AH_FALSE);
-		tx_desc->rts_cts_rate = rtscts_rate;
-		tx_desc->rts_duration = rtscts_duration;
+		tx_desc->tx_control_2 |=
+		    rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION;
+		tx_desc->tx_control_3 |=
+		    AR5K_REG_SM(rtscts_rate,
+		    AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE);
 	}
 
 	return (AH_TRUE);
@@ -1335,13 +1348,15 @@ ar5k_ar5212_fillTxDesc(hal, desc, segment_length, first_segment, last_segment)
 	bzero(desc->ds_hw, sizeof(desc->ds_hw));
 
 	/* Validate segment length and initialize the descriptor */
-	if ((tx_desc->buf_len = segment_length) != segment_length)
+	if ((tx_desc->tx_control_1 = (segment_length &
+	    AR5K_AR5212_DESC_TX_CTL1_BUF_LEN)) != segment_length)
 		return (AH_FALSE);
 
 	if (first_segment != AH_TRUE)
-		tx_desc->frame_len = 0;
+		tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN;
 
-	tx_desc->more = last_segment == AH_TRUE ? 0 : 1;
+	if (last_segment != AH_TRUE)
+		tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE;
 
 	return (AH_TRUE);
 }
@@ -1364,8 +1379,12 @@ ar5k_ar5212_setupXTxDesc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
 
 #define _XTX_TRIES(_n)							\
 	if (tx_tries##_n) {						\
-		tx_desc->xmit_tries##_n = tx_tries##_n;			\
-		tx_desc->xmit_rate##_n = tx_rate##_n;			\
+		tx_desc->tx_control_2 |=				\
+		    AR5K_REG_SM(tx_tries##_n,				\
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n);		\
+		tx_desc->tx_control_3 |=				\
+		    AR5K_REG_SM(tx_rate##_n,				\
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n);		\
 	}
 
 	_XTX_TRIES(1);
@@ -1389,46 +1408,75 @@ ar5k_ar5212_procTxDesc(hal, desc)
 	tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
 
 	/* No frame has been send or error */
-	if (tx_status->done == 0)
+	if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Get descriptor status
 	 */
-	desc->ds_us.tx.ts_seqnum = tx_status->seq_num;
-	desc->ds_us.tx.ts_tstamp = tx_status->send_timestamp;
-	desc->ds_us.tx.ts_shortretry = tx_status->rts_fail_count;
-	desc->ds_us.tx.ts_longretry = tx_status->data_fail_count;
-	desc->ds_us.tx.ts_rssi = tx_status->ack_sig_strength;
-	desc->ds_us.tx.ts_antenna = tx_status->xmit_antenna ? 2 : 1;
+	desc->ds_us.tx.ts_tstamp =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP);
+	desc->ds_us.tx.ts_shortretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT);
+	desc->ds_us.tx.ts_longretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT);
+	desc->ds_us.tx.ts_seqnum =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM);
+	desc->ds_us.tx.ts_rssi =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+	desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
+	    AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
 	desc->ds_us.tx.ts_status = 0;
 
-	switch (tx_status->final_ts_index) {
+	switch (AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
 	case 0:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate0;
+		desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0;
 		break;
 	case 1:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate1;
-		desc->ds_us.tx.ts_longretry += tx_desc->xmit_tries0;
+		desc->ds_us.tx.ts_rate =
+		    AR5K_REG_MS(tx_desc->tx_control_3,
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1);
+		desc->ds_us.tx.ts_longretry +=
+		    AR5K_REG_MS(tx_desc->tx_control_2,
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1);
 		break;
 	case 2:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate2;
-		desc->ds_us.tx.ts_longretry += tx_desc->xmit_tries1;
+		desc->ds_us.tx.ts_rate =
+		    AR5K_REG_MS(tx_desc->tx_control_3,
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2);
+		desc->ds_us.tx.ts_longretry +=
+		    AR5K_REG_MS(tx_desc->tx_control_2,
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2);
 		break;
 	case 3:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate3;
-		desc->ds_us.tx.ts_longretry += tx_desc->xmit_tries2;
+		desc->ds_us.tx.ts_rate =
+		    AR5K_REG_MS(tx_desc->tx_control_3,
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3);
+		desc->ds_us.tx.ts_longretry +=
+		    AR5K_REG_MS(tx_desc->tx_control_2,
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3);
 		break;
 	}
 
-	if (tx_status->frame_xmit_ok == 0) {
-		if (tx_status->excessive_retries)
+	if ((tx_status->tx_status_0 &
+	    AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
 
-		if (tx_status->fifo_underrun)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;
 
-		if (tx_status->filtered)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5212_DESC_TX_STATUS0_FILTERED)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;
 	}
 
@@ -1601,18 +1649,14 @@ ar5k_ar5212_setupRxDesc(hal, desc, size, flags)
 {
 	struct ar5k_ar5212_rx_desc *rx_desc;
 
-	/* Reset descriptor */
-	desc->ds_ctl0 = 0;
-	desc->ds_ctl1 = 0;
-	bzero(&desc->ds_hw[0], sizeof(struct ar5k_ar5212_rx_status));
-
 	rx_desc = (struct ar5k_ar5212_rx_desc*)&desc->ds_ctl0;
 
-	if ((rx_desc->buf_len = size) != size)
+	if ((rx_desc->rx_control_1 = (size &
+	    AR5K_AR5212_DESC_RX_CTL1_BUF_LEN)) != size)
 		return (AH_FALSE);
 
 	if (flags & HAL_RXDESC_INTREQ)
-		rx_desc->inter_req = 1;
+		rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ;
 
 	return (AH_TRUE);
 }
@@ -1624,56 +1668,73 @@ ar5k_ar5212_procRxDesc(hal, desc, phys_addr, next)
 	u_int32_t phys_addr;
 	struct ath_desc *next;
 {
-	u_int32_t now, tstamp;
 	struct ar5k_ar5212_rx_status *rx_status;
+	struct ar5k_ar5212_rx_error *rx_err;
 
 	rx_status = (struct ar5k_ar5212_rx_status*)&desc->ds_hw[0];
 
+	/* Overlay on error */
+	rx_err = (struct ar5k_ar5212_rx_error*)&desc->ds_hw[0];
+
 	/* No frame received / not ready */
-	if (!rx_status->done)
+	if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Frame receive status
 	 */
-	now = (AR5K_REG_READ(AR5K_AR5212_TSF_L32) >> 10) & 0xffff;
-	tstamp = ((now & 0x1fff) < rx_status->receive_timestamp) ?
-	    (((now - 0x2000) & 0xffff) |
-	    (u_int32_t)rx_status->receive_timestamp) :
-	    (now | (u_int32_t)rx_status->receive_timestamp);
-	desc->ds_us.rx.rs_tstamp = rx_status->receive_timestamp & 0x7fff;
-	desc->ds_us.rx.rs_datalen = rx_status->data_len;
-	desc->ds_us.rx.rs_rssi = rx_status->receive_sig_strength;
-	desc->ds_us.rx.rs_rate = rx_status->receive_rate;
-	desc->ds_us.rx.rs_antenna = rx_status->receive_antenna ? 1 : 0;
-	desc->ds_us.rx.rs_more = rx_status->more ? 1 : 0;
+	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
+	    AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
+	    AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA;
+	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
+	    AR5K_AR5212_DESC_RX_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp =
+	    AR5K_REG_MS(rx_status->rx_status_1,
+	    AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
 	 * Key table status
 	 */
-	if (!rx_status->key_index_valid) {
-		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
+	if (rx_status->rx_status_1 &
+	    AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) {
+		desc->ds_us.rx.rs_keyix =
+		    AR5K_REG_MS(rx_status->rx_status_1,
+		    AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX);
 	} else {
-		desc->ds_us.rx.rs_keyix = rx_status->key_index;
+		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
 	}
 
 	/*
 	 * Receive/descriptor errors
 	 */
-	if (!rx_status->frame_receive_ok) {
-		if (rx_status->crc_error)
+	if ((rx_status->rx_status_1 &
+	    AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_CRC;
 
-		if (rx_status->phy_error) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) {
 			desc->ds_us.rx.rs_status |= HAL_RXERR_PHY;
-			desc->ds_us.rx.rs_phyerr = rx_status->phy_error;
+			desc->ds_us.rx.rs_phyerr =
+			    AR5K_REG_MS(rx_err->rx_error_1,
+			    AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE);
 		}
 
-		if (rx_status->decrypt_crc_error)
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT;
 
-		if (rx_status->mic_error)
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_MIC;
 	}