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authorJonathan Gray <jsg@cvs.openbsd.org>2005-09-10 14:36:47 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2005-09-10 14:36:47 +0000
commit28e89a88f52d685d411a4a0dc4814cd09902b871 (patch)
treeb9747ad2c730eea3b49fd7f521097209436bb56a /sys/dev/ic
parentc64761659a10c1ab82ed76332c34c6c8a1cc0849 (diff)
ansi, no binary change.
ok reyk@
Diffstat (limited to 'sys/dev/ic')
-rw-r--r--sys/dev/ic/ar5210.c418
-rw-r--r--sys/dev/ic/ar5211.c413
-rw-r--r--sys/dev/ic/ar5212.c412
-rw-r--r--sys/dev/ic/ar5xxx.c178
4 files changed, 390 insertions, 1031 deletions
diff --git a/sys/dev/ic/ar5210.c b/sys/dev/ic/ar5210.c
index 861ba1e59e6..bdb057b56b8 100644
--- a/sys/dev/ic/ar5210.c
+++ b/sys/dev/ic/ar5210.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar5210.c,v 1.28 2005/08/14 11:02:32 miod Exp $ */
+/* $OpenBSD: ar5210.c,v 1.29 2005/09/10 14:36:46 jsg Exp $ */
/*
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -41,8 +41,7 @@ static const struct ar5k_ini ar5210_ini[] =
AR5K_HAL_FUNCTIONS(extern, ar5k_ar5210,);
const void
-ar5k_ar5210_fill(hal)
- struct ath_hal *hal;
+ar5k_ar5210_fill(struct ath_hal *hal)
{
hal->ah_magic = AR5K_AR5210_MAGIC;
@@ -175,12 +174,8 @@ ar5k_ar5210_fill(hal)
}
struct ath_hal *
-ar5k_ar5210_attach(device, sc, st, sh, status)
- u_int16_t device;
- void *sc;
- bus_space_tag_t st;
- bus_space_handle_t sh;
- int *status;
+ar5k_ar5210_attach(u_int16_t device, void *sc, bus_space_tag_t st,
+ bus_space_handle_t sh, int *status)
{
int i;
struct ath_hal *hal = (struct ath_hal*) sc;
@@ -223,9 +218,7 @@ ar5k_ar5210_attach(device, sc, st, sh, status)
}
HAL_BOOL
-ar5k_ar5210_nic_reset(hal, val)
- struct ath_hal *hal;
- u_int32_t val;
+ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val)
{
HAL_BOOL ret = AH_FALSE;
u_int32_t mask = val ? val : ~0;
@@ -259,10 +252,7 @@ ar5k_ar5210_nic_reset(hal, val)
}
HAL_BOOL
-ar5k_ar5210_nic_wakeup(hal, turbo, initial)
- struct ath_hal *hal;
- HAL_BOOL turbo;
- HAL_BOOL initial;
+ar5k_ar5210_nic_wakeup(struct ath_hal *hal, HAL_BOOL turbo, HAL_BOOL initial)
{
/*
* Reset and wakeup the device
@@ -324,9 +314,7 @@ ar5k_ar5210_nic_wakeup(hal, turbo, initial)
}
const HAL_RATE_TABLE *
-ar5k_ar5210_get_rate_table(hal, mode)
- struct ath_hal *hal;
- u_int mode;
+ar5k_ar5210_get_rate_table(struct ath_hal *hal, u_int mode)
{
switch (mode) {
case HAL_MODE_11A:
@@ -343,8 +331,7 @@ ar5k_ar5210_get_rate_table(hal, mode)
}
void
-ar5k_ar5210_detach(hal)
- struct ath_hal *hal;
+ar5k_ar5210_detach(struct ath_hal *hal)
{
/*
* Free HAL structure, assume interrupts are down
@@ -353,12 +340,8 @@ ar5k_ar5210_detach(hal)
}
HAL_BOOL
-ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
- struct ath_hal *hal;
- HAL_OPMODE op_mode;
- HAL_CHANNEL *channel;
- HAL_BOOL change_channel;
- HAL_STATUS *status;
+ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
+ HAL_BOOL change_channel, HAL_STATUS *status)
{
int i;
@@ -450,8 +433,7 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
}
void
-ar5k_ar5210_set_opmode(hal)
- struct ath_hal *hal;
+ar5k_ar5210_set_opmode(struct ath_hal *hal)
{
u_int32_t pcu_reg, beacon_reg, low_id, high_id;
@@ -500,9 +482,7 @@ ar5k_ar5210_set_opmode(hal)
}
HAL_BOOL
-ar5k_ar5210_calibrate(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5210_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
{
HAL_BOOL ret = AH_TRUE;
u_int32_t phy_sig, phy_agc, phy_sat, beacon;
@@ -606,9 +586,7 @@ ar5k_ar5210_calibrate(hal, channel)
}
HAL_BOOL
-ar5k_ar5210_do_calibrate(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5210_do_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
{
/*
* Enable calibration and wait until completion
@@ -627,9 +605,7 @@ ar5k_ar5210_do_calibrate(hal, channel)
}
HAL_BOOL
-ar5k_ar5210_noise_floor(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5210_noise_floor(struct ath_hal *hal, HAL_CHANNEL *channel)
{
int i;
u_int32_t noise_floor;
@@ -672,9 +648,7 @@ ar5k_ar5210_noise_floor(hal, channel)
*/
HAL_BOOL
-ar5k_ar5210_update_tx_triglevel(hal, increase)
- struct ath_hal *hal;
- HAL_BOOL increase;
+ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
{
u_int32_t trigger_level;
HAL_BOOL status = AH_FALSE;
@@ -710,10 +684,8 @@ ar5k_ar5210_update_tx_triglevel(hal, increase)
}
int
-ar5k_ar5210_setup_tx_queue(hal, queue_type, queue_info)
- struct ath_hal *hal;
- HAL_TX_QUEUE queue_type;
- const HAL_TXQ_INFO *queue_info;
+ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
+ const HAL_TXQ_INFO *queue_info)
{
u_int queue;
@@ -748,10 +720,8 @@ ar5k_ar5210_setup_tx_queue(hal, queue_type, queue_info)
}
HAL_BOOL
-ar5k_ar5210_setup_tx_queueprops(hal, queue, queue_info)
- struct ath_hal *hal;
- int queue;
- const HAL_TXQ_INFO *queue_info;
+ar5k_ar5210_setup_tx_queueprops(struct ath_hal *hal, int queue,
+ const HAL_TXQ_INFO *queue_info)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -767,9 +737,7 @@ ar5k_ar5210_setup_tx_queueprops(hal, queue, queue_info)
}
HAL_BOOL
-ar5k_ar5210_release_tx_queue(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5210_release_tx_queue(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -780,10 +748,7 @@ ar5k_ar5210_release_tx_queue(hal, queue)
}
void
-ar5k_ar5210_init_tx_queue(hal, aifs, turbo)
- struct ath_hal *hal;
- u_int aifs;
- HAL_BOOL turbo;
+ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, HAL_BOOL turbo)
{
int i;
struct {
@@ -801,9 +766,7 @@ ar5k_ar5210_init_tx_queue(hal, aifs, turbo)
}
HAL_BOOL
-ar5k_ar5210_reset_tx_queue(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5210_reset_tx_queue(struct ath_hal *hal, u_int queue)
{
u_int32_t cw_min, retry_lg, retry_sh;
HAL_TXQ_INFO *tq;
@@ -857,9 +820,7 @@ ar5k_ar5210_reset_tx_queue(hal, queue)
}
u_int32_t
-ar5k_ar5210_get_tx_buf(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5210_get_tx_buf(struct ath_hal *hal, u_int queue)
{
u_int16_t tx_reg;
@@ -884,10 +845,7 @@ ar5k_ar5210_get_tx_buf(hal, queue)
}
HAL_BOOL
-ar5k_ar5210_put_tx_buf(hal, queue, phys_addr)
- struct ath_hal *hal;
- u_int queue;
- u_int32_t phys_addr;
+ar5k_ar5210_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
{
u_int16_t tx_reg;
@@ -915,9 +873,7 @@ ar5k_ar5210_put_tx_buf(hal, queue, phys_addr)
}
HAL_BOOL
-ar5k_ar5210_tx_start(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5210_tx_start(struct ath_hal *hal, u_int queue)
{
u_int32_t tx_queue;
@@ -957,9 +913,7 @@ ar5k_ar5210_tx_start(hal, queue)
}
HAL_BOOL
-ar5k_ar5210_stop_tx_dma(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5210_stop_tx_dma(struct ath_hal *hal, u_int queue)
{
u_int32_t tx_queue;
@@ -993,22 +947,10 @@ ar5k_ar5210_stop_tx_dma(hal, queue)
}
HAL_BOOL
-ar5k_ar5210_setup_tx_desc(hal, desc, packet_length, header_length, type,
- tx_power, tx_rate0, tx_tries0, key_index, antenna_mode, flags, rtscts_rate,
- rtscts_duration)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int packet_length;
- u_int header_length;
- HAL_PKT_TYPE type;
- u_int tx_power;
- u_int tx_rate0;
- u_int tx_tries0;
- u_int key_index;
- u_int antenna_mode;
- u_int flags;
- u_int rtscts_rate;
- u_int rtscts_duration;
+ar5k_ar5210_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
+ u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
+ u_int flags, u_int rtscts_rate, u_int rtscts_duration)
{
u_int32_t frame_type;
struct ar5k_ar5210_tx_desc *tx_desc;
@@ -1075,12 +1017,8 @@ ar5k_ar5210_setup_tx_desc(hal, desc, packet_length, header_length, type,
}
HAL_BOOL
-ar5k_ar5210_fill_tx_desc(hal, desc, segment_length, first_segment, last_segment)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int segment_length;
- HAL_BOOL first_segment;
- HAL_BOOL last_segment;
+ar5k_ar5210_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment)
{
struct ar5k_ar5210_tx_desc *tx_desc;
@@ -1104,16 +1042,9 @@ ar5k_ar5210_fill_tx_desc(hal, desc, segment_length, first_segment, last_segment)
}
HAL_BOOL
-ar5k_ar5210_setup_xtx_desc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
- tx_rate3, tx_tries3)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int tx_rate1;
- u_int tx_tries1;
- u_int tx_rate2;
- u_int tx_tries2;
- u_int tx_rate3;
- u_int tx_tries3;
+ar5k_ar5210_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
+ u_int tx_rate3, u_int tx_tries3)
{
/*
* Does this function is for setting up XR? Not sure...
@@ -1124,9 +1055,7 @@ ar5k_ar5210_setup_xtx_desc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
}
HAL_STATUS
-ar5k_ar5210_proc_tx_desc(hal, desc)
- struct ath_hal *hal;
- struct ath_desc *desc;
+ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
{
struct ar5k_ar5210_tx_status *tx_status;
struct ar5k_ar5210_tx_desc *tx_desc;
@@ -1181,8 +1110,7 @@ ar5k_ar5210_proc_tx_desc(hal, desc)
}
HAL_BOOL
-ar5k_ar5210_has_veol(hal)
- struct ath_hal *hal;
+ar5k_ar5210_has_veol(struct ath_hal *hal)
{
return (AH_FALSE);
}
@@ -1192,30 +1120,25 @@ ar5k_ar5210_has_veol(hal)
*/
u_int32_t
-ar5k_ar5210_get_rx_buf(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_rx_buf(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5210_RXDP));
}
void
-ar5k_ar5210_put_rx_buf(hal, phys_addr)
- struct ath_hal *hal;
- u_int32_t phys_addr;
+ar5k_ar5210_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
{
AR5K_REG_WRITE(AR5K_AR5210_RXDP, phys_addr);
}
void
-ar5k_ar5210_start_rx(hal)
- struct ath_hal *hal;
+ar5k_ar5210_start_rx(struct ath_hal *hal)
{
AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXE);
}
HAL_BOOL
-ar5k_ar5210_stop_rx_dma(hal)
- struct ath_hal *hal;
+ar5k_ar5210_stop_rx_dma(struct ath_hal *hal)
{
int i;
@@ -1233,24 +1156,20 @@ ar5k_ar5210_stop_rx_dma(hal)
}
void
-ar5k_ar5210_start_rx_pcu(hal)
- struct ath_hal *hal;
+ar5k_ar5210_start_rx_pcu(struct ath_hal *hal)
{
AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX);
}
void
-ar5k_ar5210_stop_pcu_recv(hal)
- struct ath_hal *hal;
+ar5k_ar5210_stop_pcu_recv(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX);
}
void
-ar5k_ar5210_set_mcast_filter(hal, filter0, filter1)
- struct ath_hal *hal;
- u_int32_t filter0;
- u_int32_t filter1;
+ar5k_ar5210_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
+ u_int32_t filter1)
{
/* Set the multicat filter */
AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL0, filter0);
@@ -1258,9 +1177,7 @@ ar5k_ar5210_set_mcast_filter(hal, filter0, filter1)
}
HAL_BOOL
-ar5k_ar5210_set_mcast_filterindex(hal, index)
- struct ath_hal *hal;
- u_int32_t index;
+ar5k_ar5210_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
{
if (index >= 64) {
return (AH_FALSE);
@@ -1276,9 +1193,7 @@ ar5k_ar5210_set_mcast_filterindex(hal, index)
}
HAL_BOOL
-ar5k_ar5210_clear_mcast_filter_idx(hal, index)
- struct ath_hal *hal;
- u_int32_t index;
+ar5k_ar5210_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
{
if (index >= 64) {
return (AH_FALSE);
@@ -1294,16 +1209,13 @@ ar5k_ar5210_clear_mcast_filter_idx(hal, index)
}
u_int32_t
-ar5k_ar5210_get_rx_filter(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_rx_filter(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER));
}
void
-ar5k_ar5210_set_rx_filter(hal, filter)
- struct ath_hal *hal;
- u_int32_t filter;
+ar5k_ar5210_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
{
/*
* The AR5210 uses promiscous mode to detect radar activity
@@ -1317,11 +1229,8 @@ ar5k_ar5210_set_rx_filter(hal, filter)
}
HAL_BOOL
-ar5k_ar5210_setup_rx_desc(hal, desc, size, flags)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int32_t size;
- u_int flags;
+ar5k_ar5210_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int32_t size, u_int flags)
{
struct ar5k_ar5210_rx_desc *rx_desc;
@@ -1338,11 +1247,8 @@ ar5k_ar5210_setup_rx_desc(hal, desc, size, flags)
}
HAL_STATUS
-ar5k_ar5210_proc_rx_desc(hal, desc, phys_addr, next)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int32_t phys_addr;
- struct ath_desc *next;
+ar5k_ar5210_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int32_t phys_addr, struct ath_desc *next)
{
struct ar5k_ar5210_rx_status *rx_status;
@@ -1414,8 +1320,7 @@ ar5k_ar5210_proc_rx_desc(hal, desc, phys_addr, next)
}
void
-ar5k_ar5210_set_rx_signal(hal)
- struct ath_hal *hal;
+ar5k_ar5210_set_rx_signal(struct ath_hal *hal)
{
/* Signal state monitoring is not yet supported */
}
@@ -1425,8 +1330,7 @@ ar5k_ar5210_set_rx_signal(hal)
*/
void
-ar5k_ar5210_dump_state(hal)
- struct ath_hal *hal;
+ar5k_ar5210_dump_state(struct ath_hal *hal)
{
#ifdef AR5K_DEBUG
#define AR5K_PRINT_REGISTER(_x) \
@@ -1516,12 +1420,8 @@ ar5k_ar5210_dump_state(hal)
}
HAL_BOOL
-ar5k_ar5210_get_diag_state(hal, id, device, size)
- struct ath_hal *hal;
- int id;
- void **device;
- u_int *size;
-
+ar5k_ar5210_get_diag_state(struct ath_hal *hal, int id, void **device,
+ u_int *size)
{
/*
* We'll ignore this right now. This seems to be some kind of an obscure
@@ -1531,17 +1431,13 @@ ar5k_ar5210_get_diag_state(hal, id, device, size)
}
void
-ar5k_ar5210_get_lladdr(hal, mac)
- struct ath_hal *hal;
- u_int8_t *mac;
+ar5k_ar5210_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
{
bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
}
HAL_BOOL
-ar5k_ar5210_set_lladdr(hal, mac)
- struct ath_hal *hal;
- const u_int8_t *mac;
+ar5k_ar5210_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
{
u_int32_t low_id, high_id;
@@ -1559,11 +1455,8 @@ ar5k_ar5210_set_lladdr(hal, mac)
}
HAL_BOOL
-ar5k_ar5210_set_regdomain(hal, regdomain, status)
- struct ath_hal *hal;
- u_int16_t regdomain;
- HAL_STATUS *status;
-
+ar5k_ar5210_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
+ HAL_STATUS *status)
{
ieee80211_regdomain_t ieee_regdomain;
@@ -1581,9 +1474,7 @@ ar5k_ar5210_set_regdomain(hal, regdomain, status)
}
void
-ar5k_ar5210_set_ledstate(hal, state)
- struct ath_hal *hal;
- HAL_LED_STATE state;
+ar5k_ar5210_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
{
u_int32_t led;
@@ -1614,11 +1505,8 @@ ar5k_ar5210_set_ledstate(hal, state)
}
void
-ar5k_ar5210_set_associd(hal, bssid, assoc_id, tim_offset)
- struct ath_hal *hal;
- const u_int8_t *bssid;
- u_int16_t assoc_id;
- u_int16_t tim_offset;
+ar5k_ar5210_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
+ u_int16_t assoc_id, u_int16_t tim_offset)
{
u_int32_t low_id, high_id;
@@ -1644,9 +1532,7 @@ ar5k_ar5210_set_associd(hal, bssid, assoc_id, tim_offset)
}
HAL_BOOL
-ar5k_ar5210_set_gpio_output(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5210_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5210_NUM_GPIO)
return (AH_FALSE);
@@ -1659,9 +1545,7 @@ ar5k_ar5210_set_gpio_output(hal, gpio)
}
HAL_BOOL
-ar5k_ar5210_set_gpio_input(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5210_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5210_NUM_GPIO)
return (AH_FALSE);
@@ -1674,9 +1558,7 @@ ar5k_ar5210_set_gpio_input(hal, gpio)
}
u_int32_t
-ar5k_ar5210_get_gpio(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5210_get_gpio(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5210_NUM_GPIO)
return (0xffffffff);
@@ -1687,10 +1569,7 @@ ar5k_ar5210_get_gpio(hal, gpio)
}
HAL_BOOL
-ar5k_ar5210_set_gpio(hal, gpio, val)
- struct ath_hal *hal;
- u_int32_t gpio;
- u_int32_t val;
+ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
{
u_int32_t data;
@@ -1709,10 +1588,8 @@ ar5k_ar5210_set_gpio(hal, gpio, val)
}
void
-ar5k_ar5210_set_gpio_intr(hal, gpio, interrupt_level)
- struct ath_hal *hal;
- u_int gpio;
- u_int32_t interrupt_level;
+ar5k_ar5210_set_gpio_intr(struct ath_hal *hal, u_int gpio,
+ u_int32_t interrupt_level)
{
u_int32_t data;
@@ -1737,38 +1614,33 @@ ar5k_ar5210_set_gpio_intr(hal, gpio, interrupt_level)
}
u_int32_t
-ar5k_ar5210_get_tsf32(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_tsf32(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5210_TSF_L32));
}
u_int64_t
-ar5k_ar5210_get_tsf64(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_tsf64(struct ath_hal *hal)
{
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32);
return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32));
}
void
-ar5k_ar5210_reset_tsf(hal)
- struct ath_hal *hal;
+ar5k_ar5210_reset_tsf(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON,
AR5K_AR5210_BEACON_RESET_TSF);
}
u_int16_t
-ar5k_ar5210_get_regdomain(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_regdomain(struct ath_hal *hal)
{
return (ar5k_get_regdomain(hal));
}
HAL_BOOL
-ar5k_ar5210_detect_card_present(hal)
- struct ath_hal *hal;
+ar5k_ar5210_detect_card_present(struct ath_hal *hal)
{
u_int16_t magic;
@@ -1784,9 +1656,7 @@ ar5k_ar5210_detect_card_present(hal)
}
void
-ar5k_ar5210_update_mib_counters(hal, statistics)
- struct ath_hal *hal;
- HAL_MIB_STATS *statistics;
+ar5k_ar5210_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
{
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL);
statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL);
@@ -1796,17 +1666,13 @@ ar5k_ar5210_update_mib_counters(hal, statistics)
}
HAL_RFGAIN
-ar5k_ar5210_get_rf_gain(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_rf_gain(struct ath_hal *hal)
{
return (HAL_RFGAIN_INACTIVE);
}
HAL_BOOL
-ar5k_ar5210_set_slot_time(hal, slot_time)
- struct ath_hal *hal;
- u_int slot_time;
-
+ar5k_ar5210_set_slot_time(struct ath_hal *hal, u_int slot_time)
{
if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
return (AH_FALSE);
@@ -1818,17 +1684,14 @@ ar5k_ar5210_set_slot_time(hal, slot_time)
}
u_int
-ar5k_ar5210_get_slot_time(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_slot_time(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) &
0xffff, hal->ah_turbo));
}
HAL_BOOL
-ar5k_ar5210_set_ack_timeout(hal, timeout)
- struct ath_hal *hal;
- u_int timeout;
+ar5k_ar5210_set_ack_timeout(struct ath_hal *hal, u_int timeout)
{
if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK),
hal->ah_turbo) <= timeout)
@@ -1841,17 +1704,14 @@ ar5k_ar5210_set_ack_timeout(hal, timeout)
}
u_int
-ar5k_ar5210_get_ack_timeout(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_ack_timeout(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo));
}
HAL_BOOL
-ar5k_ar5210_set_cts_timeout(hal, timeout)
- struct ath_hal *hal;
- u_int timeout;
+ar5k_ar5210_set_cts_timeout(struct ath_hal *hal, u_int timeout)
{
if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS),
hal->ah_turbo) <= timeout)
@@ -1864,8 +1724,7 @@ ar5k_ar5210_set_cts_timeout(hal, timeout)
}
u_int
-ar5k_ar5210_get_cts_timeout(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_cts_timeout(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo));
@@ -1876,9 +1735,7 @@ ar5k_ar5210_get_cts_timeout(hal)
*/
HAL_BOOL
-ar5k_ar5210_is_cipher_supported(hal, cipher)
- struct ath_hal *hal;
- HAL_CIPHER cipher;
+ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
{
/*
* The AR5210 only supports WEP
@@ -1890,16 +1747,13 @@ ar5k_ar5210_is_cipher_supported(hal, cipher)
}
u_int32_t
-ar5k_ar5210_get_keycache_size(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_keycache_size(struct ath_hal *hal)
{
return (AR5K_AR5210_KEYCACHE_SIZE);
}
HAL_BOOL
-ar5k_ar5210_reset_key(hal, entry)
- struct ath_hal *hal;
- u_int16_t entry;
+ar5k_ar5210_reset_key(struct ath_hal *hal, u_int16_t entry)
{
int i;
@@ -1912,9 +1766,7 @@ ar5k_ar5210_reset_key(hal, entry)
}
HAL_BOOL
-ar5k_ar5210_is_key_valid(hal, entry)
- struct ath_hal *hal;
- u_int16_t entry;
+ar5k_ar5210_is_key_valid(struct ath_hal *hal, u_int16_t entry)
{
AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE);
@@ -1929,12 +1781,8 @@ ar5k_ar5210_is_key_valid(hal, entry)
}
HAL_BOOL
-ar5k_ar5210_set_key(hal, entry, keyval, mac, xor_notused)
- struct ath_hal *hal;
- u_int16_t entry;
- const HAL_KEYVAL *keyval;
- const u_int8_t *mac;
- int xor_notused;
+ar5k_ar5210_set_key(struct ath_hal *hal, u_int16_t entry,
+ const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused)
{
int i;
u_int32_t key_v[AR5K_AR5210_KEYCACHE_SIZE - 2];
@@ -1980,10 +1828,8 @@ ar5k_ar5210_set_key(hal, entry, keyval, mac, xor_notused)
}
HAL_BOOL
-ar5k_ar5210_set_key_lladdr(hal, entry, mac)
- struct ath_hal *hal;
- u_int16_t entry;
- const u_int8_t *mac;
+ar5k_ar5210_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
+ const u_int8_t *mac)
{
u_int32_t low_id, high_id;
const u_int8_t *mac_v;
@@ -2011,11 +1857,8 @@ ar5k_ar5210_set_key_lladdr(hal, entry, mac)
*/
HAL_BOOL
-ar5k_ar5210_set_power(hal, mode, set_chip, sleep_duration)
- struct ath_hal *hal;
- HAL_POWER_MODE mode;
- HAL_BOOL set_chip;
- u_int16_t sleep_duration;
+ar5k_ar5210_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
+ HAL_BOOL set_chip, u_int16_t sleep_duration)
{
u_int32_t staid;
int i;
@@ -2080,23 +1923,20 @@ ar5k_ar5210_set_power(hal, mode, set_chip, sleep_duration)
}
HAL_POWER_MODE
-ar5k_ar5210_get_power_mode(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_power_mode(struct ath_hal *hal)
{
return (hal->ah_power_mode);
}
HAL_BOOL
-ar5k_ar5210_query_pspoll_support(hal)
- struct ath_hal *hal;
+ar5k_ar5210_query_pspoll_support(struct ath_hal *hal)
{
/* I think so, why not? */
return (AH_TRUE);
}
HAL_BOOL
-ar5k_ar5210_init_pspoll(hal)
- struct ath_hal *hal;
+ar5k_ar5210_init_pspoll(struct ath_hal *hal)
{
/*
* Not used on the AR5210
@@ -2105,10 +1945,8 @@ ar5k_ar5210_init_pspoll(hal)
}
HAL_BOOL
-ar5k_ar5210_enable_pspoll(hal, bssid, assoc_id)
- struct ath_hal *hal;
- u_int8_t *bssid;
- u_int16_t assoc_id;
+ar5k_ar5210_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
+ u_int16_t assoc_id)
{
AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_NO_PSPOLL |
@@ -2118,8 +1956,7 @@ ar5k_ar5210_enable_pspoll(hal, bssid, assoc_id)
}
HAL_BOOL
-ar5k_ar5210_disable_pspoll(hal)
- struct ath_hal *hal;
+ar5k_ar5210_disable_pspoll(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1,
AR5K_AR5210_STA_ID1_NO_PSPOLL |
@@ -2133,10 +1970,8 @@ ar5k_ar5210_disable_pspoll(hal)
*/
void
-ar5k_ar5210_init_beacon(hal, next_beacon, interval)
- struct ath_hal *hal;
- u_int32_t next_beacon;
- u_int32_t interval;
+ar5k_ar5210_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
+ u_int32_t interval)
{
u_int32_t timer1, timer2, timer3;
@@ -2172,13 +2007,9 @@ ar5k_ar5210_init_beacon(hal, next_beacon, interval)
}
void
-ar5k_ar5210_set_beacon_timers(hal, state, tsf, dtim_count, cfp_count)
- struct ath_hal *hal;
- const HAL_BEACON_STATE *state;
- u_int32_t tsf;
- u_int32_t dtim_count;
- u_int32_t cfp_count;
-
+ar5k_ar5210_set_beacon_timers(struct ath_hal *hal,
+ const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count,
+ u_int32_t cfp_count)
{
u_int32_t cfp_period, next_cfp;
@@ -2236,8 +2067,7 @@ ar5k_ar5210_set_beacon_timers(hal, state, tsf, dtim_count, cfp_count)
}
void
-ar5k_ar5210_reset_beacon(hal)
- struct ath_hal *hal;
+ar5k_ar5210_reset_beacon(struct ath_hal *hal)
{
/*
* Disable beacon timer
@@ -2253,9 +2083,7 @@ ar5k_ar5210_reset_beacon(hal)
}
HAL_BOOL
-ar5k_ar5210_wait_for_beacon(hal, phys_addr)
- struct ath_hal *hal;
- bus_addr_t phys_addr;
+ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
{
int i;
@@ -2288,16 +2116,13 @@ ar5k_ar5210_wait_for_beacon(hal, phys_addr)
*/
HAL_BOOL
-ar5k_ar5210_is_intr_pending(hal)
- struct ath_hal *hal;
+ar5k_ar5210_is_intr_pending(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
}
HAL_BOOL
-ar5k_ar5210_get_isr(hal, interrupt_mask)
- struct ath_hal *hal;
- u_int32_t *interrupt_mask;
+ar5k_ar5210_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
{
u_int32_t data;
@@ -2332,17 +2157,14 @@ ar5k_ar5210_get_isr(hal, interrupt_mask)
}
u_int32_t
-ar5k_ar5210_get_intr(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_intr(struct ath_hal *hal)
{
/* Return the interrupt mask stored previously */
return (hal->ah_imr);
}
HAL_INT
-ar5k_ar5210_set_intr(hal, new_mask)
- struct ath_hal *hal;
- HAL_INT new_mask;
+ar5k_ar5210_set_intr(struct ath_hal *hal, HAL_INT new_mask)
{
HAL_INT old_mask, int_mask;
@@ -2390,8 +2212,7 @@ ar5k_ar5210_set_intr(hal, new_mask)
*/
HAL_BOOL
-ar5k_ar5210_get_capabilities(hal)
- struct ath_hal *hal;
+ar5k_ar5210_get_capabilities(struct ath_hal *hal)
{
/* Set number of supported TX queues */
hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5210_TX_NUM_QUEUES;
@@ -2415,9 +2236,7 @@ ar5k_ar5210_get_capabilities(hal)
}
void
-ar5k_ar5210_radar_alert(hal, enable)
- struct ath_hal *hal;
- HAL_BOOL enable;
+ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
{
/*
* Set the RXPHY interrupt to be able to detect
@@ -2441,18 +2260,14 @@ ar5k_ar5210_radar_alert(hal, enable)
*/
HAL_BOOL
-ar5k_ar5210_eeprom_is_busy(hal)
- struct ath_hal *hal;
+ar5k_ar5210_eeprom_is_busy(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ?
AH_TRUE : AH_FALSE);
}
int
-ar5k_ar5210_eeprom_read(hal, offset, data)
- struct ath_hal *hal;
- u_int32_t offset;
- u_int16_t *data;
+ar5k_ar5210_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
{
u_int32_t status, timeout;
@@ -2480,10 +2295,7 @@ ar5k_ar5210_eeprom_read(hal, offset, data)
}
int
-ar5k_ar5210_eeprom_write(hal, offset, data)
- struct ath_hal *hal;
- u_int32_t offset;
- u_int16_t data;
+ar5k_ar5210_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
{
u_int32_t status, timeout;
diff --git a/sys/dev/ic/ar5211.c b/sys/dev/ic/ar5211.c
index 8ff066b1425..e14969c9b94 100644
--- a/sys/dev/ic/ar5211.c
+++ b/sys/dev/ic/ar5211.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar5211.c,v 1.20 2005/08/14 11:02:33 miod Exp $ */
+/* $OpenBSD: ar5211.c,v 1.21 2005/09/10 14:36:46 jsg Exp $ */
/*
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -45,8 +45,7 @@ static const struct ar5k_ar5211_ini_rf ar5211_rf[] =
AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,);
const void
-ar5k_ar5211_fill(hal)
- struct ath_hal *hal;
+ar5k_ar5211_fill(struct ath_hal *hal)
{
hal->ah_magic = AR5K_AR5211_MAGIC;
@@ -179,12 +178,8 @@ ar5k_ar5211_fill(hal)
}
struct ath_hal *
-ar5k_ar5211_attach(device, sc, st, sh, status)
- u_int16_t device;
- void *sc;
- bus_space_tag_t st;
- bus_space_handle_t sh;
- int *status;
+ar5k_ar5211_attach(u_int16_t device, void *sc, bus_space_tag_t st,
+ bus_space_handle_t sh, int *status)
{
struct ath_hal *hal = (struct ath_hal*) sc;
u_int8_t mac[IEEE80211_ADDR_LEN];
@@ -225,9 +220,7 @@ ar5k_ar5211_attach(device, sc, st, sh, status)
}
HAL_BOOL
-ar5k_ar5211_nic_reset(hal, val)
- struct ath_hal *hal;
- u_int32_t val;
+ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val)
{
HAL_BOOL ret = AH_FALSE;
u_int32_t mask = val ? val : ~0;
@@ -261,9 +254,7 @@ ar5k_ar5211_nic_reset(hal, val)
}
HAL_BOOL
-ar5k_ar5211_nic_wakeup(hal, flags)
- struct ath_hal *hal;
- u_int16_t flags;
+ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags)
{
u_int32_t turbo, mode, clock;
@@ -337,9 +328,7 @@ ar5k_ar5211_nic_wakeup(hal, flags)
}
u_int16_t
-ar5k_ar5211_radio_revision(hal, chip)
- struct ath_hal *hal;
- HAL_CHIP chip;
+ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip)
{
int i;
u_int32_t srev;
@@ -377,9 +366,7 @@ ar5k_ar5211_radio_revision(hal, chip)
}
const HAL_RATE_TABLE *
-ar5k_ar5211_get_rate_table(hal, mode)
- struct ath_hal *hal;
- u_int mode;
+ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode)
{
switch (mode) {
case HAL_MODE_11A:
@@ -399,8 +386,7 @@ ar5k_ar5211_get_rate_table(hal, mode)
}
void
-ar5k_ar5211_detach(hal)
- struct ath_hal *hal;
+ar5k_ar5211_detach(struct ath_hal *hal)
{
/*
* Free HAL structure, assume interrupts are down
@@ -409,12 +395,8 @@ ar5k_ar5211_detach(hal)
}
HAL_BOOL
-ar5k_ar5211_reset(hal, op_mode, channel, change_channel, status)
- struct ath_hal *hal;
- HAL_OPMODE op_mode;
- HAL_CHANNEL *channel;
- HAL_BOOL change_channel;
- HAL_STATUS *status;
+ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
+ HAL_BOOL change_channel, HAL_STATUS *status)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int8_t mac[IEEE80211_ADDR_LEN];
@@ -665,8 +647,7 @@ ar5k_ar5211_reset(hal, op_mode, channel, change_channel, status)
}
void
-ar5k_ar5211_set_opmode(hal)
- struct ath_hal *hal;
+ar5k_ar5211_set_opmode(struct ath_hal *hal)
{
u_int32_t pcu_reg, low_id, high_id;
@@ -704,9 +685,7 @@ ar5k_ar5211_set_opmode(hal)
}
HAL_BOOL
-ar5k_ar5211_calibrate(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
{
u_int32_t i_pwr, q_pwr;
int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd;
@@ -748,9 +727,7 @@ ar5k_ar5211_calibrate(hal, channel)
*/
HAL_BOOL
-ar5k_ar5211_update_tx_triglevel(hal, increase)
- struct ath_hal *hal;
- HAL_BOOL increase;
+ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
{
u_int32_t trigger_level, imr;
HAL_BOOL status = AH_FALSE;
@@ -787,10 +764,8 @@ ar5k_ar5211_update_tx_triglevel(hal, increase)
}
int
-ar5k_ar5211_setup_tx_queue(hal, queue_type, queue_info)
- struct ath_hal *hal;
- HAL_TX_QUEUE queue_type;
- const HAL_TXQ_INFO *queue_info;
+ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
+ const HAL_TXQ_INFO *queue_info)
{
u_int queue;
@@ -830,10 +805,8 @@ ar5k_ar5211_setup_tx_queue(hal, queue_type, queue_info)
}
HAL_BOOL
-ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info)
- struct ath_hal *hal;
- int queue;
- const HAL_TXQ_INFO *queue_info;
+ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue,
+ const HAL_TXQ_INFO *queue_info)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -852,9 +825,7 @@ ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info)
}
HAL_BOOL
-ar5k_ar5211_release_tx_queue(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -866,9 +837,7 @@ ar5k_ar5211_release_tx_queue(hal, queue)
}
HAL_BOOL
-ar5k_ar5211_reset_tx_queue(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue)
{
u_int32_t cw_min, cw_max, retry_lg, retry_sh;
struct ieee80211_channel *channel = (struct ieee80211_channel*)
@@ -1044,9 +1013,7 @@ ar5k_ar5211_reset_tx_queue(hal, queue)
}
u_int32_t
-ar5k_ar5211_get_tx_buf(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1057,10 +1024,7 @@ ar5k_ar5211_get_tx_buf(hal, queue)
}
HAL_BOOL
-ar5k_ar5211_put_tx_buf(hal, queue, phys_addr)
- struct ath_hal *hal;
- u_int queue;
- u_int32_t phys_addr;
+ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1077,9 +1041,7 @@ ar5k_ar5211_put_tx_buf(hal, queue, phys_addr)
}
HAL_BOOL
-ar5k_ar5211_tx_start(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1094,9 +1056,7 @@ ar5k_ar5211_tx_start(hal, queue)
}
HAL_BOOL
-ar5k_ar5211_stop_tx_dma(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue)
{
int i = 100, pending;
@@ -1120,22 +1080,10 @@ ar5k_ar5211_stop_tx_dma(hal, queue)
}
HAL_BOOL
-ar5k_ar5211_setup_tx_desc(hal, desc, packet_length, header_length, type,
- tx_power, tx_rate0, tx_tries0, key_index, antenna_mode, flags, rtscts_rate,
- rtscts_duration)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int packet_length;
- u_int header_length;
- HAL_PKT_TYPE type;
- u_int tx_power;
- u_int tx_rate0;
- u_int tx_tries0;
- u_int key_index;
- u_int antenna_mode;
- u_int flags;
- u_int rtscts_rate;
- u_int rtscts_duration;
+ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
+ u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
+ u_int flags, u_int rtscts_rate, u_int rtscts_duration)
{
struct ar5k_ar5211_tx_desc *tx_desc;
@@ -1185,12 +1133,8 @@ ar5k_ar5211_setup_tx_desc(hal, desc, packet_length, header_length, type,
}
HAL_BOOL
-ar5k_ar5211_fill_tx_desc(hal, desc, segment_length, first_segment, last_segment)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int segment_length;
- HAL_BOOL first_segment;
- HAL_BOOL last_segment;
+ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment)
{
struct ar5k_ar5211_tx_desc *tx_desc;
@@ -1214,24 +1158,15 @@ ar5k_ar5211_fill_tx_desc(hal, desc, segment_length, first_segment, last_segment)
}
HAL_BOOL
-ar5k_ar5211_setup_xtx_desc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
- tx_rate3, tx_tries3)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int tx_rate1;
- u_int tx_tries1;
- u_int tx_rate2;
- u_int tx_tries2;
- u_int tx_rate3;
- u_int tx_tries3;
+ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
+ u_int tx_rate3, u_int tx_tries3)
{
return (AH_FALSE);
}
HAL_STATUS
-ar5k_ar5211_proc_tx_desc(hal, desc)
- struct ath_hal *hal;
- struct ath_desc *desc;
+ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
{
struct ar5k_ar5211_tx_status *tx_status;
struct ar5k_ar5211_tx_desc *tx_desc;
@@ -1286,8 +1221,7 @@ ar5k_ar5211_proc_tx_desc(hal, desc)
}
HAL_BOOL
-ar5k_ar5211_has_veol(hal)
- struct ath_hal *hal;
+ar5k_ar5211_has_veol(struct ath_hal *hal)
{
return (AH_TRUE);
}
@@ -1297,30 +1231,25 @@ ar5k_ar5211_has_veol(hal)
*/
u_int32_t
-ar5k_ar5211_get_rx_buf(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_rx_buf(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5211_RXDP));
}
void
-ar5k_ar5211_put_rx_buf(hal, phys_addr)
- struct ath_hal *hal;
- u_int32_t phys_addr;
+ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
{
AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr);
}
void
-ar5k_ar5211_start_rx(hal)
- struct ath_hal *hal;
+ar5k_ar5211_start_rx(struct ath_hal *hal)
{
AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE);
}
HAL_BOOL
-ar5k_ar5211_stop_rx_dma(hal)
- struct ath_hal *hal;
+ar5k_ar5211_stop_rx_dma(struct ath_hal *hal)
{
int i;
@@ -1338,24 +1267,20 @@ ar5k_ar5211_stop_rx_dma(hal)
}
void
-ar5k_ar5211_start_rx_pcu(hal)
- struct ath_hal *hal;
+ar5k_ar5211_start_rx_pcu(struct ath_hal *hal)
{
AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX);
}
void
-ar5k_ar5211_stop_pcu_recv(hal)
- struct ath_hal *hal;
+ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX);
}
void
-ar5k_ar5211_set_mcast_filter(hal, filter0, filter1)
- struct ath_hal *hal;
- u_int32_t filter0;
- u_int32_t filter1;
+ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
+ u_int32_t filter1)
{
/* Set the multicat filter */
AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0);
@@ -1363,9 +1288,7 @@ ar5k_ar5211_set_mcast_filter(hal, filter0, filter1)
}
HAL_BOOL
-ar5k_ar5211_set_mcast_filterindex(hal, index)
- struct ath_hal *hal;
- u_int32_t index;
+ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
{
if (index >= 64) {
return (AH_FALSE);
@@ -1381,9 +1304,7 @@ ar5k_ar5211_set_mcast_filterindex(hal, index)
}
HAL_BOOL
-ar5k_ar5211_clear_mcast_filter_idx(hal, index)
- struct ath_hal *hal;
- u_int32_t index;
+ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
{
if (index >= 64) {
@@ -1400,26 +1321,20 @@ ar5k_ar5211_clear_mcast_filter_idx(hal, index)
}
u_int32_t
-ar5k_ar5211_get_rx_filter(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_rx_filter(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER));
}
void
-ar5k_ar5211_set_rx_filter(hal, filter)
- struct ath_hal *hal;
- u_int32_t filter;
+ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
{
AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter);
}
HAL_BOOL
-ar5k_ar5211_setup_rx_desc(hal, desc, size, flags)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int32_t size;
- u_int flags;
+ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int32_t size, u_int flags)
{
struct ar5k_ar5211_rx_desc *rx_desc;
@@ -1436,11 +1351,8 @@ ar5k_ar5211_setup_rx_desc(hal, desc, size, flags)
}
HAL_STATUS
-ar5k_ar5211_proc_rx_desc(hal, desc, phys_addr, next)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int32_t phys_addr;
- struct ath_desc *next;
+ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int32_t phys_addr, struct ath_desc *next)
{
struct ar5k_ar5211_rx_status *rx_status;
@@ -1508,8 +1420,7 @@ ar5k_ar5211_proc_rx_desc(hal, desc, phys_addr, next)
}
void
-ar5k_ar5211_set_rx_signal(hal)
- struct ath_hal *hal;
+ar5k_ar5211_set_rx_signal(struct ath_hal *hal)
{
/* Signal state monitoring is not yet supported */
}
@@ -1519,8 +1430,7 @@ ar5k_ar5211_set_rx_signal(hal)
*/
void
-ar5k_ar5211_dump_state(hal)
- struct ath_hal *hal;
+ar5k_ar5211_dump_state(struct ath_hal *hal)
{
#ifdef AR5K_DEBUG
#define AR5K_PRINT_REGISTER(_x) \
@@ -1609,12 +1519,8 @@ ar5k_ar5211_dump_state(hal)
}
HAL_BOOL
-ar5k_ar5211_get_diag_state(hal, id, device, size)
- struct ath_hal *hal;
- int id;
- void **device;
- u_int *size;
-
+ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device,
+ u_int *size)
{
/*
* We'll ignore this right now. This seems to be some kind of an obscure
@@ -1624,17 +1530,13 @@ ar5k_ar5211_get_diag_state(hal, id, device, size)
}
void
-ar5k_ar5211_get_lladdr(hal, mac)
- struct ath_hal *hal;
- u_int8_t *mac;
+ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
{
bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
}
HAL_BOOL
-ar5k_ar5211_set_lladdr(hal, mac)
- struct ath_hal *hal;
- const u_int8_t *mac;
+ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
{
u_int32_t low_id, high_id;
@@ -1652,11 +1554,8 @@ ar5k_ar5211_set_lladdr(hal, mac)
}
HAL_BOOL
-ar5k_ar5211_set_regdomain(hal, regdomain, status)
- struct ath_hal *hal;
- u_int16_t regdomain;
- HAL_STATUS *status;
-
+ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
+ HAL_STATUS *status)
{
ieee80211_regdomain_t ieee_regdomain;
@@ -1674,9 +1573,7 @@ ar5k_ar5211_set_regdomain(hal, regdomain, status)
}
void
-ar5k_ar5211_set_ledstate(hal, state)
- struct ath_hal *hal;
- HAL_LED_STATE state;
+ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
{
u_int32_t led;
@@ -1714,11 +1611,8 @@ ar5k_ar5211_set_ledstate(hal, state)
}
void
-ar5k_ar5211_set_associd(hal, bssid, assoc_id, tim_offset)
- struct ath_hal *hal;
- const u_int8_t *bssid;
- u_int16_t assoc_id;
- u_int16_t tim_offset;
+ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
+ u_int16_t assoc_id, u_int16_t tim_offset)
{
u_int32_t low_id, high_id;
@@ -1748,9 +1642,7 @@ ar5k_ar5211_set_associd(hal, bssid, assoc_id, tim_offset)
}
HAL_BOOL
-ar5k_ar5211_set_gpio_output(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5211_NUM_GPIO)
return (AH_FALSE);
@@ -1763,9 +1655,7 @@ ar5k_ar5211_set_gpio_output(hal, gpio)
}
HAL_BOOL
-ar5k_ar5211_set_gpio_input(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5211_NUM_GPIO)
return (AH_FALSE);
@@ -1778,9 +1668,7 @@ ar5k_ar5211_set_gpio_input(hal, gpio)
}
u_int32_t
-ar5k_ar5211_get_gpio(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5211_NUM_GPIO)
return (0xffffffff);
@@ -1791,10 +1679,7 @@ ar5k_ar5211_get_gpio(hal, gpio)
}
HAL_BOOL
-ar5k_ar5211_set_gpio(hal, gpio, val)
- struct ath_hal *hal;
- u_int32_t gpio;
- u_int32_t val;
+ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
{
u_int32_t data;
@@ -1813,10 +1698,8 @@ ar5k_ar5211_set_gpio(hal, gpio, val)
}
void
-ar5k_ar5211_set_gpio_intr(hal, gpio, interrupt_level)
- struct ath_hal *hal;
- u_int gpio;
- u_int32_t interrupt_level;
+ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio,
+ u_int32_t interrupt_level)
{
u_int32_t data;
@@ -1841,15 +1724,13 @@ ar5k_ar5211_set_gpio_intr(hal, gpio, interrupt_level)
}
u_int32_t
-ar5k_ar5211_get_tsf32(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_tsf32(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5211_TSF_L32));
}
u_int64_t
-ar5k_ar5211_get_tsf64(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_tsf64(struct ath_hal *hal)
{
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32);
@@ -1857,23 +1738,20 @@ ar5k_ar5211_get_tsf64(hal)
}
void
-ar5k_ar5211_reset_tsf(hal)
- struct ath_hal *hal;
+ar5k_ar5211_reset_tsf(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON,
AR5K_AR5211_BEACON_RESET_TSF);
}
u_int16_t
-ar5k_ar5211_get_regdomain(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_regdomain(struct ath_hal *hal)
{
return (ar5k_get_regdomain(hal));
}
HAL_BOOL
-ar5k_ar5211_detect_card_present(hal)
- struct ath_hal *hal;
+ar5k_ar5211_detect_card_present(struct ath_hal *hal)
{
u_int16_t magic;
@@ -1889,9 +1767,7 @@ ar5k_ar5211_detect_card_present(hal)
}
void
-ar5k_ar5211_update_mib_counters(hal, statistics)
- struct ath_hal *hal;
- HAL_MIB_STATS *statistics;
+ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
{
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL);
statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL);
@@ -1901,16 +1777,13 @@ ar5k_ar5211_update_mib_counters(hal, statistics)
}
HAL_RFGAIN
-ar5k_ar5211_get_rf_gain(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_rf_gain(struct ath_hal *hal)
{
return (HAL_RFGAIN_INACTIVE);
}
HAL_BOOL
-ar5k_ar5211_set_slot_time(hal, slot_time)
- struct ath_hal *hal;
- u_int slot_time;
+ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time)
{
if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
return (AH_FALSE);
@@ -1921,16 +1794,13 @@ ar5k_ar5211_set_slot_time(hal, slot_time)
}
u_int
-ar5k_ar5211_get_slot_time(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_slot_time(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff);
}
HAL_BOOL
-ar5k_ar5211_set_ack_timeout(hal, timeout)
- struct ath_hal *hal;
- u_int timeout;
+ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout)
{
if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK),
hal->ah_turbo) <= timeout)
@@ -1943,17 +1813,14 @@ ar5k_ar5211_set_ack_timeout(hal, timeout)
}
u_int
-ar5k_ar5211_get_ack_timeout(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_ack_timeout(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
AR5K_AR5211_TIME_OUT_ACK), hal->ah_turbo));
}
HAL_BOOL
-ar5k_ar5211_set_cts_timeout(hal, timeout)
- struct ath_hal *hal;
- u_int timeout;
+ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout)
{
if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS),
hal->ah_turbo) <= timeout)
@@ -1966,8 +1833,7 @@ ar5k_ar5211_set_cts_timeout(hal, timeout)
}
u_int
-ar5k_ar5211_get_cts_timeout(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_cts_timeout(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
AR5K_AR5211_TIME_OUT_CTS), hal->ah_turbo));
@@ -1978,9 +1844,7 @@ ar5k_ar5211_get_cts_timeout(hal)
*/
HAL_BOOL
-ar5k_ar5211_is_cipher_supported(hal, cipher)
- struct ath_hal *hal;
- HAL_CIPHER cipher;
+ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
{
/*
* The AR5211 only supports WEP
@@ -1992,16 +1856,13 @@ ar5k_ar5211_is_cipher_supported(hal, cipher)
}
u_int32_t
-ar5k_ar5211_get_keycache_size(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_keycache_size(struct ath_hal *hal)
{
return (AR5K_AR5211_KEYCACHE_SIZE);
}
HAL_BOOL
-ar5k_ar5211_reset_key(hal, entry)
- struct ath_hal *hal;
- u_int16_t entry;
+ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry)
{
int i;
@@ -2014,9 +1875,7 @@ ar5k_ar5211_reset_key(hal, entry)
}
HAL_BOOL
-ar5k_ar5211_is_key_valid(hal, entry)
- struct ath_hal *hal;
- u_int16_t entry;
+ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry)
{
AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE);
@@ -2031,12 +1890,8 @@ ar5k_ar5211_is_key_valid(hal, entry)
}
HAL_BOOL
-ar5k_ar5211_set_key(hal, entry, keyval, mac, xor_notused)
- struct ath_hal *hal;
- u_int16_t entry;
- const HAL_KEYVAL *keyval;
- const u_int8_t *mac;
- int xor_notused;
+ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry,
+ const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused)
{
int i;
u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2];
@@ -2082,10 +1937,8 @@ ar5k_ar5211_set_key(hal, entry, keyval, mac, xor_notused)
}
HAL_BOOL
-ar5k_ar5211_set_key_lladdr(hal, entry, mac)
- struct ath_hal *hal;
- u_int16_t entry;
- const u_int8_t *mac;
+ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
+ const u_int8_t *mac)
{
u_int32_t low_id, high_id;
const u_int8_t *mac_v;
@@ -2113,11 +1966,8 @@ ar5k_ar5211_set_key_lladdr(hal, entry, mac)
*/
HAL_BOOL
-ar5k_ar5211_set_power(hal, mode, set_chip, sleep_duration)
- struct ath_hal *hal;
- HAL_POWER_MODE mode;
- HAL_BOOL set_chip;
- u_int16_t sleep_duration;
+ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
+ HAL_BOOL set_chip, u_int16_t sleep_duration)
{
u_int32_t staid;
int i;
@@ -2182,23 +2032,20 @@ ar5k_ar5211_set_power(hal, mode, set_chip, sleep_duration)
}
HAL_POWER_MODE
-ar5k_ar5211_get_power_mode(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_power_mode(struct ath_hal *hal)
{
return (hal->ah_power_mode);
}
HAL_BOOL
-ar5k_ar5211_query_pspoll_support(hal)
- struct ath_hal *hal;
+ar5k_ar5211_query_pspoll_support(struct ath_hal *hal)
{
/* nope */
return (AH_FALSE);
}
HAL_BOOL
-ar5k_ar5211_init_pspoll(hal)
- struct ath_hal *hal;
+ar5k_ar5211_init_pspoll(struct ath_hal *hal)
{
/*
* Not used on the AR5211
@@ -2207,17 +2054,14 @@ ar5k_ar5211_init_pspoll(hal)
}
HAL_BOOL
-ar5k_ar5211_enable_pspoll(hal, bssid, assoc_id)
- struct ath_hal *hal;
- u_int8_t *bssid;
- u_int16_t assoc_id;
+ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
+ u_int16_t assoc_id)
{
return (AH_FALSE);
}
HAL_BOOL
-ar5k_ar5211_disable_pspoll(hal)
- struct ath_hal *hal;
+ar5k_ar5211_disable_pspoll(struct ath_hal *hal)
{
return (AH_FALSE);
}
@@ -2227,10 +2071,8 @@ ar5k_ar5211_disable_pspoll(hal)
*/
void
-ar5k_ar5211_init_beacon(hal, next_beacon, interval)
- struct ath_hal *hal;
- u_int32_t next_beacon;
- u_int32_t interval;
+ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
+ u_int32_t interval)
{
u_int32_t timer1, timer2, timer3;
@@ -2268,13 +2110,9 @@ ar5k_ar5211_init_beacon(hal, next_beacon, interval)
}
void
-ar5k_ar5211_set_beacon_timers(hal, state, tsf, dtim_count, cfp_count)
- struct ath_hal *hal;
- const HAL_BEACON_STATE *state;
- u_int32_t tsf;
- u_int32_t dtim_count;
- u_int32_t cfp_count;
-
+ar5k_ar5211_set_beacon_timers(struct ath_hal *hal,
+ const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count,
+ u_int32_t cfp_count)
{
u_int32_t cfp_period, next_cfp;
@@ -2335,8 +2173,7 @@ ar5k_ar5211_set_beacon_timers(hal, state, tsf, dtim_count, cfp_count)
}
void
-ar5k_ar5211_reset_beacon(hal)
- struct ath_hal *hal;
+ar5k_ar5211_reset_beacon(struct ath_hal *hal)
{
/*
* Disable beacon timer
@@ -2352,9 +2189,7 @@ ar5k_ar5211_reset_beacon(hal)
}
HAL_BOOL
-ar5k_ar5211_wait_for_beacon(hal, phys_addr)
- struct ath_hal *hal;
- bus_addr_t phys_addr;
+ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
{
HAL_BOOL ret;
@@ -2376,16 +2211,13 @@ ar5k_ar5211_wait_for_beacon(hal, phys_addr)
*/
HAL_BOOL
-ar5k_ar5211_is_intr_pending(hal)
- struct ath_hal *hal;
+ar5k_ar5211_is_intr_pending(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
}
HAL_BOOL
-ar5k_ar5211_get_isr(hal, interrupt_mask)
- struct ath_hal *hal;
- u_int32_t *interrupt_mask;
+ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
{
u_int32_t data;
@@ -2422,17 +2254,14 @@ ar5k_ar5211_get_isr(hal, interrupt_mask)
}
u_int32_t
-ar5k_ar5211_get_intr(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_intr(struct ath_hal *hal)
{
/* Return the interrupt mask stored previously */
return (hal->ah_imr);
}
HAL_INT
-ar5k_ar5211_set_intr(hal, new_mask)
- struct ath_hal *hal;
- HAL_INT new_mask;
+ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask)
{
HAL_INT old_mask, int_mask;
@@ -2488,8 +2317,7 @@ ar5k_ar5211_set_intr(hal, new_mask)
*/
HAL_BOOL
-ar5k_ar5211_get_capabilities(hal)
- struct ath_hal *hal;
+ar5k_ar5211_get_capabilities(struct ath_hal *hal)
{
u_int16_t ee_header;
@@ -2540,9 +2368,7 @@ ar5k_ar5211_get_capabilities(hal)
}
void
-ar5k_ar5211_radar_alert(hal, enable)
- struct ath_hal *hal;
- HAL_BOOL enable;
+ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
{
/*
* Enable radar detection
@@ -2569,18 +2395,14 @@ ar5k_ar5211_radar_alert(hal, enable)
*/
HAL_BOOL
-ar5k_ar5211_eeprom_is_busy(hal)
- struct ath_hal *hal;
+ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ?
AH_TRUE : AH_FALSE);
}
int
-ar5k_ar5211_eeprom_read(hal, offset, data)
- struct ath_hal *hal;
- u_int32_t offset;
- u_int16_t *data;
+ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
{
u_int32_t status, i;
@@ -2607,10 +2429,7 @@ ar5k_ar5211_eeprom_read(hal, offset, data)
}
int
-ar5k_ar5211_eeprom_write(hal, offset, data)
- struct ath_hal *hal;
- u_int32_t offset;
- u_int16_t data;
+ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
{
u_int32_t status, timeout;
@@ -2643,10 +2462,8 @@ ar5k_ar5211_eeprom_write(hal, offset, data)
*/
void
-ar5k_ar5211_rfregs(hal, channel, freq, ee_mode)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
- u_int freq, ee_mode;
+ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq,
+ u_int ee_mode)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
struct ar5k_ar5211_ini_rf rf[AR5K_ELEMENTS(ar5211_rf)];
diff --git a/sys/dev/ic/ar5212.c b/sys/dev/ic/ar5212.c
index 5591bf123a0..aac1722c595 100644
--- a/sys/dev/ic/ar5212.c
+++ b/sys/dev/ic/ar5212.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar5212.c,v 1.24 2005/08/14 11:02:33 miod Exp $ */
+/* $OpenBSD: ar5212.c,v 1.25 2005/09/10 14:36:46 jsg Exp $ */
/*
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -42,8 +42,7 @@ static const struct ar5k_ar5212_ini_mode ar5212_mode[] =
AR5K_HAL_FUNCTIONS(extern, ar5k_ar5212,);
const void
-ar5k_ar5212_fill(hal)
- struct ath_hal *hal;
+ar5k_ar5212_fill(struct ath_hal *hal)
{
hal->ah_magic = AR5K_AR5212_MAGIC;
@@ -176,12 +175,8 @@ ar5k_ar5212_fill(hal)
}
struct ath_hal *
-ar5k_ar5212_attach(device, sc, st, sh, status)
- u_int16_t device;
- void *sc;
- bus_space_tag_t st;
- bus_space_handle_t sh;
- int *status;
+ar5k_ar5212_attach(u_int16_t device, void *sc, bus_space_tag_t st,
+ bus_space_handle_t sh, int *status)
{
struct ath_hal *hal = (struct ath_hal*) sc;
u_int8_t mac[IEEE80211_ADDR_LEN];
@@ -223,9 +218,7 @@ ar5k_ar5212_attach(device, sc, st, sh, status)
}
HAL_BOOL
-ar5k_ar5212_nic_reset(hal, val)
- struct ath_hal *hal;
- u_int32_t val;
+ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val)
{
HAL_BOOL ret = AH_FALSE;
u_int32_t mask = val ? val : ~0;
@@ -259,9 +252,7 @@ ar5k_ar5212_nic_reset(hal, val)
}
HAL_BOOL
-ar5k_ar5212_nic_wakeup(hal, flags)
- struct ath_hal *hal;
- u_int16_t flags;
+ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags)
{
u_int32_t turbo, mode, clock;
@@ -343,9 +334,7 @@ ar5k_ar5212_nic_wakeup(hal, flags)
}
u_int16_t
-ar5k_ar5212_radio_revision(hal, chip)
- struct ath_hal *hal;
- HAL_CHIP chip;
+ar5k_ar5212_radio_revision(struct ath_hal *hal, HAL_CHIP chip)
{
int i;
u_int32_t srev;
@@ -383,9 +372,7 @@ ar5k_ar5212_radio_revision(hal, chip)
}
const HAL_RATE_TABLE *
-ar5k_ar5212_get_rate_table(hal, mode)
- struct ath_hal *hal;
- u_int mode;
+ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode)
{
switch (mode) {
case HAL_MODE_11A:
@@ -407,8 +394,7 @@ ar5k_ar5212_get_rate_table(hal, mode)
}
void
-ar5k_ar5212_detach(hal)
- struct ath_hal *hal;
+ar5k_ar5212_detach(struct ath_hal *hal)
{
if (hal->ah_rf_banks != NULL)
free(hal->ah_rf_banks, M_DEVBUF);
@@ -420,12 +406,8 @@ ar5k_ar5212_detach(hal)
}
HAL_BOOL
-ar5k_ar5212_reset(hal, op_mode, channel, change_channel, status)
- struct ath_hal *hal;
- HAL_OPMODE op_mode;
- HAL_CHANNEL *channel;
- HAL_BOOL change_channel;
- HAL_STATUS *status;
+ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
+ HAL_BOOL change_channel, HAL_STATUS *status)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int8_t mac[IEEE80211_ADDR_LEN];
@@ -794,8 +776,7 @@ ar5k_ar5212_reset(hal, op_mode, channel, change_channel, status)
}
void
-ar5k_ar5212_set_opmode(hal)
- struct ath_hal *hal;
+ar5k_ar5212_set_opmode(struct ath_hal *hal)
{
u_int32_t pcu_reg, low_id, high_id;
@@ -833,9 +814,7 @@ ar5k_ar5212_set_opmode(hal)
}
HAL_BOOL
-ar5k_ar5212_calibrate(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
{
u_int32_t i_pwr, q_pwr;
int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd;
@@ -886,9 +865,7 @@ ar5k_ar5212_calibrate(hal, channel)
*/
HAL_BOOL
-ar5k_ar5212_update_tx_triglevel(hal, increase)
- struct ath_hal *hal;
- HAL_BOOL increase;
+ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
{
u_int32_t trigger_level, imr;
HAL_BOOL status = AH_FALSE;
@@ -925,10 +902,8 @@ ar5k_ar5212_update_tx_triglevel(hal, increase)
}
int
-ar5k_ar5212_setup_tx_queue(hal, queue_type, queue_info)
- struct ath_hal *hal;
- HAL_TX_QUEUE queue_type;
- const HAL_TXQ_INFO *queue_info;
+ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
+ const HAL_TXQ_INFO *queue_info)
{
u_int queue;
@@ -968,10 +943,8 @@ ar5k_ar5212_setup_tx_queue(hal, queue_type, queue_info)
}
HAL_BOOL
-ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info)
- struct ath_hal *hal;
- int queue;
- const HAL_TXQ_INFO *queue_info;
+ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue,
+ const HAL_TXQ_INFO *queue_info)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -990,9 +963,7 @@ ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info)
}
HAL_BOOL
-ar5k_ar5212_release_tx_queue(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1004,9 +975,7 @@ ar5k_ar5212_release_tx_queue(hal, queue)
}
HAL_BOOL
-ar5k_ar5212_reset_tx_queue(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue)
{
u_int32_t cw_min, cw_max, retry_lg, retry_sh;
struct ieee80211_channel *channel = (struct ieee80211_channel*)
@@ -1186,9 +1155,7 @@ ar5k_ar5212_reset_tx_queue(hal, queue)
}
u_int32_t
-ar5k_ar5212_get_tx_buf(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5212_get_tx_buf(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1199,10 +1166,7 @@ ar5k_ar5212_get_tx_buf(hal, queue)
}
HAL_BOOL
-ar5k_ar5212_put_tx_buf(hal, queue, phys_addr)
- struct ath_hal *hal;
- u_int queue;
- u_int32_t phys_addr;
+ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1219,9 +1183,7 @@ ar5k_ar5212_put_tx_buf(hal, queue, phys_addr)
}
HAL_BOOL
-ar5k_ar5212_tx_start(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue)
{
AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
@@ -1236,9 +1198,7 @@ ar5k_ar5212_tx_start(hal, queue)
}
HAL_BOOL
-ar5k_ar5212_stop_tx_dma(hal, queue)
- struct ath_hal *hal;
- u_int queue;
+ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue)
{
int i = 100, pending;
@@ -1262,22 +1222,10 @@ ar5k_ar5212_stop_tx_dma(hal, queue)
}
HAL_BOOL
-ar5k_ar5212_setup_tx_desc(hal, desc, packet_length, header_length, type,
- tx_power, tx_rate0, tx_tries0, key_index, antenna_mode, flags, rtscts_rate,
- rtscts_duration)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int packet_length;
- u_int header_length;
- HAL_PKT_TYPE type;
- u_int tx_power;
- u_int tx_rate0;
- u_int tx_tries0;
- u_int key_index;
- u_int antenna_mode;
- u_int flags;
- u_int rtscts_rate;
- u_int rtscts_duration;
+ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
+ u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
+ u_int flags, u_int rtscts_rate, u_int rtscts_duration)
{
struct ar5k_ar5212_tx_desc *tx_desc;
@@ -1347,12 +1295,8 @@ ar5k_ar5212_setup_tx_desc(hal, desc, packet_length, header_length, type,
}
HAL_BOOL
-ar5k_ar5212_fill_tx_desc(hal, desc, segment_length, first_segment, last_segment)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int segment_length;
- HAL_BOOL first_segment;
- HAL_BOOL last_segment;
+ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment)
{
struct ar5k_ar5212_tx_desc *tx_desc;
@@ -1376,16 +1320,9 @@ ar5k_ar5212_fill_tx_desc(hal, desc, segment_length, first_segment, last_segment)
}
HAL_BOOL
-ar5k_ar5212_setup_xtx_desc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
- tx_rate3, tx_tries3)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int tx_rate1;
- u_int tx_tries1;
- u_int tx_rate2;
- u_int tx_tries2;
- u_int tx_rate3;
- u_int tx_tries3;
+ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
+ u_int tx_rate3, u_int tx_tries3)
{
struct ar5k_ar5212_tx_desc *tx_desc;
@@ -1411,9 +1348,7 @@ ar5k_ar5212_setup_xtx_desc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
}
HAL_STATUS
-ar5k_ar5212_proc_tx_desc(hal, desc)
- struct ath_hal *hal;
- struct ath_desc *desc;
+ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
{
struct ar5k_ar5212_tx_status *tx_status;
struct ar5k_ar5212_tx_desc *tx_desc;
@@ -1498,8 +1433,7 @@ ar5k_ar5212_proc_tx_desc(hal, desc)
}
HAL_BOOL
-ar5k_ar5212_has_veol(hal)
- struct ath_hal *hal;
+ar5k_ar5212_has_veol(struct ath_hal *hal)
{
return (AH_TRUE);
}
@@ -1509,30 +1443,25 @@ ar5k_ar5212_has_veol(hal)
*/
u_int32_t
-ar5k_ar5212_get_rx_buf(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_rx_buf(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5212_RXDP));
}
void
-ar5k_ar5212_put_rx_buf(hal, phys_addr)
- struct ath_hal *hal;
- u_int32_t phys_addr;
+ar5k_ar5212_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
{
AR5K_REG_WRITE(AR5K_AR5212_RXDP, phys_addr);
}
void
-ar5k_ar5212_start_rx(hal)
- struct ath_hal *hal;
+ar5k_ar5212_start_rx(struct ath_hal *hal)
{
AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE);
}
HAL_BOOL
-ar5k_ar5212_stop_rx_dma(hal)
- struct ath_hal *hal;
+ar5k_ar5212_stop_rx_dma(struct ath_hal *hal)
{
int i;
@@ -1550,24 +1479,20 @@ ar5k_ar5212_stop_rx_dma(hal)
}
void
-ar5k_ar5212_start_rx_pcu(hal)
- struct ath_hal *hal;
+ar5k_ar5212_start_rx_pcu(struct ath_hal *hal)
{
AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX);
}
void
-ar5k_ar5212_stop_pcu_recv(hal)
- struct ath_hal *hal;
+ar5k_ar5212_stop_pcu_recv(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX);
}
void
-ar5k_ar5212_set_mcast_filter(hal, filter0, filter1)
- struct ath_hal *hal;
- u_int32_t filter0;
- u_int32_t filter1;
+ar5k_ar5212_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
+ u_int32_t filter1)
{
/* Set the multicat filter */
AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL0, filter0);
@@ -1575,9 +1500,7 @@ ar5k_ar5212_set_mcast_filter(hal, filter0, filter1)
}
HAL_BOOL
-ar5k_ar5212_set_mcast_filterindex(hal, index)
- struct ath_hal *hal;
- u_int32_t index;
+ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
{
if (index >= 64) {
return (AH_FALSE);
@@ -1593,9 +1516,7 @@ ar5k_ar5212_set_mcast_filterindex(hal, index)
}
HAL_BOOL
-ar5k_ar5212_clear_mcast_filter_idx(hal, index)
- struct ath_hal *hal;
- u_int32_t index;
+ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
{
if (index >= 64) {
@@ -1612,8 +1533,7 @@ ar5k_ar5212_clear_mcast_filter_idx(hal, index)
}
u_int32_t
-ar5k_ar5212_get_rx_filter(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_rx_filter(struct ath_hal *hal)
{
u_int32_t data, filter = 0;
@@ -1630,9 +1550,7 @@ ar5k_ar5212_get_rx_filter(hal)
}
void
-ar5k_ar5212_set_rx_filter(hal, filter)
- struct ath_hal *hal;
- u_int32_t filter;
+ar5k_ar5212_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
{
u_int32_t data = 0;
@@ -1655,11 +1573,8 @@ ar5k_ar5212_set_rx_filter(hal, filter)
}
HAL_BOOL
-ar5k_ar5212_setup_rx_desc(hal, desc, size, flags)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int32_t size;
- u_int flags;
+ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int32_t size, u_int flags)
{
struct ar5k_ar5212_rx_desc *rx_desc;
@@ -1676,11 +1591,8 @@ ar5k_ar5212_setup_rx_desc(hal, desc, size, flags)
}
HAL_STATUS
-ar5k_ar5212_proc_rx_desc(hal, desc, phys_addr, next)
- struct ath_hal *hal;
- struct ath_desc *desc;
- u_int32_t phys_addr;
- struct ath_desc *next;
+ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
+ u_int32_t phys_addr, struct ath_desc *next)
{
struct ar5k_ar5212_rx_status *rx_status;
struct ar5k_ar5212_rx_error *rx_err;
@@ -1756,8 +1668,7 @@ ar5k_ar5212_proc_rx_desc(hal, desc, phys_addr, next)
}
void
-ar5k_ar5212_set_rx_signal(hal)
- struct ath_hal *hal;
+ar5k_ar5212_set_rx_signal(struct ath_hal *hal)
{
/* Signal state monitoring is not yet supported */
}
@@ -1767,8 +1678,7 @@ ar5k_ar5212_set_rx_signal(hal)
*/
void
-ar5k_ar5212_dump_state(hal)
- struct ath_hal *hal;
+ar5k_ar5212_dump_state(struct ath_hal *hal)
{
#ifdef AR5K_DEBUG
#define AR5K_PRINT_REGISTER(_x) \
@@ -1872,12 +1782,8 @@ ar5k_ar5212_dump_state(hal)
}
HAL_BOOL
-ar5k_ar5212_get_diag_state(hal, id, device, size)
- struct ath_hal *hal;
- int id;
- void **device;
- u_int *size;
-
+ar5k_ar5212_get_diag_state(struct ath_hal *hal, int id, void **device,
+ u_int *size)
{
/*
* We'll ignore this right now. This seems to be some kind of an obscure
@@ -1887,17 +1793,13 @@ ar5k_ar5212_get_diag_state(hal, id, device, size)
}
void
-ar5k_ar5212_get_lladdr(hal, mac)
- struct ath_hal *hal;
- u_int8_t *mac;
+ar5k_ar5212_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
{
bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
}
HAL_BOOL
-ar5k_ar5212_set_lladdr(hal, mac)
- struct ath_hal *hal;
- const u_int8_t *mac;
+ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
{
u_int32_t low_id, high_id;
@@ -1915,11 +1817,8 @@ ar5k_ar5212_set_lladdr(hal, mac)
}
HAL_BOOL
-ar5k_ar5212_set_regdomain(hal, regdomain, status)
- struct ath_hal *hal;
- u_int16_t regdomain;
- HAL_STATUS *status;
-
+ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
+ HAL_STATUS *status)
{
ieee80211_regdomain_t ieee_regdomain;
@@ -1937,9 +1836,7 @@ ar5k_ar5212_set_regdomain(hal, regdomain, status)
}
void
-ar5k_ar5212_set_ledstate(hal, state)
- struct ath_hal *hal;
- HAL_LED_STATE state;
+ar5k_ar5212_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
{
u_int32_t led;
@@ -1977,11 +1874,8 @@ ar5k_ar5212_set_ledstate(hal, state)
}
void
-ar5k_ar5212_set_associd(hal, bssid, assoc_id, tim_offset)
- struct ath_hal *hal;
- const u_int8_t *bssid;
- u_int16_t assoc_id;
- u_int16_t tim_offset;
+ar5k_ar5212_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
+ u_int16_t assoc_id, u_int16_t tim_offset)
{
u_int32_t low_id, high_id;
@@ -2017,9 +1911,7 @@ ar5k_ar5212_set_associd(hal, bssid, assoc_id, tim_offset)
}
HAL_BOOL
-ar5k_ar5212_set_gpio_output(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5212_NUM_GPIO)
return (AH_FALSE);
@@ -2032,9 +1924,7 @@ ar5k_ar5212_set_gpio_output(hal, gpio)
}
HAL_BOOL
-ar5k_ar5212_set_gpio_input(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5212_NUM_GPIO)
return (AH_FALSE);
@@ -2047,9 +1937,7 @@ ar5k_ar5212_set_gpio_input(hal, gpio)
}
u_int32_t
-ar5k_ar5212_get_gpio(hal, gpio)
- struct ath_hal *hal;
- u_int32_t gpio;
+ar5k_ar5212_get_gpio(struct ath_hal *hal, u_int32_t gpio)
{
if (gpio > AR5K_AR5212_NUM_GPIO)
return (0xffffffff);
@@ -2060,10 +1948,7 @@ ar5k_ar5212_get_gpio(hal, gpio)
}
HAL_BOOL
-ar5k_ar5212_set_gpio(hal, gpio, val)
- struct ath_hal *hal;
- u_int32_t gpio;
- u_int32_t val;
+ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
{
u_int32_t data;
@@ -2082,10 +1967,8 @@ ar5k_ar5212_set_gpio(hal, gpio, val)
}
void
-ar5k_ar5212_set_gpio_intr(hal, gpio, interrupt_level)
- struct ath_hal *hal;
- u_int gpio;
- u_int32_t interrupt_level;
+ar5k_ar5212_set_gpio_intr(struct ath_hal *hal, u_int gpio,
+ u_int32_t interrupt_level)
{
u_int32_t data;
@@ -2110,15 +1993,13 @@ ar5k_ar5212_set_gpio_intr(hal, gpio, interrupt_level)
}
u_int32_t
-ar5k_ar5212_get_tsf32(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_tsf32(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5212_TSF_L32));
}
u_int64_t
-ar5k_ar5212_get_tsf64(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_tsf64(struct ath_hal *hal)
{
u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32);
@@ -2126,23 +2007,20 @@ ar5k_ar5212_get_tsf64(hal)
}
void
-ar5k_ar5212_reset_tsf(hal)
- struct ath_hal *hal;
+ar5k_ar5212_reset_tsf(struct ath_hal *hal)
{
AR5K_REG_ENABLE_BITS(AR5K_AR5212_BEACON,
AR5K_AR5212_BEACON_RESET_TSF);
}
u_int16_t
-ar5k_ar5212_get_regdomain(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_regdomain(struct ath_hal *hal)
{
return (ar5k_get_regdomain(hal));
}
HAL_BOOL
-ar5k_ar5212_detect_card_present(hal)
- struct ath_hal *hal;
+ar5k_ar5212_detect_card_present(struct ath_hal *hal)
{
u_int16_t magic;
@@ -2158,9 +2036,7 @@ ar5k_ar5212_detect_card_present(hal)
}
void
-ar5k_ar5212_update_mib_counters(hal, statistics)
- struct ath_hal *hal;
- HAL_MIB_STATS *statistics;
+ar5k_ar5212_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
{
/* Read-And-Clear */
statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL);
@@ -2177,8 +2053,7 @@ ar5k_ar5212_update_mib_counters(hal, statistics)
}
HAL_RFGAIN
-ar5k_ar5212_get_rf_gain(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_rf_gain(struct ath_hal *hal)
{
u_int32_t data, type;
@@ -2217,9 +2092,7 @@ ar5k_ar5212_get_rf_gain(hal)
}
HAL_BOOL
-ar5k_ar5212_set_slot_time(hal, slot_time)
- struct ath_hal *hal;
- u_int slot_time;
+ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time)
{
if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
return (AH_FALSE);
@@ -2230,16 +2103,13 @@ ar5k_ar5212_set_slot_time(hal, slot_time)
}
u_int
-ar5k_ar5212_get_slot_time(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_slot_time(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff);
}
HAL_BOOL
-ar5k_ar5212_set_ack_timeout(hal, timeout)
- struct ath_hal *hal;
- u_int timeout;
+ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout)
{
if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_ACK),
hal->ah_turbo) <= timeout)
@@ -2252,17 +2122,14 @@ ar5k_ar5212_set_ack_timeout(hal, timeout)
}
u_int
-ar5k_ar5212_get_ack_timeout(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_ack_timeout(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),
AR5K_AR5212_TIME_OUT_ACK), hal->ah_turbo));
}
HAL_BOOL
-ar5k_ar5212_set_cts_timeout(hal, timeout)
- struct ath_hal *hal;
- u_int timeout;
+ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout)
{
if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_CTS),
hal->ah_turbo) <= timeout)
@@ -2275,8 +2142,7 @@ ar5k_ar5212_set_cts_timeout(hal, timeout)
}
u_int
-ar5k_ar5212_get_cts_timeout(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_cts_timeout(struct ath_hal *hal)
{
return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),
AR5K_AR5212_TIME_OUT_CTS), hal->ah_turbo));
@@ -2287,9 +2153,7 @@ ar5k_ar5212_get_cts_timeout(hal)
*/
HAL_BOOL
-ar5k_ar5212_is_cipher_supported(hal, cipher)
- struct ath_hal *hal;
- HAL_CIPHER cipher;
+ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
{
/*
* The AR5212 only supports WEP
@@ -2301,16 +2165,13 @@ ar5k_ar5212_is_cipher_supported(hal, cipher)
}
u_int32_t
-ar5k_ar5212_get_keycache_size(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_keycache_size(struct ath_hal *hal)
{
return (AR5K_AR5212_KEYCACHE_SIZE);
}
HAL_BOOL
-ar5k_ar5212_reset_key(hal, entry)
- struct ath_hal *hal;
- u_int16_t entry;
+ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry)
{
int i;
@@ -2327,9 +2188,7 @@ ar5k_ar5212_reset_key(hal, entry)
}
HAL_BOOL
-ar5k_ar5212_is_key_valid(hal, entry)
- struct ath_hal *hal;
- u_int16_t entry;
+ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry)
{
AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE);
@@ -2344,12 +2203,8 @@ ar5k_ar5212_is_key_valid(hal, entry)
}
HAL_BOOL
-ar5k_ar5212_set_key(hal, entry, keyval, mac, xor_notused)
- struct ath_hal *hal;
- u_int16_t entry;
- const HAL_KEYVAL *keyval;
- const u_int8_t *mac;
- int xor_notused;
+ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry,
+ const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused)
{
int i;
u_int32_t key_v[AR5K_AR5212_KEYCACHE_SIZE - 2];
@@ -2395,10 +2250,8 @@ ar5k_ar5212_set_key(hal, entry, keyval, mac, xor_notused)
}
HAL_BOOL
-ar5k_ar5212_set_key_lladdr(hal, entry, mac)
- struct ath_hal *hal;
- u_int16_t entry;
- const u_int8_t *mac;
+ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
+ const u_int8_t *mac)
{
u_int32_t low_id, high_id;
const u_int8_t *mac_v;
@@ -2426,11 +2279,8 @@ ar5k_ar5212_set_key_lladdr(hal, entry, mac)
*/
HAL_BOOL
-ar5k_ar5212_set_power(hal, mode, set_chip, sleep_duration)
- struct ath_hal *hal;
- HAL_POWER_MODE mode;
- HAL_BOOL set_chip;
- u_int16_t sleep_duration;
+ar5k_ar5212_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
+ HAL_BOOL set_chip, u_int16_t sleep_duration)
{
u_int32_t staid;
int i;
@@ -2495,23 +2345,20 @@ ar5k_ar5212_set_power(hal, mode, set_chip, sleep_duration)
}
HAL_POWER_MODE
-ar5k_ar5212_get_power_mode(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_power_mode(struct ath_hal *hal)
{
return (hal->ah_power_mode);
}
HAL_BOOL
-ar5k_ar5212_query_pspoll_support(hal)
- struct ath_hal *hal;
+ar5k_ar5212_query_pspoll_support(struct ath_hal *hal)
{
/* nope */
return (AH_FALSE);
}
HAL_BOOL
-ar5k_ar5212_init_pspoll(hal)
- struct ath_hal *hal;
+ar5k_ar5212_init_pspoll(struct ath_hal *hal)
{
/*
* Not used on the AR5212
@@ -2520,17 +2367,14 @@ ar5k_ar5212_init_pspoll(hal)
}
HAL_BOOL
-ar5k_ar5212_enable_pspoll(hal, bssid, assoc_id)
- struct ath_hal *hal;
- u_int8_t *bssid;
- u_int16_t assoc_id;
+ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
+ u_int16_t assoc_id)
{
return (AH_FALSE);
}
HAL_BOOL
-ar5k_ar5212_disable_pspoll(hal)
- struct ath_hal *hal;
+ar5k_ar5212_disable_pspoll(struct ath_hal *hal)
{
return (AH_FALSE);
}
@@ -2540,10 +2384,8 @@ ar5k_ar5212_disable_pspoll(hal)
*/
void
-ar5k_ar5212_init_beacon(hal, next_beacon, interval)
- struct ath_hal *hal;
- u_int32_t next_beacon;
- u_int32_t interval;
+ar5k_ar5212_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
+ u_int32_t interval)
{
u_int32_t timer1, timer2, timer3;
@@ -2581,13 +2423,9 @@ ar5k_ar5212_init_beacon(hal, next_beacon, interval)
}
void
-ar5k_ar5212_set_beacon_timers(hal, state, tsf, dtim_count, cfp_count)
- struct ath_hal *hal;
- const HAL_BEACON_STATE *state;
- u_int32_t tsf;
- u_int32_t dtim_count;
- u_int32_t cfp_count;
-
+ar5k_ar5212_set_beacon_timers(struct ath_hal *hal,
+ const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count,
+ u_int32_t cfp_count)
{
u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon;
@@ -2680,8 +2518,7 @@ ar5k_ar5212_set_beacon_timers(hal, state, tsf, dtim_count, cfp_count)
}
void
-ar5k_ar5212_reset_beacon(hal)
- struct ath_hal *hal;
+ar5k_ar5212_reset_beacon(struct ath_hal *hal)
{
/*
* Disable beacon timer
@@ -2697,9 +2534,7 @@ ar5k_ar5212_reset_beacon(hal)
}
HAL_BOOL
-ar5k_ar5212_wait_for_beacon(hal, phys_addr)
- struct ath_hal *hal;
- bus_addr_t phys_addr;
+ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
{
HAL_BOOL ret;
@@ -2721,16 +2556,13 @@ ar5k_ar5212_wait_for_beacon(hal, phys_addr)
*/
HAL_BOOL
-ar5k_ar5212_is_intr_pending(hal)
- struct ath_hal *hal;
+ar5k_ar5212_is_intr_pending(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
}
HAL_BOOL
-ar5k_ar5212_get_isr(hal, interrupt_mask)
- struct ath_hal *hal;
- u_int32_t *interrupt_mask;
+ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
{
u_int32_t data;
@@ -2770,17 +2602,14 @@ ar5k_ar5212_get_isr(hal, interrupt_mask)
}
u_int32_t
-ar5k_ar5212_get_intr(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_intr(struct ath_hal *hal)
{
/* Return the interrupt mask stored previously */
return (hal->ah_imr);
}
HAL_INT
-ar5k_ar5212_set_intr(hal, new_mask)
- struct ath_hal *hal;
- HAL_INT new_mask;
+ar5k_ar5212_set_intr(struct ath_hal *hal, HAL_INT new_mask)
{
HAL_INT old_mask, int_mask;
@@ -2836,8 +2665,7 @@ ar5k_ar5212_set_intr(hal, new_mask)
*/
HAL_BOOL
-ar5k_ar5212_get_capabilities(hal)
- struct ath_hal *hal;
+ar5k_ar5212_get_capabilities(struct ath_hal *hal)
{
u_int16_t ee_header;
@@ -2889,9 +2717,7 @@ ar5k_ar5212_get_capabilities(hal)
}
void
-ar5k_ar5212_radar_alert(hal, enable)
- struct ath_hal *hal;
- HAL_BOOL enable;
+ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
{
/*
* Enable radar detection
@@ -2918,18 +2744,14 @@ ar5k_ar5212_radar_alert(hal, enable)
*/
HAL_BOOL
-ar5k_ar5212_eeprom_is_busy(hal)
- struct ath_hal *hal;
+ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal)
{
return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ?
AH_TRUE : AH_FALSE);
}
int
-ar5k_ar5212_eeprom_read(hal, offset, data)
- struct ath_hal *hal;
- u_int32_t offset;
- u_int16_t *data;
+ar5k_ar5212_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
{
u_int32_t status, i;
@@ -2956,10 +2778,7 @@ ar5k_ar5212_eeprom_read(hal, offset, data)
}
int
-ar5k_ar5212_eeprom_write(hal, offset, data)
- struct ath_hal *hal;
- u_int32_t offset;
- u_int16_t data;
+ar5k_ar5212_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
{
u_int32_t status, timeout;
@@ -2992,10 +2811,7 @@ ar5k_ar5212_eeprom_write(hal, offset, data)
*/
HAL_BOOL
-ar5k_ar5212_txpower(hal, channel, txpower)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
- u_int txpower;
+ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower)
{
HAL_BOOL tpc = hal->ah_txpower.txp_tpc;
int i;
diff --git a/sys/dev/ic/ar5xxx.c b/sys/dev/ic/ar5xxx.c
index 9ad962dee86..c638e0dcf31 100644
--- a/sys/dev/ic/ar5xxx.c
+++ b/sys/dev/ic/ar5xxx.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar5xxx.c,v 1.28 2005/08/17 12:22:49 reyk Exp $ */
+/* $OpenBSD: ar5xxx.c,v 1.29 2005/09/10 14:36:46 jsg Exp $ */
/*
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -121,9 +121,7 @@ static const struct ar5k_ini_rfgain ar5k_rfg[] = AR5K_INI_RFGAIN;
* Perform a lookup if the device is supported by the HAL
*/
const char *
-ath_hal_probe(vendor, device)
- u_int16_t vendor;
- u_int16_t device;
+ath_hal_probe(u_int16_t vendor, u_int16_t device)
{
int i;
@@ -143,12 +141,8 @@ ath_hal_probe(vendor, device)
* Fills in the HAL structure and initialises the device
*/
struct ath_hal *
-ath_hal_attach(device, sc, st, sh, status)
- u_int16_t device;
- void *sc;
- bus_space_tag_t st;
- bus_space_handle_t sh;
- int *status;
+ath_hal_attach(u_int16_t device, void *sc, bus_space_tag_t st,
+ bus_space_handle_t sh, int *status)
{
ieee80211_regdomain_t ieee_regdomain;
u_int16_t regdomain;
@@ -293,12 +287,8 @@ ath_hal_attach(device, sc, st, sh, status)
}
u_int16_t
-ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble)
- struct ath_hal *hal;
- const HAL_RATE_TABLE *rates;
- u_int32_t frame_length;
- u_int16_t rate_index;
- HAL_BOOL short_preamble;
+ath_hal_computetxtime(struct ath_hal *hal, const HAL_RATE_TABLE *rates,
+ u_int32_t frame_length, u_int16_t rate_index, HAL_BOOL short_preamble)
{
const HAL_RATE *rate;
u_int32_t value;
@@ -359,26 +349,19 @@ ath_hal_computetxtime(hal, rates, frame_length, rate_index, short_preamble)
}
u_int
-ath_hal_mhz2ieee(mhz, flags)
- u_int mhz;
- u_int flags;
+ath_hal_mhz2ieee(u_int mhz, u_int flags)
{
return (ieee80211_mhz2ieee(mhz, flags));
}
u_int
-ath_hal_ieee2mhz(ieee, flags)
- u_int ieee;
- u_int flags;
+ath_hal_ieee2mhz(u_int ieee, u_int flags)
{
return (ieee80211_ieee2mhz(ieee, flags));
}
HAL_BOOL
-ar5k_check_channel(hal, freq, flags)
- struct ath_hal *hal;
- u_int16_t freq;
- u_int flags;
+ar5k_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags)
{
/* Check if the channel is in our supported range */
if (flags & IEEE80211_CHAN_2GHZ) {
@@ -395,16 +378,9 @@ ar5k_check_channel(hal, freq, flags)
}
HAL_BOOL
-ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,
- outdoor, extended)
- struct ath_hal *hal;
- HAL_CHANNEL *channels;
- u_int max_channels;
- u_int *channels_size;
- HAL_CTRY_CODE country;
- u_int16_t mode;
- HAL_BOOL outdoor;
- HAL_BOOL extended;
+ath_hal_init_channels(struct ath_hal *hal, HAL_CHANNEL *channels,
+ u_int max_channels, u_int *channels_size, HAL_CTRY_CODE country,
+ u_int16_t mode, HAL_BOOL outdoor, HAL_BOOL extended)
{
u_int i, c;
u_int32_t domain_current;
@@ -536,9 +512,7 @@ ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,
*/
const char *
-ar5k_printver(type, val)
- enum ar5k_srev_type type;
- u_int32_t val;
+ar5k_printver(enum ar5k_srev_type type, u_int32_t val)
{
struct ar5k_srev_name names[] = AR5K_SREV_NAME;
const char *name = "xxxx";
@@ -558,8 +532,7 @@ ar5k_printver(type, val)
}
void
-ar5k_radar_alert(hal)
- struct ath_hal *hal;
+ar5k_radar_alert(struct ath_hal *hal)
{
/*
* Limit ~1/s
@@ -580,8 +553,7 @@ ar5k_radar_alert(hal)
}
u_int16_t
-ar5k_regdomain_from_ieee(ieee)
- ieee80211_regdomain_t ieee;
+ar5k_regdomain_from_ieee(ieee80211_regdomain_t ieee)
{
u_int32_t regdomain = (u_int32_t)ieee;
@@ -592,8 +564,7 @@ ar5k_regdomain_from_ieee(ieee)
}
ieee80211_regdomain_t
-ar5k_regdomain_to_ieee(regdomain)
- u_int16_t regdomain;
+ar5k_regdomain_to_ieee(u_int16_t regdomain)
{
ieee80211_regdomain_t ieee = (ieee80211_regdomain_t)regdomain & 0xff;
@@ -601,8 +572,7 @@ ar5k_regdomain_to_ieee(regdomain)
}
u_int16_t
-ar5k_get_regdomain(hal)
- struct ath_hal *hal;
+ar5k_get_regdomain(struct ath_hal *hal)
{
#ifndef COUNTRYCODE
/*
@@ -632,9 +602,7 @@ ar5k_get_regdomain(hal)
}
u_int32_t
-ar5k_bitswap(val, bits)
- u_int32_t val;
- u_int bits;
+ar5k_bitswap(u_int32_t val, u_int bits)
{
u_int32_t retval = 0, bit, i;
@@ -647,25 +615,19 @@ ar5k_bitswap(val, bits)
}
u_int
-ar5k_htoclock(usec, turbo)
- u_int usec;
- HAL_BOOL turbo;
+ar5k_htoclock(u_int usec, HAL_BOOL turbo)
{
return (turbo == AH_TRUE ? (usec * 80) : (usec * 40));
}
u_int
-ar5k_clocktoh(clock, turbo)
- u_int clock;
- HAL_BOOL turbo;
+ar5k_clocktoh(u_int clock, HAL_BOOL turbo)
{
return (turbo == AH_TRUE ? (clock / 80) : (clock / 40));
}
void
-ar5k_rt_copy(dst, src)
- HAL_RATE_TABLE *dst;
- const HAL_RATE_TABLE *src;
+ar5k_rt_copy(HAL_RATE_TABLE *dst, const HAL_RATE_TABLE *src)
{
bzero(dst, sizeof(HAL_RATE_TABLE));
dst->rateCount = src->rateCount;
@@ -673,12 +635,8 @@ ar5k_rt_copy(dst, src)
}
HAL_BOOL
-ar5k_register_timeout(hal, reg, flag, val, is_set)
- struct ath_hal *hal;
- u_int32_t reg;
- u_int32_t flag;
- u_int32_t val;
- HAL_BOOL is_set;
+ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
+ u_int32_t val, HAL_BOOL is_set)
{
int i;
u_int32_t data;
@@ -703,10 +661,7 @@ ar5k_register_timeout(hal, reg, flag, val, is_set)
*/
u_int16_t
-ar5k_eeprom_bin2freq(hal, bin, mode)
- struct ath_hal *hal;
- u_int16_t bin;
- u_int mode;
+ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode)
{
u_int16_t val;
@@ -731,10 +686,7 @@ ar5k_eeprom_bin2freq(hal, bin, mode)
}
int
-ar5k_eeprom_read_ants(hal, offset, mode)
- struct ath_hal *hal;
- u_int32_t *offset;
- u_int mode;
+ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int32_t o = *offset;
@@ -790,10 +742,7 @@ ar5k_eeprom_read_ants(hal, offset, mode)
}
int
-ar5k_eeprom_read_modes(hal, offset, mode)
- struct ath_hal *hal;
- u_int32_t *offset;
- u_int mode;
+ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int32_t o = *offset;
@@ -874,8 +823,7 @@ ar5k_eeprom_read_modes(hal, offset, mode)
}
int
-ar5k_eeprom_init(hal)
- struct ath_hal *hal;
+ar5k_eeprom_init(struct ath_hal *hal)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
u_int32_t offset;
@@ -1053,9 +1001,7 @@ ar5k_eeprom_init(hal)
}
int
-ar5k_eeprom_read_mac(hal, mac)
- struct ath_hal *hal;
- u_int8_t *mac;
+ar5k_eeprom_read_mac(struct ath_hal *hal, u_int8_t *mac)
{
u_int32_t total, offset;
u_int16_t data;
@@ -1088,10 +1034,8 @@ ar5k_eeprom_read_mac(hal, mac)
}
HAL_BOOL
-ar5k_eeprom_regulation_domain(hal, write, regdomain)
- struct ath_hal *hal;
- HAL_BOOL write;
- ieee80211_regdomain_t *regdomain;
+ar5k_eeprom_regulation_domain(struct ath_hal *hal, HAL_BOOL write,
+ ieee80211_regdomain_t *regdomain)
{
/* Read current value */
if (write != AH_TRUE) {
@@ -1121,9 +1065,7 @@ ar5k_eeprom_regulation_domain(hal, write, regdomain)
*/
HAL_BOOL
-ar5k_channel(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
{
HAL_BOOL ret;
@@ -1162,8 +1104,7 @@ ar5k_channel(hal, channel)
}
u_int32_t
-ar5k_ar5110_chan2athchan(channel)
- HAL_CHANNEL *channel;
+ar5k_ar5110_chan2athchan(HAL_CHANNEL *channel)
{
u_int32_t athchan;
@@ -1181,9 +1122,7 @@ ar5k_ar5110_chan2athchan(channel)
}
HAL_BOOL
-ar5k_ar5110_channel(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5110_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
{
u_int32_t data;
@@ -1199,9 +1138,7 @@ ar5k_ar5110_channel(hal, channel)
}
HAL_BOOL
-ar5k_ar5111_chan2athchan(ieee, athchan)
- u_int ieee;
- struct ar5k_athchan_2ghz *athchan;
+ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan)
{
int channel;
@@ -1227,9 +1164,7 @@ ar5k_ar5111_chan2athchan(ieee, athchan)
}
HAL_BOOL
-ar5k_ar5111_channel(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5111_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
{
u_int ieee_channel, ath_channel;
u_int32_t data0, data1, clock;
@@ -1270,9 +1205,7 @@ ar5k_ar5111_channel(hal, channel)
}
HAL_BOOL
-ar5k_ar5112_channel(hal, channel)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
+ar5k_ar5112_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
{
u_int32_t data, data0, data1, data2;
u_int16_t c;
@@ -1317,10 +1250,8 @@ ar5k_ar5112_channel(hal, channel)
}
u_int
-ar5k_rfregs_op(rf, offset, reg, bits, first, col, set)
- u_int32_t *rf;
- u_int32_t offset, reg, bits, first, col;
- HAL_BOOL set;
+ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits,
+ u_int32_t first, u_int32_t col, HAL_BOOL set)
{
u_int32_t mask, entry, last, data, shift, position;
int32_t left;
@@ -1366,8 +1297,7 @@ ar5k_rfregs_op(rf, offset, reg, bits, first, col, set)
}
u_int32_t
-ar5k_rfregs_gainf_corr(hal)
- struct ath_hal *hal;
+ar5k_rfregs_gainf_corr(struct ath_hal *hal)
{
u_int32_t mix, step;
u_int32_t *rf;
@@ -1403,8 +1333,7 @@ ar5k_rfregs_gainf_corr(hal)
}
HAL_BOOL
-ar5k_rfregs_gain_readback(hal)
- struct ath_hal *hal;
+ar5k_rfregs_gain_readback(struct ath_hal *hal)
{
u_int32_t step, mix, level[4];
u_int32_t *rf;
@@ -1446,8 +1375,7 @@ ar5k_rfregs_gain_readback(hal)
}
int32_t
-ar5k_rfregs_gain_adjust(hal)
- struct ath_hal *hal;
+ar5k_rfregs_gain_adjust(struct ath_hal *hal)
{
int ret = 0;
const struct ar5k_gain_opt *go;
@@ -1504,10 +1432,7 @@ ar5k_rfregs_gain_adjust(hal)
}
HAL_BOOL
-ar5k_rfregs(hal, channel, mode)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
- u_int mode;
+ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
{
ar5k_rfgain_t *func = NULL;
HAL_BOOL ret;
@@ -1539,10 +1464,7 @@ ar5k_rfregs(hal, channel, mode)
}
HAL_BOOL
-ar5k_ar5111_rfregs(hal, channel, mode)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
- u_int mode;
+ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
const u_int rf_size = AR5K_ELEMENTS(ar5111_rf);
@@ -1637,10 +1559,7 @@ ar5k_ar5111_rfregs(hal, channel, mode)
}
HAL_BOOL
-ar5k_ar5112_rfregs(hal, channel, mode)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
- u_int mode;
+ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
{
struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
const u_int rf_size = AR5K_ELEMENTS(ar5112_rf);
@@ -1722,9 +1641,7 @@ ar5k_ar5112_rfregs(hal, channel, mode)
}
HAL_BOOL
-ar5k_rfgain(hal, phy, freq)
- struct ath_hal *hal;
- u_int phy, freq;
+ar5k_rfgain(struct ath_hal *hal, u_int phy, u_int freq)
{
int i;
@@ -1757,10 +1674,7 @@ ar5k_rfgain(hal, phy, freq)
* Common TX power setup
*/
void
-ar5k_txpower_table(hal, channel, max_power)
- struct ath_hal *hal;
- HAL_CHANNEL *channel;
- int16_t max_power;
+ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power)
{
u_int16_t txpower, *rates;
int i;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 08:49:55 +0000