cosmetic changes, fix regdomain code and beacon handling

3 files changed, 119 insertions, 106 deletions

diff --git a/sys/dev/ic/ar5210.c b/sys/dev/ic/ar5210.c
index c688f66d449..4d0cce7e094 100644
--- a/sys/dev/ic/ar5210.c
+++ b/sys/dev/ic/ar5210.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5210.c,v 1.10 2005/02/16 01:31:25 reyk Exp $	*/
+/*     $OpenBSD: ar5210.c,v 1.11 2005/02/17 22:32:48 reyk Exp $        */
 
 /*
  * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
@@ -444,7 +444,7 @@ ar5k_ar5210_reset(hal, op_mode, channel, change_channel, status)
 		}
 	}
 
-	AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON,
+	AR5K_REG_DISABLE_BITS(AR5K_AR5210_BEACON,
 	    AR5K_AR5210_BEACON_EN | AR5K_AR5210_BEACON_RESET_TSF);
 
 	return (AH_TRUE);
@@ -506,7 +506,7 @@ ar5k_ar5210_perCalibration(hal, channel)
 	HAL_CHANNEL *channel;
 {
 	HAL_BOOL ret = AH_TRUE;
-	u_int32_t phy_sig, phy_agc, phy_sat;
+	u_int32_t phy_sig, phy_agc, phy_sat, beacon;
 
 #define AGC_DISABLE	{						\
         AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGC,			\
@@ -524,7 +524,8 @@ ar5k_ar5210_perCalibration(hal, channel)
 	 */
 	AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW,
 	    AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX);
-	AR5K_REG_DISABLE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_EN);
+	beacon = AR5K_REG_READ(AR5K_AR5210_BEACON);
+	AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon & ~AR5K_AR5210_BEACON_EN);
 
 	AR5K_DELAY(2300);
 
@@ -597,7 +598,7 @@ ar5k_ar5210_perCalibration(hal, channel)
 	 */
 	AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW,
 	    AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX);
-	AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_EN);
+	AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon);
 
 #undef AGC_ENABLE
 #undef AGC_DISABLE
@@ -1551,8 +1552,12 @@ ar5k_ar5210_setRegulatoryDomain(hal, regdomain, status)
 	HAL_STATUS *status;
 
 {
+	ieee80211_regdomain_t ieee_regdomain;
+
+	ieee_regdomain = ar5k_regdomain_to_ieee(regdomain);
+
 	if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
-		ar5k_regdomain_to_ieee(regdomain)) == AH_TRUE) {
+		&ieee_regdomain) == AH_TRUE) {
 		*status = HAL_OK;
 		return (AH_TRUE);
 	}
@@ -1609,22 +1614,18 @@ ar5k_ar5210_writeAssocid(hal, bssid, assoc_id, tim_offset)
 	 */
 	memcpy(&low_id, bssid, 4);
 	memcpy(&high_id, bssid + 4, 2);
+	memcpy(&hal->ah_bssid, bssid, IEEE80211_ADDR_LEN);
 	AR5K_REG_WRITE(AR5K_AR5210_BSS_ID0, htole32(low_id));
 	AR5K_REG_WRITE(AR5K_AR5210_BSS_ID1, htole32(high_id) |
 	    ((assoc_id & 0x3fff) << AR5K_AR5210_BSS_ID1_AID_S));
-	memcpy(&hal->ah_bssid, bssid, IEEE80211_ADDR_LEN);
 
 	if (assoc_id == 0) {
 		ar5k_ar5210_disablePSPoll(hal);
 		return;
 	}
 
-	AR5K_REG_WRITE(AR5K_AR5210_BEACON,
-	    (AR5K_REG_READ(AR5K_AR5210_BEACON) &
-		~AR5K_AR5210_BEACON_TIM) |
-	    (((tim_offset ? tim_offset + 4 : 0) <<
-		AR5K_AR5210_BEACON_TIM_S) &
-		AR5K_AR5210_BEACON_TIM));
+	AR5K_REG_WRITE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_TIM,
+	    tim_offset ? tim_offset + 4 : 0);
 
 	ar5k_ar5210_enablePSPoll(hal, NULL, 0);
 }
@@ -1749,16 +1750,7 @@ u_int16_t
 ar5k_ar5210_getRegDomain(hal)
 	struct ath_hal *hal;
 {
-	u_int16_t regdomain;
-	ieee80211_regdomain_t ieee_regdomain;
-
-	if (ar5k_eeprom_regulation_domain(hal,
-		AH_FALSE, ieee_regdomain) == AH_TRUE) {
-		regdomain = ar5k_regdomain_from_ieee(ieee_regdomain);
-		return (regdomain > 0 ? regdomain : hal->ah_regdomain);
-	}
-
-	return (0);
+	return (ar5k_get_regdomain(hal));
 }
 
 HAL_BOOL
@@ -2158,11 +2150,10 @@ ar5k_ar5210_beaconInit(hal, next_beacon, interval)
 		break;
 
 	default:
-		timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) <<
-		    0x00000003;
-		timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) <<
-		    0x00000003;
+		timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
+		timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
 		timer3 = next_beacon + hal->ah_atim_window;
+		break;
 	}
 
 	/*
@@ -2230,15 +2221,14 @@ ar5k_ar5210_setStationBeaconTimers(hal, state, tsf, dtim_count, cfp_count)
 	    (AR5K_REG_READ(AR5K_AR5210_BEACON) &~
 		(AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_TIM)) |
 	    AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
-		AR5K_AR5210_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
-		    AR5K_AR5210_BEACON_PERIOD));
+		AR5K_AR5210_BEACON_TIM) |
+	    AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD));
 
 	/*
 	 * Write new beacon miss threshold, if it appears to be valid
 	 */
-	if ((state->bs_bmiss_threshold > (AR5K_AR5210_RSSI_THR_BM_THR >>
-		 AR5K_AR5210_RSSI_THR_BM_THR_S)) &&
-	    (state->bs_bmiss_threshold & 0x00007) != 0)
+	if (state->bs_bmiss_threshold <=
+	    (AR5K_AR5210_RSSI_THR_BM_THR >> AR5K_AR5210_RSSI_THR_BM_THR_S))
 		AR5K_REG_WRITE_BITS(AR5K_AR5210_RSSI_THR,
 		    AR5K_AR5210_RSSI_THR_BM_THR, state->bs_bmiss_threshold);
 }
@@ -2383,7 +2373,8 @@ ar5k_ar5210_setInterrupts(hal, new_mask)
 	hal->ah_imr = new_mask;
 
 	/* ..re-enable interrupts */
-	AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE);
+	if (int_mask)
+		AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE);
 
 	return (old_mask);
 }
diff --git a/sys/dev/ic/ar5xxx.c b/sys/dev/ic/ar5xxx.c
index be3bd2b21f1..b68c24fead7 100644
--- a/sys/dev/ic/ar5xxx.c
+++ b/sys/dev/ic/ar5xxx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5xxx.c,v 1.9 2005/02/03 03:21:37 kevlo Exp $	*/
+/*	$OpenBSD: ar5xxx.c,v 1.10 2005/02/17 22:32:48 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
@@ -197,7 +197,6 @@ ath_hal_attach(device, sc, st, sh, status)
 	hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
 	hal->ah_turbo = AH_FALSE;
 	hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
-	hal->ah_txpower.txp_max = AR5K_TUNE_MAX_TXPOWER;
 	hal->ah_imr = 0;
 	hal->ah_atim_window = 0;
 	hal->ah_aifs = AR5K_TUNE_AIFS;
@@ -228,7 +227,7 @@ ath_hal_attach(device, sc, st, sh, status)
 		    hal->ah_capabilities.cap_regdomain.reg_current;
 
 		/* Try to write default regulation domain to EEPROM */
- 		ar5k_eeprom_regulation_domain(hal, AH_TRUE, ieee_regdomain);
+ 		ar5k_eeprom_regulation_domain(hal, AH_TRUE, &ieee_regdomain);
 	}
 
 	hal->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
@@ -478,7 +477,7 @@ ar5k_regdomain_from_ieee(ieee)
 	u_int32_t regdomain = (u_int32_t)ieee;
 
 	if (regdomain & 0xf0000000)
-		return ((u_int16_t)DMN_DEFAULT);
+		return ((u_int16_t)AR5K_TUNE_REGDOMAIN);
 
         return (regdomain & 0xff);
 }
@@ -492,6 +491,37 @@ ar5k_regdomain_to_ieee(regdomain)
 	return (ieee);
 }
 
+u_int16_t
+ar5k_get_regdomain(hal)
+	struct ath_hal *hal;
+{
+#ifndef COUNTRYCODE
+	/*
+	 * Use the regulation domain found in the EEPROM, if not
+	 * forced by a static country code.
+	 */
+	u_int16_t regdomain;
+	ieee80211_regdomain_t ieee_regdomain;
+
+	if (ar5k_eeprom_regulation_domain(hal,
+		AH_FALSE, &ieee_regdomain) == AH_TRUE) {
+		if ((regdomain = ar5k_regdomain_from_ieee(ieee_regdomain)))
+			return (regdomain);
+	}
+
+	return (hal->ah_regdomain);
+#else
+	/*
+	 * Get the regulation domain by country code. This will ignore
+	 * the settings found in the EEPROM.
+	 */
+	u_int16_t code;
+	
+	code = ieee80211_name2countrycode(COUNTRYCODE);
+	return (ieee80211_countrycode2regdomain(code));
+#endif
+}
+
 u_int32_t
 ar5k_bitswap(val, bits)
 	u_int32_t val;
@@ -591,18 +621,6 @@ ar5k_eeprom_bin2freq(hal, bin, mode)
 	return (val);
 }
 
-#define EEPROM_READ_VAL(_o, _v)	{					\
-	if ((ret = hal->ah_eeprom_read(hal, (_o),			\
-		 &(_v))) != 0)						\
-		return (ret);						\
-}			
-
-#define EEPROM_READ_HDR(_o, _v)	{					\
-	if ((ret = hal->ah_eeprom_read(hal, (_o),			\
-		 &hal->ah_capabilities.cap_eeprom._v)) != 0)		\
-		return (ret);						\
-}
-
 int
 ar5k_eeprom_read_ants(hal, offset, mode)
 	struct ath_hal *hal;
@@ -614,28 +632,28 @@ ar5k_eeprom_read_ants(hal, offset, mode)
 	u_int16_t val;
 	int ret, i = 0;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_switch_settling[mode]	= (val >> 8) & 0x7f;
 	ee->ee_ant_tx_rx[mode]		= (val >> 2) & 0x3f;
 	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
 	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
 	ee->ee_ant_control[mode][i++]	= val & 0x3f;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_ant_control[mode][i++]	= (val >> 10) & 0x3f;
 	ee->ee_ant_control[mode][i++]	= (val >> 4) & 0x3f;
 	ee->ee_ant_control[mode][i]	= (val << 2) & 0x3f;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_ant_control[mode][i++]	|= (val >> 14) & 0x3;
 	ee->ee_ant_control[mode][i++]	= (val >> 8) & 0x3f;
 	ee->ee_ant_control[mode][i++]	= (val >> 2) & 0x3f;
 	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
 	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
 	ee->ee_ant_control[mode][i++]	= val & 0x3f;
@@ -673,7 +691,7 @@ ar5k_eeprom_read_modes(hal, offset, mode)
 	u_int16_t val;
 	int ret;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_tx_end2xlna_enable[mode]	= (val >> 8) & 0xff;
 	ee->ee_thr_62[mode]		= val & 0xff;
 
@@ -681,11 +699,11 @@ ar5k_eeprom_read_modes(hal, offset, mode)
 		ee->ee_thr_62[mode] =
 		    mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_tx_end2xpa_disable[mode]	= (val >> 8) & 0xff;
 	ee->ee_tx_frm2xpa_enable[mode]	= val & 0xff;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_pga_desired_size[mode]	= (val >> 8) & 0xff;
 
 	if ((val & 0xff) & 0x80)
@@ -697,7 +715,7 @@ ar5k_eeprom_read_modes(hal, offset, mode)
 		ee->ee_noise_floor_thr[mode] =
 		    mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
 
-	EEPROM_READ_VAL(o++, val);
+	AR5K_EEPROM_READ(o++, val);
 	ee->ee_xlna_gain[mode]		= (val >> 5) & 0xff;
 	ee->ee_x_gain[mode]		= (val >> 1) & 0xf;
 	ee->ee_xpd[mode]		= val & 0x1;
@@ -706,7 +724,7 @@ ar5k_eeprom_read_modes(hal, offset, mode)
 		ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
-		EEPROM_READ_VAL(o++, val);
+		AR5K_EEPROM_READ(o++, val);
 		ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
 
 		if (mode == AR5K_EEPROM_MODE_11A)
@@ -723,7 +741,7 @@ ar5k_eeprom_read_modes(hal, offset, mode)
 	} else {
 		ee->ee_i_gain[mode] = (val >> 13) & 0x7;
 		
-		EEPROM_READ_VAL(o++, val);
+		AR5K_EEPROM_READ(o++, val);
 		ee->ee_i_gain[mode] |= (val << 3) & 0x38;
 
 		if (mode == AR5K_EEPROM_MODE_11G)
@@ -768,29 +786,29 @@ ar5k_eeprom_init(hal)
 	/*
 	 * Read values from EEPROM and store them in the capability structure
 	 */
-	EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
-	EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
-	EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
-	EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
-	EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
 
 	/* Return if we have an old EEPROM */
 	if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
 		return (0);
 
-	EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), ee_ant_gain);
+	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version), ee_ant_gain);
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
-		EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
-		EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
+		AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
+		AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
 	}
 
 	if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
-		EEPROM_READ_VAL(AR5K_EEPROM_OBDB0_2GHZ, val);
+		AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
 		ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
 		ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
 
-		EEPROM_READ_VAL(AR5K_EEPROM_OBDB1_2GHZ, val);
+		AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
 		ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
 		ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
 	}
@@ -802,7 +820,7 @@ ar5k_eeprom_init(hal)
 	ee->ee_ctls = AR5K_EEPROM_N_CTLS(hal->ah_ee_version);
 
 	for (i = 0; i < ee->ee_ctls; i++) {
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_ctl[i] = (val >> 8) & 0xff;
 		ee->ee_ctl[i + 1] = val & 0xff;
 	}
@@ -820,13 +838,13 @@ ar5k_eeprom_init(hal)
 	if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
 		return (ret);
 
-	EEPROM_READ_VAL(offset++, val);
+	AR5K_EEPROM_READ(offset++, val);
 	ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
 	ee->ee_ob[mode][3]		= (val >> 5) & 0x7;
 	ee->ee_db[mode][3]		= (val >> 2) & 0x7;
 	ee->ee_ob[mode][2]		= (val << 1) & 0x7;
 
-	EEPROM_READ_VAL(offset++, val);
+	AR5K_EEPROM_READ(offset++, val);
 	ee->ee_ob[mode][2]		|= (val >> 15) & 0x1;
 	ee->ee_db[mode][2]		= (val >> 12) & 0x7;
 	ee->ee_ob[mode][1]		= (val >> 9) & 0x7;
@@ -838,7 +856,7 @@ ar5k_eeprom_init(hal)
 		return (ret);
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_margin_tx_rx[mode] = val & 0x3f;
 	}
 
@@ -851,7 +869,7 @@ ar5k_eeprom_init(hal)
 	if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
 		return (ret);
 
-	EEPROM_READ_VAL(offset++, val);
+	AR5K_EEPROM_READ(offset++, val);
 	ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
 	ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
 	ee->ee_db[mode][1]		= val & 0x7;
@@ -860,13 +878,13 @@ ar5k_eeprom_init(hal)
 		return (ret);
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][0] =
 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
 		ee->ee_cal_pier[mode][1] =
 		    ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
 
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][2] =
 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
 	}
@@ -884,7 +902,7 @@ ar5k_eeprom_init(hal)
 	if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
 		return (ret);
 
-	EEPROM_READ_VAL(offset++, val);
+	AR5K_EEPROM_READ(offset++, val);
 	ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
 	ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
 	ee->ee_db[mode][1]		= val & 0x7;
@@ -893,17 +911,17 @@ ar5k_eeprom_init(hal)
 		return (ret);
 
 	if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][0] =
 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
 		ee->ee_cal_pier[mode][1] =
 		    ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
 
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_turbo_max_power[mode] = val & 0x7f;
 		ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
 
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_cal_pier[mode][2] =
 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
 
@@ -911,12 +929,12 @@ ar5k_eeprom_init(hal)
 			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 		}
 
-		EEPROM_READ_VAL(offset++, val);
+		AR5K_EEPROM_READ(offset++, val);
 		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
 		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 
 		if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
-			EEPROM_READ_VAL(offset++, val);
+			AR5K_EEPROM_READ(offset++, val);
 			ee->ee_cck_ofdm_gain_delta = val & 0xff;
 		}
 	}
@@ -928,9 +946,6 @@ ar5k_eeprom_init(hal)
 	return (0);
 }
 
-#undef EEPROM_READ_VAL
-#undef EEPROM_READ_HDR
-
 int
 ar5k_eeprom_read_mac(hal, mac)
 	struct ath_hal *hal;
@@ -973,28 +988,28 @@ HAL_BOOL
 ar5k_eeprom_regulation_domain(hal, write, regdomain)
 	struct ath_hal *hal;
 	HAL_BOOL write;
-	ieee80211_regdomain_t regdomain;
+	ieee80211_regdomain_t *regdomain;
 {
 	/* Read current value */
 	if (write != AH_TRUE) {
-		regdomain = hal->ah_capabilities.cap_regdomain.reg_current;
+		*regdomain = hal->ah_capabilities.cap_regdomain.reg_current;
 		return (AH_TRUE);
 	}
 
 	/* Try to write a new value */
-	hal->ah_capabilities.cap_regdomain.reg_current = regdomain;
+	hal->ah_capabilities.cap_regdomain.reg_current = *regdomain;
 
 	if (hal->ah_capabilities.cap_eeprom.ee_protect &
 	    AR5K_EEPROM_PROTECT_WR_128_191)
 		return (AH_FALSE);
 
-	hal->ah_capabilities.cap_eeprom.ee_regdomain =
-	    ar5k_regdomain_from_ieee(regdomain);
-
 	if (hal->ah_eeprom_write(hal, AR5K_EEPROM_REG_DOMAIN,
 		hal->ah_capabilities.cap_eeprom.ee_regdomain) != 0) 
 		return (AH_FALSE);
 
+	hal->ah_capabilities.cap_eeprom.ee_regdomain =
+	    ar5k_regdomain_from_ieee(*regdomain);
+
 	return (AH_TRUE);
 }
 
@@ -1026,13 +1041,12 @@ ar5k_channel(hal, channel)
 	/*
 	 * Set the channel and wait
 	 */
-	if (hal->ah_radio == AR5K_AR5110) {
+	if (hal->ah_radio == AR5K_AR5110)
 		ret = ar5k_ar5110_channel(hal, channel);
-	} else if (hal->ah_radio == AR5K_AR5111) {
+	else if (hal->ah_radio == AR5K_AR5111)
 		ret = ar5k_ar5111_channel(hal, channel);
-	} else {
+	else
 		ret = ar5k_ar5112_channel(hal, channel);
-	}
 
 	if (ret == AH_FALSE)
 		return (ret);
@@ -1119,8 +1133,6 @@ ar5k_ar5111_channel(hal, channel)
 	u_int32_t data0, data1, clock;
 	struct ar5k_athchan_2ghz ath_channel_2ghz;
 	
-	AR5K_TRACE;
-
 	/*
 	 * Set the channel on the AR5111 radio
 	 */
@@ -1163,8 +1175,6 @@ ar5k_ar5112_channel(hal, channel)
 	u_int32_t data, data0, data1, data2;
 	u_int16_t c;
 	
-	AR5K_TRACE;
-
 	c = channel->c_channel;
 
 	/*
diff --git a/sys/dev/ic/ar5xxx.h b/sys/dev/ic/ar5xxx.h
index 0d44b4e9b4f..06c1ecbaa0b 100644
--- a/sys/dev/ic/ar5xxx.h
+++ b/sys/dev/ic/ar5xxx.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5xxx.h,v 1.8 2005/01/09 18:18:15 reyk Exp $	*/
+/*	$OpenBSD: ar5xxx.h,v 1.9 2005/02/17 22:32:48 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004 Reyk Floeter <reyk@vantronix.net>.
@@ -565,7 +565,7 @@ typedef enum ieee80211_state HAL_LED_STATE;
         (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
 
 #define AR5K_EEPROM_ANT_GAIN(_v)	AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
-#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)	((int8_t)(((_v) >> 8) >> 0xff))
+#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)	((int8_t)(((_v) >> 8) & 0xff))
 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)	((int8_t)((_v) & 0xff))
 
 #define AR5K_EEPROM_MODES_11A(_v)	AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
@@ -722,11 +722,12 @@ typedef struct {
  */
 
 #define AR5K_TXPOWER_OFDM(_r, _v)	(				\
-        ((0 & 1) << ((_v) + 6)) | (((_r) & 0x3f) << (_v))		\
+        ((0 & 1) << ((_v) + 6)) | 					\
+        (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v))		\
 )
 
 #define AR5K_TXPOWER_CCK(_r, _v)	(				\
-        ((_r) & 0x3f) << (_v)						\
+        (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v)		\
 )
 
 /*
@@ -1041,7 +1042,7 @@ struct ath_hal {
 	struct {
 		u_int16_t	txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
 		u_int16_t	txp_rates[AR5K_MAX_RATES];
-		u_int		txp_max;
+		int16_t		txp_min, txp_max;
 		HAL_BOOL	txp_tpc;
 	} ah_txpower;
 
@@ -1131,6 +1132,7 @@ typedef struct ath_hal*(ar5k_attach_t)
 
 /* Default regulation domain if stored value EEPROM value is invalid */
 #define AR5K_TUNE_REGDOMAIN	DMN_FCC1_FCCA
+#define AR5K_TUNE_CTRY		CTRY_DEFAULT
 
 /*
  * Common initial register values
@@ -1216,6 +1218,14 @@ typedef struct ath_hal*(ar5k_attach_t)
 #define AR5K_PHY_READ(_reg)						\
         AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
 
+#define AR5K_EEPROM_READ(_o, _v)	{				\
+	if ((ret = hal->ah_eeprom_read(hal, (_o),			\
+		 &(_v))) != 0)						\
+		return (ret);						\
+}			
+#define AR5K_EEPROM_READ_HDR(_o, _v)					\
+        AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v);	\
+
 /* Read status of selected queue */
 #define AR5K_REG_READ_Q(_reg, _queue)					\
 	(AR5K_REG_READ(_reg) & (1 << _queue))				\
@@ -1410,6 +1420,8 @@ HAL_BOOL		 ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *,
 void			 ar5k_radar_alert(struct ath_hal *);
 ieee80211_regdomain_t	 ar5k_regdomain_to_ieee(u_int16_t);
 u_int16_t		 ar5k_regdomain_from_ieee(ieee80211_regdomain_t);
+u_int16_t		 ar5k_get_regdomain(struct ath_hal *);
+
 u_int32_t		 ar5k_bitswap(u_int32_t, u_int);
 u_int			 ar5k_clocktoh(u_int, HAL_BOOL);
 u_int			 ar5k_htoclock(u_int, HAL_BOOL);
@@ -1421,7 +1433,7 @@ HAL_BOOL		 ar5k_register_timeout(struct ath_hal *, u_int32_t,
 int			 ar5k_eeprom_init(struct ath_hal *);
 int			 ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *);
 HAL_BOOL		 ar5k_eeprom_regulation_domain(struct ath_hal *,
-    HAL_BOOL, ieee80211_regdomain_t);
+    HAL_BOOL, ieee80211_regdomain_t *);
 
 HAL_BOOL		 ar5k_channel(struct ath_hal *, HAL_CHANNEL *);
 HAL_BOOL		 ar5k_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);