remove some unused includes

7 files changed, 0 insertions, 832 deletions

diff --git a/sys/dev/ic/dc503reg.h b/sys/dev/ic/dc503reg.h
deleted file mode 100644
index 26ed195f50c..00000000000
--- a/sys/dev/ic/dc503reg.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*	$OpenBSD: dc503reg.h,v 1.1 2006/07/23 19:17:23 miod Exp $	*/
-/*	$NetBSD: pmreg.h,v 1.7 2005/12/11 12:18:36 christos Exp $	*/
-
-/*
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * Ralph Campbell.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)pmreg.h	8.1 (Berkeley) 6/10/93
- */
-
-/*
- * Layout of the programmable cursor chip (DC503) registers.
- * All registers are 16 bit wide.
- */
-
-#define	PCC_CMD		0x00	/* cursor command register */
-#define	PCCCMD_TEST	0x8000
-#define	PCCCMD_HSHI	0x4000
-#define	PCCCMD_VBHI	0x2000
-#define	PCCCMD_LODSA	0x1000
-#define	PCCCMD_FORG2	0x0800
-#define	PCCCMD_ENRG2	0x0400
-#define	PCCCMD_FORG1	0x0200
-#define	PCCCMD_ENRG1	0x0100
-#define	PCCCMD_XHWID	0x0080
-#define	PCCCMD_XHCL1	0x0040
-#define	PCCCMD_XHCLP	0x0020
-#define	PCCCMD_XHAIR	0x0010
-#define	PCCCMD_FOPB	0x0008
-#define	PCCCMD_ENPB	0x0004
-#define	PCCCMD_FOPA	0x0002
-#define	PCCCMD_ENPA	0x0001
-
-#define	PCC_XPOS	0x04	/* cursor X position */
-#define	PCC_YPOS	0x08	/* cursor Y position */
-#define	PCC_XMIN_1	0x0c	/* region 1 left edge */
-#define	PCC_XMAX_1	0x10	/* region 1 right edge */
-#define	PCC_YMIN_1	0x14	/* region 1 top edge */
-#define	PCC_YMAX_1	0x18	/* region 1 bottom edge */
-#define	PCC_XMIN_2	0x1c	/* region 2 left edge */
-#define	PCC_XMAX_2	0x20	/* region 2 right edge */
-#define	PCC_YMIN_2	0x24	/* region 2 top edge */
-#define	PCC_YMAX_2	0x28	/* region 2 bottom edge */
-#define	PCC_LOAD	0x2c	/* cursor pattern load */
-
-struct dc503reg {
-	volatile u_int16_t	cmdr;
-	int16_t	pad1;
-	volatile u_int16_t	xpos;
-	int16_t	pad2;
-	volatile u_int16_t	ypos;
-	int16_t	pad3;
-	volatile u_int16_t	xmin1;
-	int16_t	pad4;
-	volatile u_int16_t	xmax1;
-	int16_t	pad5;
-	volatile u_int16_t	ymin1;
-	int16_t	pad6;
-	volatile u_int16_t	ymax1;
-	int16_t	pad7[9];
-	volatile u_int16_t	xmin2;
-	int16_t	pad8;
-	volatile u_int16_t	xmax2;
-	int16_t	pad9;
-	volatile u_int16_t	ymin2;
-	int16_t	pad10;
-	volatile u_int16_t	ymax2;
-	int16_t	pad11;
-	volatile u_int16_t	load;
-};
-
-#define	PCC_CURSOR_SIZE	16
diff --git a/sys/dev/ic/espreg.h b/sys/dev/ic/espreg.h
deleted file mode 100644
index 618a60ea7b4..00000000000
--- a/sys/dev/ic/espreg.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*	$OpenBSD: espreg.h,v 1.2 1996/10/31 01:01:30 niklas Exp $	*/
-
-/*-
- * Copyright (c) 1995  Sean E. Fagin, John M Vinopal.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the author nor the names of contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _ESPREG_H_
-#define	_ESPREG_H_
-
-/*
- * Definitions for Hayes ESP serial cards.
- */
-
-/*
- * CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
- */
-#define	ESP_CMD1	4
-#define	ESP_CMD2	5
-
-/*
- * STAT1 and STAT2 are to get return values and status bytes
- */
-#define	ESP_STATUS1	ESP_CMD1
-#define	ESP_STATUS2	ESP_CMD2
-
-/*
- * Commands.  Commands are given by writing the command value to
- * ESP_CMD1 and then writing or reading some number of bytes from
- * ESP_CMD2 or ESP_STATUS2.
- */
-#define	ESP_GETTEST	0x01	/* self-test command (1 byte + extras) */
-#define	ESP_GETDIPS	0x02	/* get on-board DIP switches (1 byte) */
-#define	ESP_SETFLOWTYPE	0x08	/* set type of flow-control (2 bytes) */
-#define	ESP_SETRXFLOW	0x0a	/* set Rx FIFO flow control levels (4 bytes) */
-#define	ESP_SETMODE	0x10	/* set board mode (1 byte) */
-
-/* Mode bits (ESP_SETMODE). */
-#define	ESP_MODE_FIFO	0x02	/* act like a 16550 (compatibility mode) */
-#define	ESP_MODE_RTS	0x04	/* use RTS hardware flow control */
-#define	ESP_MODE_SCALE	0x80	/* scale FIFO trigger levels */
-
-/* Flow control type bits (ESP_SETFLOWTYPE). */
-#define	ESP_FLOW_RTS	0x04	/* cmd1: local Rx sends RTS flow control */
-#define	ESP_FLOW_CTS	0x10	/* cmd2: local transmitter responds to CTS */
-
-/* Used by ESP_SETRXFLOW. */
-#define	RXHIGHWATER	768
-#define	RXLOWWATER	512
-#define	HIBYTE(w)	(((w) >> 8) & 0xff)
-#define	LOBYTE(w)	((w) & 0xff)
-
-#endif /* !_ESPREG_H_ */
diff --git a/sys/dev/ic/hayespreg.h b/sys/dev/ic/hayespreg.h
deleted file mode 100644
index 118304fda97..00000000000
--- a/sys/dev/ic/hayespreg.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*	$OpenBSD: hayespreg.h,v 1.2 1996/10/31 01:01:30 niklas Exp $	*/
-/*	$NetBSD: hayespreg.h,v 1.1 1996/02/10 20:23:40 christos Exp $	*/
-
-/*-
- * Copyright (c) 1995  Sean E. Fagin, John M Vinopal.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the author nor the names of contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _HAYESPREG_H_
-#define	_HAYESPREG_H_
-
-/*
- * Definitions for Hayes ESP serial cards.
- */
-
-/*
- * CMD1 and CMD2 are the command ports, offsets from <hayesp_iobase>.
- */
-#define	HAYESP_CMD1	4
-#define	HAYESP_CMD2	5
-
-/*
- * STAT1 and STAT2 are to get return values and status bytes
- */
-#define	HAYESP_STATUS1	HAYESP_CMD1
-#define	HAYESP_STATUS2	HAYESP_CMD2
-
-/*
- * Commands.  Commands are given by writing the command value to
- * HAYESP_CMD1 and then writing or reading some number of bytes from
- * HAYESP_CMD2 or HAYESP_STATUS2.
- */
-#define	HAYESP_GETTEST		0x01	/* self-test command (1b+extras) */
-#define	HAYESP_GETDIPS		0x02	/* get on-board DIP switches (1b) */
-#define	HAYESP_SETFLOWTYPE	0x08	/* set type of flow-control (2b) */
-#define	HAYESP_SETRXFLOW	0x0a	/* set Rx FIFO " levels (4b) */
-#define	HAYESP_SETMODE		0x10	/* set board mode (1b) */
-
-/* Mode bits (HAYESP_SETMODE). */
-#define	HAYESP_MODE_FIFO	0x02	/* act like a 16550 (compat mode) */
-#define	HAYESP_MODE_RTS		0x04	/* use RTS hardware flow control */
-#define	HAYESP_MODE_SCALE	0x80	/* scale FIFO trigger levels */
-
-/* Flow control type bits (HAYESP_SETFLOWTYPE). */
-#define	HAYESP_FLOW_RTS	0x04	/* cmd1: local Rx sends RTS flow control */
-#define	HAYESP_FLOW_CTS	0x10	/* cmd2: local transmitter responds to CTS */
-
-/* Used by HAYESP_SETRXFLOW. */
-#define	HAYESP_RXHIWMARK	768
-#define	HAYESP_RXLOWMARK	512
-#define	HAYESP_HIBYTE(w)	(((w) >> 8) & 0xff)
-#define	HAYESP_LOBYTE(w)	((w) & 0xff)
-
-#endif /* !_HAYESPREG_H_ */
diff --git a/sys/dev/ic/i82595reg.h b/sys/dev/ic/i82595reg.h
deleted file mode 100644
index 2898af9bd76..00000000000
--- a/sys/dev/ic/i82595reg.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*	$OpenBSD: i82595reg.h,v 1.3 2003/10/21 18:58:49 jmc Exp $	*/
-/*	$NetBSD: i82595reg.h,v 1.1 1996/05/06 21:36:51 is Exp $	*/
-
-/*
- * Copyright (c) 1996, Ignatios Souvatzis.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Ignatios Souvatzis
- *	for the NetBSD project.
- * 4. The name of the author may not be used to endorse or promote products 
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Intel 82595 Ethernet chip register, bit, and structure definitions.
- *
- * Written by is with reference to Intel's i82595FX data sheet, with some 
- * clarification coming from looking at the Clarkson Packet Driver code for this
- * chip written by Russ Nelson and others;
- *
- * and
- *
- * configuration EEPROM layout. Written with reference to Intels
- * public "LAN595 Hardware and Software Specifications" document.
- */
-
-/* registers */
-
-/* bank0 */
-
-#define COMMAND_REG 0	/* available in any bank */
-
-#define		MC_SETUP_CMD	0x03
-#define		XMT_CMD		0x04
-#define		TDR_CMD		0x05
-#define		DUMP_CMD	0x06
-#define		DIAG_CMD	0x07
-#define		RCV_ENABLE_CMD	0x08
-#define		RCV_DISABLE_CMD	0x0a
-#define		RCV_STOP_CMD	0x0b
-#define		RESET_CMD	0x0e
-#define		TRISTATE_CMD	0x16
-#define		NO_TRISTATE_CMD	0x17
-#define		POWER_DOWN_CMD	0x18
-#define		SLEEP_MODE_CMD	0x19
-#define		NEGOTIATE_CMD	0x1a
-#define		RESUME_XMT_CMD	0x1c
-#define		SEL_RESET_CMD	0x1e
-#define		BANK_SEL(n)	(n<<6)	/* 0, 1, 2 */
-
-#define STATUS_REG 1
-
-#define		RX_STP_INT	0x01
-#define		RX_INT		0x02
-#define		TX_INT		0x04
-#define		EXEC_INT	0x08
-#define		EXEC_STATUS	0x30
-
-#define ID_REG 2
-
-#define		ID_REG_MASK	0x2c
-#define		ID_REG_SIG	0x24
-#define		R_ROBIN_BITS	0xc0
-#define		R_ROBIN_SHIFT	6
-#define		AUTO_ENABLE	0x10
-
-#define INT_MASK_REG 3
-
-#define		RX_STOP_BIT	0x01
-#define		RX_BIT		0x02
-#define		TX_BIT		0x04
-#define		EXEC_BIT	0x08
-#define		ALL_INTS	0x0f
-
-#define RCV_START_LOW 4
-#define RCV_START_HIGH 5
-
-#define RCV_STOP_LOW 6
-#define RCV_STOP_HIGH 7
-
-#define XMT_ADDR_REG 0x0a
-#define HOST_ADDR_REG 0x0c
-#define MEM_PORT_REG 0x0e
-
-/* -------------------- bank1 -------------------- */
-
-#define REG1 1
-
-#define		WORD_WIDTH	0x02
-#define		INT_ENABLE	0x80
-
-#define INT_NO_REG 2
-
-#define RCV_LOWER_LIMIT_REG 8
-#define RCV_UPPER_LIMIT_REG 9
-
-#define XMT_LOWER_LIMIT_REG 10
-#define XMT_UPPER_LIMIT_REG 11
-
-/* bank2 */
-
-/* reg1, apparently */
-
-#define		XMT_CHAIN_INT	0x20	/* interrupt at end of xmt chain */
-#define		XMT_CHAIN_ERRSTOP 0x40	/* int at end of chain even if err */
-#define		RCV_DISCARD_BAD	0x80	/* Throw bad frames away and continue */
-
-#define RECV_MODES_REG 2
-
-#define		PROMISC_MODE	0x01
-#define		NO_RX_CRC	0x04
-#define		NO_ADD_INS	0x10
-#define		MULTI_IA	0x20
-
-#define		MATCH_ID	(NO_ADD_INS | NO_RX_CRC | 0x02)
-#define		MATCH_ALL	(NO_ADD_INS | NO_RX_CRC | 0x01)
-#define		MATCH_BRDCST	(NO_ADD_INS | NO_RX_CRC)
-
-#define MEDIA_SELECT 3
-
-#define		TPE_BIT		0x04
-#define		BNC_BIT		0x20
-#define		TEST_MODE_MASK	0x3f
-
-#define I_ADD(n) (n+4)	/* 0..5 -> 4..9 */
-
-#define EEPROM_REG 10
-
-#define		EEDO 8
-#define		EEDI 4
-#define		EECS 2
-#define		EESK 1
-
-/*
- * EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
- * Software Specifications" document.
- */
-
-#define EEPPW0		0
-#define		EEPP_BusWidth	0x0004
-#define		EEPP_FlashAdrs	0x0038
-#define		EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
-					0xD4000, 0xD8000, 0xDC000}
-#define		EEPP_AutoIO	0x0040
-#define		EEPP_IOMapping	0xfc00
-
-#define EEPPW1		1
-#define		EEPP_Int	0x0007
-#define		EEPP_INTMAP	{3, 5, 9, 10, 11, -1, -1, -1}
-#define		EEPP_RINTMAP	{0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
-				 0xff, 0xff, 0x02, 0x03, 0x04 }
-
-#define		EEPP_LinkInteg	0x0008
-#define		EEPP_PolarCorr	0x0010
-#define		EEPP_AuiTpe	0x0020
-#define		EEPP_Jabber	0x0040
-#define		EEPP_AutoPort	0x0080
-#define		EEPP_SmOut	0x0100
-#define		EEPP_BootFls	0x0200
-#define		EEPP_DramSize	0x1000
-#define		EEPP_AltReady	0x2000
-
-#define EEPPEther2	2
-#define EEPPEther1	3
-#define EEPPEther0	4
-
-#define EEPPEther2a	0x3c
-#define EEPPEther1a	0x3d
-#define EEPPEther0a	0x3e
-
-#define EEPPW5		5
-#define		EEPP_BncTpe	0x0001
-#define		EEPP_RomSlct	0x0006	/* none, NetWare, NDIS, rsrvd. */
-#define		EEPP_NumConn	0x0008	/* 0=2, 1=3 */
-
-#define EEPW6		6
-#define EEPP_BoardRev	0x00FF
-
-#define EEPP_LENGTH 0x40
-#define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
-
-#define I595_XMT_HDRLEN	8
-
-#define CMD_MASK	0x001f
-#define TX_DONE		0x0080
-#define CHAIN		0x8000
-
-#define XMT_STATUS	0x02
-#define XMT_CHAIN	0x04
-#define XMT_COUNT	0x06
-
-#define I595_RCV_HDRLEN	8
-
-#define RCV_DONE	0x0008
-#define RX_OK		0x2000
-#define RX_ERR		0x0d81
-
-
diff --git a/sys/dev/ic/i82810reg.h b/sys/dev/ic/i82810reg.h
deleted file mode 100644
index 24e40362ad9..00000000000
--- a/sys/dev/ic/i82810reg.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*	$OpenBSD: i82810reg.h,v 1.4 2007/05/22 04:14:03 jsg Exp $	*/
-
-/*
- * Copyright (c) 2000 Michael Shalayeff
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* Intel i82810/810E memory and graphics controller */
-
-/* Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) */
-#define	I82810_SMRAM		0x70
-#define	I82810_SMRAM_GMS_DIS	0x00
-#define	I82810_SMRAM_GMS_RSRVD	0x40
-#define	I82810_SMRAM_GMS_512	0x80
-#define	I82810_SMRAM_GMS_1024	0xc0
-#define	I82810_SMRAM_USMM_DIS	0x00
-#define	I82810_SMRAM_USMM_TDHE	0x10
-#define	I82810_SMRAM_USMM_T5HE	0x20
-#define	I82810_SMRAM_USMM_T1HE	0x30
-#define	I82810_SMRAM_LSMM_DIS	0x00
-#define	I82810_SMRAM_LSMM_GSM	0x04
-#define	I82810_SMRAM_LSMM_CRSH	0x08
-#define	I82810_SMRAM_D_LCK	0x02
-#define	I82810_SMRAM_E_SMERR	0x01
-#define	I82810_MISCC		0x72
-#define	I82810_MISCC_GDCWS	0x0001
-#define	I82810_MISCC_P_LCK	0x0008
-#define	I82810_MISCC_WPTHC_NO	0x0000
-#define	I82810_MISCC_WPTHC_625	0x0010
-#define	I82810_MISCC_WPTHC_500	0x0020
-#define	I82810_MISCC_WPTHC_375	0x0030
-#define	I82810_MISCC_RPTHC_NO	0x0000
-#define	I82810_MISCC_RPTHC_625	0x0040
-#define	I82810_MISCC_RPTHC_500	0x0080
-#define	I82810_MISCC_RPTHC_375	0x00c0
-
-/* Graphics Device Registers (Device 1) */
-#define	I82810_GMADR		0x10
-#define	I82810_MMADR		0x14
-
-#define	I82810_DRT		0x3000
-#define	I82810_DRT_DP		0x01
-#define	I82810_DRAMCL		0x3001
-#define	I82810_DRAMCL_RPT	0x01
-#define	I82810_DRAMCL_RT	0x02
-#define	I82810_DRAMCL_CL	0x04
-#define	I82810_DRAMCL_RCO	0x08
-#define	I82810_DRAMCL_PMC	0x10
-#define	I82810_DRAMCH		0x3002
-#define	I82810_DRAMCH_SMS	0x07
-#define	I82810_DRAMCH_DRR	0x18
-#define	I82810_GTT		0x10000
-
-/*
- * Intel i82820 memory and graphics controller
- */
-
-/* Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) */
-#define	I82820_SMRAM		0x9c
-#define	I82820_SMRAM_SHIFT	8
-#define	I82820_SMRAM_G_SMRAME	(1 << 3)
-#define	I82820_SMRAM_D_LCK	(1 << 4)
-#define	I82820_SMRAM_D_CLS	(1 << 5)
-#define	I82820_SMRAM_D_OPEN	(1 << 6)
diff --git a/sys/dev/ic/ibm525reg.h b/sys/dev/ic/ibm525reg.h
deleted file mode 100644
index fca2fff436a..00000000000
--- a/sys/dev/ic/ibm525reg.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*	$OpenBSD: ibm525reg.h,v 1.2 2010/08/02 20:55:49 kettenis Exp $	*/
-/*
- * Copyright (c) 2005, Miodrag Vallat.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * IBM RGB525 Ramdac registers
- */
-
-#define	IBM525_REVISION		0x00
-#define	IBM525_ID		0x01
-
-/* Miscellaneous clock control */
-#define	IBM525_MISC_CLOCK	0x02
-#define	MC_B24P_PLL		0x00
-#define	MC_B24P_SCLK		0x20
-#define	MC_DDOT_DIV_1		0x00	/* (VRAM size / 1) bpp */
-#define	MC_DDOT_DIV_2		0x02	/* (VRAM size / 2) bpp */
-#define	MC_DDOT_DIV_4		0x04	/* (VRAM size / 4) bpp */
-#define	MC_DDOT_DIV_8		0x06	/* (VRAM size / 8) bpp */
-#define	MC_DDOT_DIV_16		0x08	/* (VRAM size / 16) bpp */
-#define	MC_DDOT_DIV_MASK	0x0e
-#define	MC_PLL_ENABLE		0x01
-
-/* Sync control */
-#define	IBM525_SYNC		0x03
-#define	S_CSYN_INVERT		0x40	/* Composite sync invert */
-#define	S_VSYN_INVERT		0x20	/* Vertical sync invert (positive) */
-#define	S_HSYN_INVERT		0x10	/* Horizontal sync invert (positive) */
-#define	S_VSYN_NORMAL		0x00
-#define	S_VSYN_HIGH		0x04
-#define	S_VSYN_LOW		0x08
-#define	S_VSYN_DISABLE		0x0c
-#define	S_VSYN_MASK		0x0c
-#define	S_HSYN_NORMAL		0x00
-#define	S_HSYN_HIGH		0x01
-#define	S_HSYN_LOW		0x02
-#define	S_HSYN_DISABLE		0x03
-#define	S_HSYN_MASK		0x03
-
-/* Horizontal sync position */
-#define	IBM525_HSYNC_POS	0x04
-
-/* Power management */
-#define	IBM525_POWER		0x05
-#define	P_SCLK_DISABLE		0x10
-#define	P_DDOT_DISABLE		0x08
-#define	P_SYNC_DISABLE		0x04
-#define	P_ICLK_DISABLE		0x02	/* Disable internal DAC clock */
-#define	P_DAC_PWR_DISABLE	0x01	/* Disable internal DAC power */
-
-/* DAC operation */
-#define	IBM525_DAC_OP		0x06
-#define	DO_SOG			0x08	/* Sync on Green */
-#define	DO_FAST_SLEW		0x02	/* fast (>= 20 MHz) pixel clock */
-#define	DO_BLANK_BR		0x04	/* blank blue and red channels */
-#define	DO_PEDESTAL		0x01
-
-/* Palette control */
-#define	IBM525_PALETTE		0x07
-
-/* System clock control */
-#define	IBM525_SYSCLK		0x08
-#define	SC_ENABLE		0x01
-
-/* Pixel format */
-#define	IBM525_PIXEL		0x0a
-#define	PIX_4BPP		0x02
-#define	PIX_8BPP		0x03
-#define	PIX_16BPP		0x04
-#define	PIX_24BPP		0x05
-#define	PIX_32BPP		0x06
-
-/* 8bpp pixel format */
-#define	IBM525_PF8		0x0b
-#define	PF8_INDIRECT		0x00
-#define	PF8_DIRECT		0x01
-
-/* 16bpp pixel format */
-#define	IBM525_PF16		0x0c
-#define	PF16_INDIRECT		0x00
-#define	PF16_DIRECT		0xc0
-#define	PF16_LINEAR		0x04
-#define	PF16_555		0x00	/* 5:5:5 15bpp */
-#define	PF16_565		0x02	/* 5:6:5 15bpp */
-
-/* 24bpp pixel format */
-#define	IBM525_PF24		0x0d
-#define	PF24_INDIRECT		0x00
-#define	PF24_DIRECT		0x01
-
-/* 32bpp pixel format */
-#define	IBM525_PF32		0x0e
-#define	PF32_INDIRECT		0x00
-#define	PF32_DIRECT		0x03
-#define	PF32_BYPASS		0x00
-#define	PF32_LOOKUP		0x04
-
-/* Pixel PLL control #1 */
-#define	IBM525_PLL1		0x10
-#define	P1_CLK_REF		0x00
-#define	P1_CLK_EXT		0x10
-#define	P1_SRC_EXT_F		0x00	/* Use F registers for timing */
-#define	P1_SRC_EXT_MN		0x01	/* Use M:N registers for timing */
-#define	P1_SRC_DIRECT_F		0x02	/* Use F registers for timing */
-#define	P1_SRC_DIRECT_MN	0x03	/* Use M:N registers for timing */
-
-/* Pixel PLL control #2 */
-#define	IBM525_PLL2		0x11
-
-/* Fixed PLL reference */
-#define	IBM525_PLL_FIXED_REF	0x14
-
-/* PLL reference divider */
-#define	IBM525_PLL_REF_DIV	0x15
-
-/* PLL VCO divider */
-#define	IBM525_PLL_VCO_DIV	0x16
-
-/* N0-N15 */
-#define	IBM525_F(n)		(0x20 + (n))
-
-/* Miscellaneous control #1 */
-#define	IBM525_MISC1		0x70
-#define	M1_VRAM_32		0x00
-#define	M1_VRAM_64		0x01
-#define	M1_VRAM_SIZE_MASK	0x01
-#define	M1_SENSE_DISABLE	0x10
-
-/* Miscellaneous control #2 */
-#define	IBM525_MISC2		0x71
-#define	M2_PCLK_LOCAL		0x00
-#define	M2_PCLK_PLL		0x40
-#define	M2_PCLK_EXT		0x80
-#define	M2_PCLK_MASK		0xc0
-#define	M2_PALETTE_6		0x00	/* VGA compatible 6bit palette */
-#define	M2_PALETTE_8		0x04	/* 8bit palette */
-#define	M2_PALETTE_MASK		0x04
-#define	M2_MODE_VRAM		0x01
-#define	M2_MODE_VGA		0x00
-#define	M2_MODE_MASK		0x01
-
-/* Miscellaneous control #3 */
-#define	IBM525_MISC3		0x72
-#define	M3_SWAP_BR		0x80	/* swap blue and red */
-#define	M3_SWAP_WORDS		0x10
-#define	M3_SWAP_NIBBLES		0x02
-
-/* Miscellaneous control #4 */
-#define	IBM525_MISC4		0x73
-#define	M4_INVERT_DCLK		0x10
-#define	M4_FAST			0x20	/* Fast (>= 50 MHz) pixel clock */
-
-/*
- * Pixel clock encoding
- */
-#define	MHZ_TO_PLL(m) \
-	((m) < 32 ? 0x00 | (4 * (m) - 65) : \
-	   (m) < 64 ? 0x40 | (2 * (m) - 65) : \
-	     (m) < 128 ? 0x80 | ((m) - 65) : \
-	       0xc0 | ((m) / 2 - 65))
diff --git a/sys/dev/ic/intersil7170.h b/sys/dev/ic/intersil7170.h
deleted file mode 100644
index 065ee6f87f1..00000000000
--- a/sys/dev/ic/intersil7170.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*	$OpenBSD: intersil7170.h,v 1.2 2008/06/26 05:42:15 ray Exp $	*/
-/*	$NetBSD: intersil7170.h,v 1.1 1997/05/02 06:15:28 jeremy Exp $	*/
-
-/*-
- * Copyright (c) 1996 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Adam Glass.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef	_INTERSIL7170_H
-#define	_INTERSIL7170_H
-
-/*
- * Driver support for the intersil7170 used in sun[34]s to provide
- * real time clock and time-of-day support.
- *
- * Derived from: datasheet "ICM7170 a uP-Compatible Real-Time Clock"
- *                          document #301680-005, Dec 85
- */
-
-struct intersil_dt {		       /* from p. 7 of 10 */
-    u_int8_t dt_csec;
-    u_int8_t dt_hour;
-    u_int8_t dt_min;
-    u_int8_t dt_sec;
-    u_int8_t dt_month;
-    u_int8_t dt_day;
-    u_int8_t dt_year;
-    u_int8_t dt_dow;
-};
-
-struct intersil7170 {
-    struct intersil_dt counters;
-    struct intersil_dt clk_ram;	/* should be ok as both are word aligned */
-    u_int8_t clk_intr_reg;
-    u_int8_t clk_cmd_reg;
-};
-
-/*  bit assignments for command register, p. 6 of 10, write-only */
-#define INTERSIL_CMD_FREQ_32K    0x0
-#define INTERSIL_CMD_FREQ_1M     0x1
-#define INTERSIL_CMD_FREQ_2M     0x2
-#define INTERSIL_CMD_FREQ_4M     0x3
-
-#define INTERSIL_CMD_12HR_MODE   0x0
-#define INTERSIL_CMD_24HR_MODE   0x4
-
-#define INTERSIL_CMD_STOP        0x0
-#define INTERSIL_CMD_RUN         0x8
-
-#define INTERSIL_CMD_IDISABLE   0x0
-#define INTERSIL_CMD_IENABLE   0x10
-
-#define INTERSIL_CMD_TEST_MODE      0x20
-#define INTERSIL_CMD_NORMAL_MODE    0x0
-
-/* bit assignments for interrupt register r/w, p 7 of 10*/
-
-#define INTERSIL_INTER_ALARM       0x1 /* r/w */
-#define INTERSIL_INTER_CSECONDS    0x2 /* r/w */
-#define INTERSIL_INTER_DSECONDS    0x4 /* r/w */
-#define INTERSIL_INTER_SECONDS     0x8 /* r/w */
-#define INTERSIL_INTER_MINUTES    0x10 /* r/w */
-#define INTERSIL_INTER_HOURS      0x20 /* r/w */
-#define INTERSIL_INTER_DAYS       0x40 /* r/w */
-#define INTERSIL_INTER_PENDING    0x80 /* read-only */
-
-#define INTERSIL_INTER_BITS "\20\10PENDING\7DAYS\6HRS\5MIN\4SCDS\3DSEC\2CSEC\1ALARM"
-
-#endif	/* _INTERSIL7170_H */