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authorPatrick Wildt <patrick@cvs.openbsd.org>2013-05-01 00:16:27 +0000
committerPatrick Wildt <patrick@cvs.openbsd.org>2013-05-01 00:16:27 +0000
commit8b615fe42d15574193f8112a277b25f65db72cd8 (patch)
tree0e14e21cba88e428f9a29cdb8594cd3d654add12 /sys/dev/ic
parent7ea3da0e50669753497cc90cef8b4e56a676b2ae (diff)
Add a cortex bus which represents the ARM MPCore Complex.
It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register. ok bmercer@
Diffstat (limited to 'sys/dev/ic')
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