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authorDamien Bergamini <damien@cvs.openbsd.org>2010-04-05 19:00:51 +0000
committerDamien Bergamini <damien@cvs.openbsd.org>2010-04-05 19:00:51 +0000
commitf72eaec21ea2ca0c18a2c9f8b314352921170f3c (patch)
treea56fe2ce03b24bac2ec189532bf9bc29985bd7f9 /sys/dev/ic
parent949a5e50bbb2b10122c0e2b8aefaa6d2bfd5deef (diff)
fix regression on RT2860C introduced in previous commit.
Diffstat (limited to 'sys/dev/ic')
-rw-r--r--sys/dev/ic/ar9287.c6
-rw-r--r--sys/dev/ic/athn.c22
-rw-r--r--sys/dev/ic/rt2860.c9
3 files changed, 29 insertions, 8 deletions
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c
index d8aef15b69d..d1dd87c204b 100644
--- a/sys/dev/ic/ar9287.c
+++ b/sys/dev/ic/ar9287.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ar9287.c,v 1.5 2010/03/28 13:02:57 krw Exp $ */
+/* $OpenBSD: ar9287.c,v 1.6 2010/04/05 19:00:50 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -590,6 +590,10 @@ ar9287_1_2_setup_async_fifo(struct athn_softc *sc)
{
uint32_t reg;
+ /*
+ * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is
+ * enabled, so the following counters have to be changed.
+ */
AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index dec4925384c..cbfec34b79d 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: athn.c,v 1.29 2010/03/28 13:02:57 krw Exp $ */
+/* $OpenBSD: athn.c,v 1.30 2010/04/05 19:00:50 damien Exp $ */
/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -2084,7 +2084,7 @@ athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
}
/*
- * Anti-noise immunity.
+ * Adaptive noise immunity.
*/
int32_t
athn_ani_get_rssi(struct athn_softc *sc)
@@ -3920,6 +3920,7 @@ athn_enable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_IMR, mask);
mask2 = AR_READ(sc, AR_IMR_S2);
+printf("%s IMR_S2=0x%08x\n", __func__, mask2);
mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR);
mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST;
@@ -3950,9 +3951,18 @@ athn_disable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_IMR, 0);
- AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
+{
+uint32_t tmp;
+tmp = AR_READ(sc, AR_IMR_S2);
+printf("%s IMR_S2=0x%08x\n", __func__, tmp);
+tmp &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
+AR_WRITE(sc, AR_IMR_S2, tmp);
+/* AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
+ AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
+ AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);*/
+}
AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
}
@@ -4216,7 +4226,11 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
sc->imask |= AR_IMR_MIB;
#endif
AR_WRITE(sc, AR_IMR, sc->imask);
- AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
+reg = AR_READ(sc, AR_IMR_S2);
+printf("%s AR_IMR_S2=0x%08x\n", __func__, reg);
+reg |= AR_IMR_S2_GTT;
+AR_WRITE(sc, AR_IMR_S2, reg);
+// AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
sc->isync = AR_INTR_SYNC_DEFAULT;
if (sc->flags & ATHN_FLAG_RFSILENT)
diff --git a/sys/dev/ic/rt2860.c b/sys/dev/ic/rt2860.c
index d439d2d293e..f3ea8430450 100644
--- a/sys/dev/ic/rt2860.c
+++ b/sys/dev/ic/rt2860.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: rt2860.c,v 1.44 2010/04/05 14:14:02 damien Exp $ */
+/* $OpenBSD: rt2860.c,v 1.45 2010/04/05 19:00:50 damien Exp $ */
/*-
* Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -3039,8 +3039,11 @@ rt2860_bbp_init(struct rt2860_softc *sc)
if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
rt2860_mcu_bbp_write(sc, 84, 0x19);
- /* fix BBP69 and BBP73 for RT2860C */
- if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0100) {
+ if (sc->mac_ver >= 0x3090) {
+ rt2860_mcu_bbp_write(sc, 79, 0x13);
+ rt2860_mcu_bbp_write(sc, 80, 0x05);
+ rt2860_mcu_bbp_write(sc, 81, 0x33);
+ } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
rt2860_mcu_bbp_write(sc, 69, 0x16);
rt2860_mcu_bbp_write(sc, 73, 0x12);
}