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authorBrad Smith <brad@cvs.openbsd.org>2004-10-29 01:10:44 +0000
committerBrad Smith <brad@cvs.openbsd.org>2004-10-29 01:10:44 +0000
commitb9229d3b4e4582944c8babf32bb7588dd94c97d1 (patch)
treed673b7dfeb13a88482d2b10e987ab553476388ec /sys/dev/ic
parent08135d9274a459e8ff5a3ffa240f5175efa7b5bb (diff)
rev 1.78
Enable the automatic TX underrun recovery for the ADMtek chips. This solves cvsup update on my laptop which aborts after a while without this patch. rev 1.79 Fix the support for the AN985/983 chips, which do not set the RXSTATE to STOPPED, but to WAIT. This should fix hangs which could only be solved by replugging the cable. From FreeBSD Thanks to C. Bensend <benny at bennyvision dot com> for testing.
Diffstat (limited to 'sys/dev/ic')
-rw-r--r--sys/dev/ic/dc.c12
-rw-r--r--sys/dev/ic/dcreg.h4
2 files changed, 13 insertions, 3 deletions
diff --git a/sys/dev/ic/dc.c b/sys/dev/ic/dc.c
index 4f1922d9aea..b4ed082f430 100644
--- a/sys/dev/ic/dc.c
+++ b/sys/dev/ic/dc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: dc.c,v 1.72 2004/10/14 15:34:28 brad Exp $ */
+/* $OpenBSD: dc.c,v 1.73 2004/10/29 01:10:43 brad Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -1232,7 +1232,8 @@ dc_setcfg(sc, media)
for (i = 0; i < DC_TIMEOUT; i++) {
isr = CSR_READ_4(sc, DC_ISR);
if (isr & DC_ISR_TX_IDLE &&
- (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
+ ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
+ (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
break;
DELAY(10);
}
@@ -1766,6 +1767,13 @@ hasmac:
DELAY(10);
}
+ if (DC_IS_ADMTEK(sc)) {
+ /*
+ * Set automatic TX underrun recovery for the ADMtek chips
+ */
+ DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
+ }
+
/*
* Call MI attach routines.
*/
diff --git a/sys/dev/ic/dcreg.h b/sys/dev/ic/dcreg.h
index fa7c98bbe88..408afc17967 100644
--- a/sys/dev/ic/dcreg.h
+++ b/sys/dev/ic/dcreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: dcreg.h,v 1.37 2004/10/14 15:36:03 brad Exp $ */
+/* $OpenBSD: dcreg.h,v 1.38 2004/10/29 01:10:43 brad Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -540,6 +540,7 @@ struct dc_mii_frame {
* ADMtek specific registers and constants for the AL981 and AN983.
* The AN983 doesn't use the magic PHY registers.
*/
+#define DC_AL_CR 0x88 /* Command register */
#define DC_AL_PAR0 0xA4 /* station address */
#define DC_AL_PAR1 0xA8 /* station address */
#define DC_AL_MAR0 0xAC /* multicast hash filter */
@@ -554,6 +555,7 @@ struct dc_mii_frame {
#define DC_ADMTEK_PHYADDR 0x1
#define DC_AL_EE_NODEADDR 8
+#define DC_AL_CR_ATUR 0x00000001 /* Enable automatic TX underrun recovery */
/* End of ADMtek specific registers */
/*