diff options
author | Michael Shalayeff <mickey@cvs.openbsd.org> | 2000-08-01 17:42:18 +0000 |
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committer | Michael Shalayeff <mickey@cvs.openbsd.org> | 2000-08-01 17:42:18 +0000 |
commit | 89e58d669913da272f1295de5b726fc466361c31 (patch) | |
tree | ceffc00e28bf76a8ecd1d2a6a39cd80ba572c54d /sys/dev/ic | |
parent | b6d634fe064a1c5bb11dd4406ee7785a4b244894 (diff) |
forgot these in alpha/wscons upgrade; pointed out by Erik Verbruggen <ejv@cs.kun.nl>
Diffstat (limited to 'sys/dev/ic')
-rw-r--r-- | sys/dev/ic/bt463reg.h | 89 | ||||
-rw-r--r-- | sys/dev/ic/bt485reg.h | 64 |
2 files changed, 153 insertions, 0 deletions
diff --git a/sys/dev/ic/bt463reg.h b/sys/dev/ic/bt463reg.h new file mode 100644 index 00000000000..16f9c0671ee --- /dev/null +++ b/sys/dev/ic/bt463reg.h @@ -0,0 +1,89 @@ +/* $NetBSD: bt463reg.h,v 1.1 1998/08/18 07:43:09 thorpej Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Register definitions for the Brooktree Bt463 135MHz Monolithic + * CMOS TrueVu RAMDAC. + */ + +/* + * Directly-accessible registers. Note the address register is + * auto-incrementing. + */ +#define BT463_REG_ADDR_LOW 0x00 /* C1,C0 == 0,0 */ +#define BT463_REG_ADDR_HIGH 0x01 /* C1,C0 == 0,1 */ +#define BT463_REG_IREG_DATA 0x02 /* C1,C0 == 1,0 */ +#define BT463_REG_CMAP_DATA 0x03 /* C1,C0 == 1,1 */ + +#define BT463_REG_MAX BT463_REG_CMAP_DATA + +/* + * All internal register access to the Bt463 is done indirectly via the + * Address Register (mapped into the host bus in a device-specific + * fashion). The following register definitions are in terms of + * their address register address values. + */ + +/* C1,C0 must be 1,0 */ +#define BT463_IREG_CURSOR_COLOR_0 0x0100 /* 3 r/w cycles */ +#define BT463_IREG_CURSOR_COLOR_1 0x0101 /* 3 r/w cycles */ +#define BT463_IREG_ID 0x0200 +#define BT463_IREG_COMMAND_0 0x0201 +#define BT463_IREG_COMMAND_1 0x0202 +#define BT463_IREG_COMMAND_2 0x0203 +#define BT463_IREG_READ_MASK_P0_P7 0x0205 +#define BT463_IREG_READ_MASK_P8_P15 0x0206 +#define BT463_IREG_READ_MASK_P16_P23 0x0207 +#define BT463_IREG_READ_MASK_P24_P27 0x0208 +#define BT463_IREG_BLINK_MASK_P0_P7 0x0209 +#define BT463_IREG_BLINK_MASK_P8_P15 0x020a +#define BT463_IREG_BLINK_MASK_P16_P23 0x020b +#define BT463_IREG_BLINK_MASK_P24_P27 0x020c +#define BT463_IREG_TEST 0x020d +#define BT463_IREG_INPUT_SIG 0x020e /* 2 of 3 r/w cycles */ +#define BT463_IREG_OUTPUT_SIG 0x020f /* 3 r/w cycles */ +#define BT463_IREG_REVISION 0x0220 +#define BT463_IREG_WINDOW_TYPE_TABLE 0x0300 /* 3 r/w cycles */ + +#define BT463_NWTYPE_ENTRIES 0x10 /* 16 window type entries */ + +/* C1,C0 must be 1,1 */ +#define BT463_IREG_CPALETTE_RAM 0x0000 /* 3 r/w cycles */ + +#define BT463_NCMAP_ENTRIES 0x210 /* 528 CMAP entries */ diff --git a/sys/dev/ic/bt485reg.h b/sys/dev/ic/bt485reg.h new file mode 100644 index 00000000000..30f693d0acd --- /dev/null +++ b/sys/dev/ic/bt485reg.h @@ -0,0 +1,64 @@ +/* $NetBSD: bt485reg.h,v 1.1 1998/04/15 20:16:30 drochner Exp $ */ + +/* + * Copyright (c) 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Register definitions for the Brooktree Bt485A 170MHz Monolithic + * CMOS True-Color RAMDAC. + */ + + +/* + * Directly-addressed registers. + */ +#define BT485_REG_PCRAM_WRADDR 0x00 +#define BT485_REG_PALETTE 0x01 +#define BT485_REG_PIXMASK 0x02 +#define BT485_REG_PCRAM_RDADDR 0x03 +#define BT485_REG_COC_WRADDR 0x04 +#define BT485_REG_COCDATA 0x05 +#define BT485_REG_COMMAND_0 0x06 +#define BT485_REG_COC_RDADDR 0x07 +#define BT485_REG_COMMAND_1 0x08 +#define BT485_REG_COMMAND_2 0x09 +#define BT485_REG_STATUS 0x0a +#define BT485_REG_EXTENDED BT485_REG_STATUS +#define BT485_REG_CURSOR_RAM 0x0b +#define BT485_REG_CURSOR_X_LOW 0x0c +#define BT485_REG_CURSOR_X_HIGH 0x0d +#define BT485_REG_CURSOR_Y_LOW 0x0e +#define BT485_REG_CURSOR_Y_HIGH 0x0f + +#define BT485_REG_MAX 0x0f + +#define BT485_IREG_STATUS 0x00 +#define BT485_IREG_COMMAND_3 0x01 +#define BT485_IREG_COMMAND_4 0x02 +#define BT485_IREG_RSA 0x20 +#define BT485_IREG_GSA 0x21 +#define BT485_IREG_BSA 0x22 |