diff options
| author | Damien Bergamini <damien@cvs.openbsd.org> | 2010-04-05 19:09:01 +0000 |
|---|---|---|
| committer | Damien Bergamini <damien@cvs.openbsd.org> | 2010-04-05 19:09:01 +0000 |
| commit | b3ee23f6f1ef7056d7a866667887bdf260cb5466 (patch) | |
| tree | e666fd4cbe25d51eb1bf4b33705d0818451e294c /sys/dev/ic | |
| parent | f381e6f17e41a42968f3f43122431778e6fbbea1 (diff) | |
backout these two files i committed by accident.
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/ar9287.c | 6 | ||||
| -rw-r--r-- | sys/dev/ic/athn.c | 22 |
2 files changed, 5 insertions, 23 deletions
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c index d1dd87c204b..439feceec10 100644 --- a/sys/dev/ic/ar9287.c +++ b/sys/dev/ic/ar9287.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ar9287.c,v 1.6 2010/04/05 19:00:50 damien Exp $ */ +/* $OpenBSD: ar9287.c,v 1.7 2010/04/05 19:09:00 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -590,10 +590,6 @@ ar9287_1_2_setup_async_fifo(struct athn_softc *sc) { uint32_t reg; - /* - * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is - * enabled, so the following counters have to be changed. - */ AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c index cbfec34b79d..dd6b17ed3b7 100644 --- a/sys/dev/ic/athn.c +++ b/sys/dev/ic/athn.c @@ -1,4 +1,4 @@ -/* $OpenBSD: athn.c,v 1.30 2010/04/05 19:00:50 damien Exp $ */ +/* $OpenBSD: athn.c,v 1.31 2010/04/05 19:09:00 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -2084,7 +2084,7 @@ athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, } /* - * Adaptive noise immunity. + * Anti-noise immunity. */ int32_t athn_ani_get_rssi(struct athn_softc *sc) @@ -3920,7 +3920,6 @@ athn_enable_interrupts(struct athn_softc *sc) AR_WRITE(sc, AR_IMR, mask); mask2 = AR_READ(sc, AR_IMR_S2); -printf("%s IMR_S2=0x%08x\n", __func__, mask2); mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; @@ -3951,18 +3950,9 @@ athn_disable_interrupts(struct athn_softc *sc) AR_WRITE(sc, AR_IMR, 0); -{ -uint32_t tmp; -tmp = AR_READ(sc, AR_IMR_S2); -printf("%s IMR_S2=0x%08x\n", __func__, tmp); -tmp &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | + AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); -AR_WRITE(sc, AR_IMR_S2, tmp); -/* AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | - AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | - AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);*/ -} AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); } @@ -4226,11 +4216,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c, sc->imask |= AR_IMR_MIB; #endif AR_WRITE(sc, AR_IMR, sc->imask); -reg = AR_READ(sc, AR_IMR_S2); -printf("%s AR_IMR_S2=0x%08x\n", __func__, reg); -reg |= AR_IMR_S2_GTT; -AR_WRITE(sc, AR_IMR_S2, reg); -// AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); + AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); sc->isync = AR_INTR_SYNC_DEFAULT; if (sc->flags & ATHN_FLAG_RFSILENT) |