add comments; from banshee@gabriella.resort.com; netbsd pr#1864

1 files changed, 48 insertions, 46 deletions

diff --git a/sys/dev/isa/comreg.h b/sys/dev/isa/comreg.h
index da3fe9b6ef3..96c92944e2b 100644
--- a/sys/dev/isa/comreg.h
+++ b/sys/dev/isa/comreg.h
@@ -41,10 +41,10 @@
 #define	COM_TOLERANCE	30	/* baud rate tolerance, in 0.1% units */
 
 /* interrupt enable register */
-#define	IER_ERXRDY	0x1
-#define	IER_ETXRDY	0x2
-#define	IER_ERLS	0x4
-#define	IER_EMSC	0x8
+#define	IER_ERXRDY	0x1	/* Character received */
+#define	IER_ETXRDY	0x2	/* Transmitter empty */
+#define	IER_ERLS	0x4	/* Error condition */
+#define	IER_EMSC	0x8	/* RS-232 line state change */
 
 /* interrupt identification register */
 #define	IIR_IMASK	0xf
@@ -52,61 +52,63 @@
 #define	IIR_RLS		0x6
 #define	IIR_RXRDY	0x4
 #define	IIR_TXRDY	0x2
-#define	IIR_NOPEND	0x1
+#define	IIR_NOPEND	0x1	/* No pending interrupts */
 #define	IIR_MLSC	0x0
 #define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
 
 /* fifo control register */
-#define	FIFO_ENABLE	0x01
-#define	FIFO_RCV_RST	0x02
-#define	FIFO_XMT_RST	0x04
-#define	FIFO_DMA_MODE	0x08
-#define	FIFO_TRIGGER_1	0x00
-#define	FIFO_TRIGGER_4	0x40
-#define	FIFO_TRIGGER_8	0x80
-#define	FIFO_TRIGGER_14	0xc0
+#define	FIFO_ENABLE	0x01	/* Turn the FIFO on */
+#define	FIFO_RCV_RST	0x02	/* Reset RX FIFO */
+#define	FIFO_XMT_RST	0x04	/* Reset TX FIFO */
+#define	FIFO_DMA_MODE	0x08	/* DMA mode? */
+#define	FIFO_TRIGGER_1	0x00	/* Trigger RXRDY Interrupt on 1 character */
+#define	FIFO_TRIGGER_4	0x40	/* ibid 4 */
+#define	FIFO_TRIGGER_8	0x80	/* ibid 8 */
+#define	FIFO_TRIGGER_14	0xc0	/* ibid 14 */
 
 /* line control register */
-#define	LCR_DLAB	0x80
-#define	LCR_SBREAK	0x40
-#define	LCR_PZERO	0x30
-#define	LCR_PONE	0x20
-#define	LCR_PEVEN	0x10
-#define	LCR_PODD	0x00
-#define	LCR_PENAB	0x08
-#define	LCR_STOPB	0x04
-#define	LCR_8BITS	0x03
-#define	LCR_7BITS	0x02
-#define	LCR_6BITS	0x01
-#define	LCR_5BITS	0x00
+#define	LCR_DLAB	0x80	/* Divisor latch access enable */
+#define	LCR_SBREAK	0x40	/* Break Control */
+#define	LCR_PZERO	0x38	/* Space parity */
+#define	LCR_PONE	0x28	/* Mark parity */
+#define	LCR_PEVEN	0x18	/* Even parity */
+#define	LCR_PODD	0x08	/* Odd parity */
+#define	LCR_PNONE	0x00	/* No parity */
+#define	LCR_PENAB	0x08	/* XXX - low order bit of all parity */
+#define	LCR_STOPB	0x04	/* 2 stop bits per serial word */
+#define	LCR_8BITS	0x03	/* 8 bits per serial word */
+#define	LCR_7BITS	0x02	/* 7 bits */
+#define	LCR_6BITS	0x01	/* 6 bits */
+#define	LCR_5BITS	0x00	/* 5 bits */
 
 /* modem control register */
-#define	MCR_LOOPBACK	0x10
-#define	MCR_IENABLE	0x08
-#define	MCR_DRS		0x04
-#define	MCR_RTS		0x02
-#define	MCR_DTR		0x01
+#define	MCR_LOOPBACK	0x10	/* Loop test: echos from TX to RX */
+#define	MCR_IENABLE	0x08	/* Output 2: enables UART interrupts */
+#define	MCR_DRS		0x04	/* Output 1: resets some internal modems */
+#define	MCR_RTS		0x02	/* RTS: ready to receive data */
+#define	MCR_DTR		0x01	/* Data Terminal Ready */
 
 /* line status register */
 #define	LSR_RCV_FIFO	0x80
-#define	LSR_TSRE	0x40
-#define	LSR_TXRDY	0x20
-#define	LSR_BI		0x10
-#define	LSR_FE		0x08
-#define	LSR_PE		0x04
-#define	LSR_OE		0x02
-#define	LSR_RXRDY	0x01
-#define	LSR_RCV_MASK	0x1f
+#define	LSR_TSRE	0x40	/* Transmitter empty: byte sent */
+#define	LSR_TXRDY	0x20	/* Transmitter buffer empty */
+#define	LSR_BI		0x10	/* Break detected */
+#define	LSR_FE		0x08	/* Framing error: bad stop bit */
+#define	LSR_PE		0x04	/* Parity error */
+#define	LSR_OE		0x02	/* Overrun, lost incoming byte */
+#define	LSR_RXRDY	0x01	/* Byte ready in Receive Buffer */
+#define	LSR_RCV_MASK	0x1f	/* Mask for incoming data or error */
 
 /* modem status register */
-#define	MSR_DCD		0x80
-#define	MSR_RI		0x40
-#define	MSR_DSR		0x20
-#define	MSR_CTS		0x10
-#define	MSR_DDCD	0x08
-#define	MSR_TERI	0x04
-#define	MSR_DDSR	0x02
-#define	MSR_DCTS	0x01
+/* All deltas are from the last read of the MSR. */
+#define	MSR_DCD		0x80	/* Current Data Carrier Detect */
+#define	MSR_RI		0x40	/* Current Ring Indicator */
+#define	MSR_DSR		0x20	/* Current Data Set Ready */
+#define	MSR_CTS		0x10	/* Current Clear to Send */
+#define	MSR_DDCD	0x08	/* DCD has changed state */
+#define	MSR_TERI	0x04	/* RI has toggled low to high */
+#define	MSR_DDSR	0x02	/* DSR has changed state */
+#define	MSR_DCTS	0x01	/* CTS has changed state */
 
 #define	COM_NPORTS	8