New port of FreeBSD's ahc driver

11 files changed, 2881 insertions, 1789 deletions

diff --git a/sys/dev/microcode/aic7xxx/Makefile b/sys/dev/microcode/aic7xxx/Makefile
index 2b91caf6dcd..d4d4e11f005 100644
--- a/sys/dev/microcode/aic7xxx/Makefile
+++ b/sys/dev/microcode/aic7xxx/Makefile
@@ -1,4 +1,4 @@
-# $OpenBSD: Makefile,v 1.1 2000/03/22 02:50:49 smurph Exp $
+# $OpenBSD: Makefile,v 1.2 2002/02/16 04:36:33 smurph Exp $
 # $FreeBSD: src/sys/dev/aic7xxx/Makefile,v 1.6 1999/08/28 00:41:22 peter Exp $
 
 PROG=	aicasm
@@ -27,11 +27,11 @@ NOMAN=	noman
 CFLAGS+= -DDEBUG -g
 YFLAGS+= -t
 LFLAGS+= -d
-MFLAGS= -l seq.lst
+SEQFLAGS= -l seq.lst
 .endif
 
 microcode aic7xxxreg.h aic7xxx_seq.h: aic7xxx.seq aic7xxx.reg
-	./aicasm -I/sys ${MFLAGS} -r tempreg.h -o tempseq.h ${.CURDIR}/aic7xxx.seq
+	${OBJDIR}./aicasm -I/sys ${SEQFLAGS} -r tempreg.h -o tempseq.h ${.CURDIR}/aic7xxx.seq
 	grep OpenBSD: ${.CURDIR}/aic7xxx.seq | cat - tempseq.h > aic7xxx_seq.h
 	grep OpenBSD: ${.CURDIR}/aic7xxx.reg | cat - tempreg.h > aic7xxxreg.h
 	mv aic7xxx_seq.h /sys/dev/microcode/aic7xxx/
diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.reg b/sys/dev/microcode/aic7xxx/aic7xxx.reg
index bb52bdba889..6be74e809ba 100644
--- a/sys/dev/microcode/aic7xxx/aic7xxx.reg
+++ b/sys/dev/microcode/aic7xxx/aic7xxx.reg
@@ -1,9 +1,8 @@
-/*	$NetBSD$	*/
-
+/* $OpenBSD: aic7xxx.reg,v 1.3 2002/02/16 04:36:33 smurph Exp $ */
 /*
  * Aic7xxx register and scratch ram definitions.
  *
- * Copyright (c) 1994-2000 Justin Gibbs.
+ * Copyright (c) 1994-2001 Justin Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -16,7 +15,7 @@
  *    derived from this software without specific prior written permission.
  *
  * Alternatively, this software may be distributed under the terms of the
- * the GNU Public License ("GPL").
+ * GNU Public License ("GPL").
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -30,9 +29,11 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.20 2000/02/09 21:24:59 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.39 2001/07/18 21:39:47 gibbs Exp $
  */
 
+VERSION = "$Id: aic7xxx.reg,v 1.3 2002/02/16 04:36:33 smurph Exp $"
+
 /*
  * This file is processed by the aic7xxx_asm utility for use in assembling
  * firmware for the aic7xxx family of SCSI host adapters as well as to generate
@@ -112,6 +113,8 @@ register SCSISIGI {
 	mask	PHASE_MASK	CDI|IOI|MSGI
 	mask	P_DATAOUT	0x00
 	mask	P_DATAIN	IOI
+        mask    P_DATAOUT_DT    P_DATAOUT|MSGI
+        mask    P_DATAIN_DT     P_DATAIN|MSGI
 	mask	P_COMMAND	CDI
 	mask	P_MESGOUT	CDI|MSGI
 	mask	P_STATUS	CDI|IOI
@@ -174,6 +177,8 @@ register SCSIID	{
 	address			0x005
 	access_mode RW
 	mask	TID		0xf0		/* Target ID mask */
+        mask    TWIN_TID        0x70
+        bit     TWIN_CHNLB      0x80
 	mask	OID		0x0f		/* Our ID mask */
 	/*
 	 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
@@ -246,6 +251,7 @@ register CLRSINT0 {
 	bit	CLRSELDI	0x20
 	bit	CLRSELINGO	0x10
 	bit	CLRSWRAP	0x08
+        bit     CLRIOERR        0x08    /* Ultra2 Only */
 	bit	CLRSPIORDY	0x02
 }
 
@@ -307,7 +313,12 @@ register SSTAT2 {
 	address			0x00d
 	access_mode RO
 	bit	OVERRUN		0x80
+        bit     SHVALID         0x40    /* Shaddow Layer non-zero */
 	bit	EXP_ACTIVE	0x10	/* SCSI Expander Active */
+        bit     CRCVALERR       0x08    /* CRC doesn't match (U3 only) */
+        bit     CRCENDERR       0x04    /* No terminal CRC packet (U3 only) */
+        bit     CRCREQERR       0x02    /* Illegal CRC packet req (U3 only) */
+        bit     DUAL_EDGE_ERR   0x01    /* Incorrect data phase (U3 only) */
 	mask	SFCNT		0x1f
 }
 
@@ -373,12 +384,12 @@ register SIMODE1 {
  */
 register SCSIBUSL {
 	address			0x012
-	access_mode RO
+        access_mode RW
 }
 
 register SCSIBUSH {
 	address			0x013
-	access_mode RO
+        access_mode RW
 }
 
 /*
@@ -673,8 +684,16 @@ register DSCOMMAND0 {
 	bit	CIOPARCKEN	0x01	/* Internal bus parity error enable */
 }
 
+register DSCOMMAND1 {
+        address                 0x085
+        access_mode RW
+        mask    DSLATT          0xfc    /* PCI latency timer (non-ultra2) */
+        bit     HADDLDSEL1      0x02    /* Host Address Load Select Bits */
+        bit     HADDLDSEL0      0x01
+}
+
 /*
- * Bus On/Off Time (p. 3-44)
+ * Bus On/Off Time (p. 3-44) aic7770 only
  */
 register BUSTIME {
 	address			0x085
@@ -693,6 +712,7 @@ register BUSSPD {
 	mask	STBOFF		0x38
 	mask	STBON		0x07
 	mask	DFTHRSH_100	0xc0
+        mask    DFTHRSH_75      0x80
 }
 
 /* aic7850/55/60/70/80/95 only */
@@ -748,7 +768,7 @@ register HCNT {
 
 /*
  * SCB Pointer (p. 3-49)
- * Gate one of the four SCBs into the SCBARRAY window.
+ * Gate one of the SCBs into the SCBARRAY window.
  */
 register SCBPTR {
 	address			0x090
@@ -770,11 +790,15 @@ register INTSTAT {
 	mask	SEND_REJECT	0x10|SEQINT	/* sending a message reject */
 	mask	NO_IDENT	0x20|SEQINT	/* no IDENTIFY after reconnect*/
 	mask	NO_MATCH	0x30|SEQINT	/* no cmd match for reconnect */
-	mask	UPDATE_TMSG_REQ	0x60|SEQINT	/* Update TMSG_REQ values */
-	mask	BAD_STATUS	0x70|SEQINT	/* Bad status from target */
-	mask	RESIDUAL	0x80|SEQINT	/* Residual byte count != 0 */
-	mask	TRACE_POINT	0x90|SEQINT
-	mask	HOST_MSG_LOOP	0xa0|SEQINT	/*
+        mask    IGN_WIDE_RES    0x40|SEQINT     /* Complex IGN Wide Res Msg */
+        mask    PDATA_REINIT    0x50|SEQINT     /*
+                                                 * Returned to data phase
+                                                 * that requires data
+                                                 * transfer pointers to be
+                                                 * recalculated from the
+                                                 * transfer residual.
+                                                 */
+        mask    HOST_MSG_LOOP   0x60|SEQINT     /*
 						 * The bus is ready for the
 						 * host to perform another
 						 * message transaction.  This
@@ -783,22 +807,37 @@ register INTSTAT {
 						 * that require a kernel based
 						 * message state engine.
 						 */
-	mask	PERR_DETECTED	0xb0|SEQINT	/*
+        mask    BAD_STATUS      0x70|SEQINT     /* Bad status from target */
+        mask    PERR_DETECTED   0x80|SEQINT     /*
 						 * Either the phase_lock
 						 * or inb_next routine has
 						 * noticed a parity error.
 						 */
-	mask	TRACEPOINT	0xd0|SEQINT
-	mask	MSGIN_PHASEMIS	0xe0|SEQINT	/*
-						 * Target changed phase on us
-						 * when we were expecting
-						 * another msgin byte.
-						 */
-	mask	DATA_OVERRUN	0xf0|SEQINT	/*
+        mask    DATA_OVERRUN    0x90|SEQINT     /*
 						 * Target attempted to write
 						 * beyond the bounds of its
 						 * command.
+                                                 */
+        mask    MKMSG_FAILED    0xa0|SEQINT     /*
+                                                 * Target completed command
+                                                 * without honoring our ATN
+                                                 * request to issue a message. 
 						 */
+        mask    MISSED_BUSFREE  0xb0|SEQINT     /*
+                                                 * The sequencer never saw
+                                                 * the bus go free after
+                                                 * either a command complete
+                                                 * or disconnect message.
+                                                 */
+        mask    SCB_MISMATCH    0xc0|SEQINT     /*
+                                                 * Downloaded SCB's tag does
+                                                 * not match the entry we
+                                                 * intended to download.
+                                                 */
+        mask    NO_FREE_SCB     0xd0|SEQINT     /*
+                                                 * get_free_or_disc_scb failed.
+                                                 */
+        mask    OUT_OF_RANGE    0xe0|SEQINT
 
 	mask	SEQINT_MASK	0xf0|SEQINT	/* SEQINT Status Codes */
 	mask	INT_PEND  (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
@@ -854,7 +893,8 @@ register DFSTATUS {
 	address			0x094
 	access_mode RO
 	bit	PRELOAD_AVAIL	0x80
-	bit	DWORDEMP	0x20
+        bit     DFCACHETH       0x40
+        bit     FIFOQWDEMP      0x20
 	bit	MREQPEND	0x10
 	bit	HDONE		0x08
 	bit	DFTHRESH	0x04
@@ -946,6 +986,7 @@ register SCSIPHASE {
 	bit	MSG_OUT_PHASE	0x04
 	bit	DATA_IN_PHASE	0x02
 	bit	DATA_OUT_PHASE	0x01
+        mask    DATA_PHASE_MASK 0x03
 }
 
 /*
@@ -962,35 +1003,19 @@ register SFUNCT {
  */
 scb {
 	address			0x0a0
-	SCB_CONTROL {
-		size	1
-		bit	TARGET_SCB	0x80
-		bit	DISCENB         0x40
-		bit	TAG_ENB		0x20
-		bit	MK_MESSAGE      0x10
-		bit	ULTRAENB	0x08
-		bit	DISCONNECTED	0x04
-		mask	SCB_TAG_TYPE	0x03
-	}
-	SCB_TCL {
-		size	1
-		bit	SELBUSB		0x08
-		mask	TID		0xf0
-		mask	LID		0x07
+        SCB_CDB_PTR {
+                size    4
+                alias   SCB_RESIDUAL_DATACNT
+                alias   SCB_CDB_STORE
+                alias   SCB_TARGET_INFO
 	}
-	SCB_TARGET_STATUS {
-		size	1
-	}
-	SCB_SGCOUNT {
-		size	1
-	}
-	SCB_SGPTR {
+        SCB_RESIDUAL_SGPTR {
 		size	4
 	}
-	SCB_RESID_SGCNT {
+        SCB_SCSI_STATUS {
 		size	1
 	}
-	SCB_RESID_DCNT	{
+        SCB_CDB_STORE_PAD {
 		size	3
 	}
 	SCB_DATAPTR {
@@ -998,24 +1023,44 @@ scb {
 	}
 	SCB_DATACNT {
 		/*
-		 * Really only 3 bytes, but padded to make
-		 * the kernel's job easier.
+                 * The last byte is really the high address bits for
+                 * the data address.
 		 */
 		size	4
+                bit     SG_LAST_SEG             0x80    /* In the fourth byte */
+                mask    SG_HIGH_ADDR_BITS       0x7F    /* In the fourth byte */
 	}
-	SCB_CMDPTR {
-		alias	SCB_TARGET_PHASES
-		bit	TARGET_DATA_IN	0x1	/* In the second byte */
+        SCB_SGPTR {
 		size	4
+                bit     SG_RESID_VALID  0x04    /* In the first byte */
+                bit     SG_FULL_RESID   0x02    /* In the first byte */
+                bit     SG_LIST_NULL    0x01    /* In the first byte */
+        }
+        SCB_CONTROL {
+                size    1
+                bit     TARGET_SCB                      0x80
+                bit     DISCENB                         0x40
+                bit     TAG_ENB                         0x20
+                bit     MK_MESSAGE                      0x10
+                bit     ULTRAENB                        0x08
+                bit     DISCONNECTED                    0x04
+                mask    SCB_TAG_TYPE                    0x03
 	}
-	SCB_CMDLEN {
-		alias	SCB_INITIATOR_TAG
+        SCB_SCSIID {
+                size    1
+                bit     TWIN_CHNLB                      0x80
+                mask    TWIN_TID                        0x70
+                mask    TID                             0xf0
+                mask    OID                             0x0f
+        }
+        SCB_LUN {
+                mask    LID                             0xff
 		size	1
 	}
 	SCB_TAG {
 		size	1
 	}
-	SCB_NEXT {
+        SCB_CDB_LEN {
 		size	1
 	}
 	SCB_SCSIRATE {
@@ -1024,22 +1069,20 @@ scb {
 	SCB_SCSIOFFSET {
 		size	1
 	}
-	SCB_SPARE	{
-		size	3
+        SCB_NEXT {
+                size    1
 	}
-	SCB_CMDSTORE	{
+        SCB_64_SPARE {
 		size	16
 	}
-	SCB_CMDSTORE_BUSADDR {
-		size	4
-	}
-	SCB_64BYTE_SPARE {
-		size	12
+        SCB_64_BTT {
+                size    16
 	}
 }
 
-const	SCB_32BYTE_SIZE	28
-const	SCB_64BYTE_SIZE	48
+const   SCB_UPLOAD_SIZE         32
+const   SCB_DOWNLOAD_SIZE       32
+const   SCB_DOWNLOAD_SIZE_64    48
 
 const	SG_SIZEOF	0x08		/* sizeof(struct ahc_dma) */
 
@@ -1085,7 +1128,7 @@ register CCSGCTL {
 	address			0x0EB
 	bit	CCSGDONE	0x80
 	bit	CCSGEN		0x08
-	bit	FLAG		0x02
+        bit     SG_FETCH_NEEDED 0x02    /* Bit used for software state */
 	bit	CCSGRESET	0x01
 }
 
@@ -1166,14 +1209,23 @@ register DFF_THRSH {
 	mask	WR_DFTHRSH_MAX	0x70
 }
 
-register SG_CACHEPTR {
-	access_mode RW
+register SG_CACHE_PRE {
+        access_mode WO
 	address			0x0fc
-	mask	SG_USER_DATA	0xfc
+        mask    SG_ADDR_MASK    0xf8
+        bit     ODD_SEG         0x04
 	bit	LAST_SEG	0x02
 	bit	LAST_SEG_DONE	0x01
 }
 
+register SG_CACHE_SHADOW {
+        access_mode RO
+        address                 0x0fc
+        mask    SG_ADDR_MASK    0xf8
+        bit     ODD_SEG         0x04
+        bit     LAST_SEG        0x02
+        bit     LAST_SEG_DONE   0x01
+}
 /* ---------------------- Scratch RAM Offsets ------------------------- */
 /* These offsets are either to values that are initialized by the board's
  * BIOS or are specified by the sequencer code.
@@ -1195,21 +1247,45 @@ scratch_ram {
 	/*
 	 * 1 byte per target starting at this address for configuration values
 	 */
-	TARG_SCSIRATE {
-		alias		CMDSIZE_TABLE
+        BUSY_TARGETS {
+                alias           TARG_SCSIRATE
 		size		16
 	}
 	/*
-	 * Bit vector of targets that have ULTRA enabled.
+         * Bit vector of targets that have ULTRA enabled as set by
+         * the BIOS.  The Sequencer relies on a per-SCB field to
+         * control whether to enable Ultra transfers or not.  During
+         * initialization, we read this field and reuse it for 2
+         * entries in the busy target table.
 	 */
 	ULTRA_ENB {
+                alias           CMDSIZE_TABLE
 		size		2
 	}
 	/*
-	 * Bit vector of targets that have disconnection disabled.
+         * Bit vector of targets that have disconnection disabled as set by
+         * the BIOS.  The Sequencer relies in a per-SCB field to control the
+         * disconnect priveldge.  During initialization, we read this field
+         * and reuse it for 2 entries in the busy target table.
 	 */
 	DISC_DSB {
 		size		2
+        }
+        CMDSIZE_TABLE_TAIL {
+                size            4
+        }
+        /*
+         * Partial transfer past cacheline end to be
+         * transferred using an extra S/G.
+         */
+        MWI_RESIDUAL {
+                size            1
+        }
+        /*
+         * SCBID of the next SCB to be started by the controller.
+         */
+        NEXT_QUEUED_SCB {
+                size            1
 	}
 	/*
 	 * Single byte buffer used to designate the type or message
@@ -1235,7 +1311,7 @@ scratch_ram {
 	SEQ_FLAGS {
 		size		1
 		bit	IDENTIFY_SEEN		0x80
-		bit	SCBPTR_VALID		0x40
+                bit     TARGET_CMD_IS_TAGGED    0x40
 		bit	DPHASE			0x20
 		/* Target flags */
 		bit	TARG_CMD_PENDING	0x10
@@ -1249,17 +1325,12 @@ scratch_ram {
 	 * target/channel/lun of a
 	 * reconnecting target
 	 */
-	SAVED_TCL {
+        SAVED_SCSIID {
 		size		1
 	}
-	/* Working value of the number of SG segments left */
-	SG_COUNT {
+        SAVED_LUN {
 		size		1
 	}
-	/* Working value of SG pointer */
-	SG_NEXT	{
-		size		4
-	}
 	/*
 	 * The last bus phase as seen by the sequencer. 
 	 */
@@ -1300,23 +1371,25 @@ scratch_ram {
 		size		1
 	}
 	/*
-	 * Address of the hardware scb array in the host.
+         * head of list of SCBs that have
+         * completed but have not been
+         * put into the qoutfifo.
 	 */
-	HSCB_ADDR {
-		size		4
+        COMPLETE_SCBH {
+                size            1
 	}
 	/*
-	 * Address of the 256 byte array storing the SCBID of outstanding
-	 * untagged SCBs indexed by TCL.
+         * Address of the hardware scb array in the host.
 	 */
-	SCBID_ADDR {
+        HSCB_ADDR {
 		size		4
 	}
 	/*
-	 * Address of the array of command descriptors used to store
-	 * information about incoming selections.
+         * Base address of our shared data with the kernel driver in host
+         * memory.  This includes the qoutfifo and target mode
+         * incoming command queue.
 	 */
-	TMODE_CMDADDR {
+        SHARED_DATA_ADDR {
 		size		4
 	}
 	KERNEL_QINPOS {
@@ -1363,23 +1436,6 @@ scratch_ram {
 	}
 
 	/*
-	 * Number of times we have filled the CCSGRAM with prefetched
-	 * SG elements.
-	 */
-	PREFETCH_CNT {
-		size		1
-	}
-
-	/*
-	 * Interrupt kernel for a message to this target on
-	 * the next transaction.  This is usually used for
-	 * negotiation requests.
-	 */
-	TARGET_MSG_REQUEST {
-		size		2
-	}
-
-	/*
 	 * Sequences the kernel driver has okayed for us.  This allows
 	 * the driver to do things like prevent initiator or target
 	 * operations.
@@ -1409,6 +1465,10 @@ scratch_ram {
 		size		1
 	}
 
+        SEQ_FLAGS2 {
+                size            1
+                bit     SCB_DMA         0x01
+        }
 	/*
 	 * These are reserved registers in the card's scratch ram.  Some of
 	 * the values are specified in the AHA2742 technical reference manual
@@ -1422,6 +1482,12 @@ scratch_ram {
 		bit	ENSPCHK		0x20
 		mask	HSCSIID		0x07	/* our SCSI ID */
 		mask	HWSCSIID	0x0f	/* our SCSI ID if Wide Bus */
+        }
+        INTDEF {
+                address         0x05c
+                size            1
+                bit     EDGE_TRIG       0x80
+                mask    VECTOR          0x0f
 	}
 	HOSTCONF {
 		address		0x05d
@@ -1443,17 +1509,13 @@ scratch_ram {
 	}
 }
 
+const TID_SHIFT         4
 const SCB_LIST_NULL	0xff
 const TARGET_CMD_CMPLT	0xfe
 
 const CCSGADDR_MAX	0x80
 const CCSGRAM_MAXSEGS	16
 
-/* Offsets into the SCBID array where different data is stored */
-const QOUTFIFO_OFFSET		0
-const QINFIFO_OFFSET		1
-const UNTAGGEDSCB_OFFSET	2
-
 /* WDTR Message values */
 const BUS_8_BIT			0x00
 const BUS_16_BIT		0x01
@@ -1468,20 +1530,22 @@ const HOST_MSG			0xff
 /* Target mode command processing constants */
 const CMD_GROUP_CODE_SHIFT	0x05
 
-const TCL_TARGET_SHIFT		4
-/* The update interval must be a power of 2 */
-const TQINFIFO_UPDATE_CNT	32
-
 const STATUS_BUSY		0x08
 const STATUS_QUEUE_FULL		0x28
+const SCB_TARGET_PHASES         0
+const SCB_TARGET_DATA_DIR       1
+const SCB_TARGET_STATUS         2
+const SCB_INITIATOR_TAG         3
+const TARGET_DATA_IN            1
 
 /*
  * Downloaded (kernel inserted) constants
  */
-
-/*
- * Number of command descriptors in the command descriptor array.
- * No longer used, but left here as an example for how downloaded
- * constantants can be defined.
-const TMODE_NUMCMDS	download
- */
+/* Offsets into the SCBID array where different data is stored */
+const QOUTFIFO_OFFSET download
+const QINFIFO_OFFSET download
+const CACHESIZE_MASK download
+const INVERTED_CACHESIZE_MASK download
+const SG_PREFETCH_CNT download
+const SG_PREFETCH_ALIGN_MASK download
+const SG_PREFETCH_ADDR_MASK download
diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.seq b/sys/dev/microcode/aic7xxx/aic7xxx.seq
index 152194f9815..8f753eb1902 100644
--- a/sys/dev/microcode/aic7xxx/aic7xxx.seq
+++ b/sys/dev/microcode/aic7xxx/aic7xxx.seq
@@ -1,7 +1,8 @@
+/* $OpenBSD: aic7xxx.seq,v 1.9 2002/02/16 04:36:33 smurph Exp $ */
 /*
  * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
  *
- * Copyright (c) 1994-2000 Justin Gibbs.
+ * Copyright (c) 1994-2001 Justin Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,7 +15,7 @@
  *    derived from this software without specific prior written permission.
  *
  * Alternatively, this software may be distributed under the terms of the
- * the GNU Public License ("GPL").
+ * GNU Public License ("GPL").
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -28,14 +29,13 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.seq,v 1.93 2000/01/07 23:08:20 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.seq,v 1.119 2001/08/05 22:20:12 gibbs Exp $
  */
 
+VERSION = "$Id: aic7xxx.seq,v 1.9 2002/02/16 04:36:33 smurph Exp $"
+
 #include <dev/microcode/aic7xxx/aic7xxx.reg>
 #include <scsi/scsi_message.h>
-/*
-#include <cam/scsi/scsi_message.h>
-*/
 
 /*
  * A few words on the waiting SCB list:
@@ -55,172 +55,122 @@
  * automatically consume the entries.
  */
 
-reset:
-	clr	SCSISIGO;		/* De-assert BSY */
-	mvi	MSG_OUT, MSG_NOOP;	/* No message to send */
-	and	SXFRCTL1, ~BITBUCKET;
-	/* Always allow reselection */
-	and	SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ_TEMPLATE;
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		/* Ensure that no DMA operations are in progress */
-		clr	CCSGCTL;
-		clr	CCSCBCTL;
-	}
-
+bus_free_sel:
+        /*
+         * Turn off the selection hardware.  We need to reset the
+         * selection request in order to perform a new selection.
+         */
+        and     SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
+        and     SIMODE1, ~ENBUSFREE;
 poll_for_work:
 	call	clear_target_state;
 	and	SXFRCTL0, ~SPIOEN;
-	if ((ahc->features & AHC_QUEUE_REGS) == 0) {
-		mov	A, QINPOS;
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                clr     SCSIBUSL;
+        }
+        test    SCSISEQ, ENSELO jnz poll_for_selection;
+        if ((ahc->features & AHC_TWIN) != 0) {
+                xor     SBLKCTL,SELBUSB;        /* Toggle to the other bus */
+                test    SCSISEQ, ENSELO         jnz poll_for_selection;
 	}
+        cmp     WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
 poll_for_work_loop:
-	if ((ahc->features & AHC_QUEUE_REGS) == 0) {
-		and	SEQCTL, ~PAUSEDIS;
-	}
-	test	SSTAT0, SELDO|SELDI	jnz selection;
-	test	SCSISEQ, ENSELO	jnz poll_for_work_loop;
 	if ((ahc->features & AHC_TWIN) != 0) {
-		/*
-		 * Twin channel devices cannot handle things like SELTO
-		 * interrupts on the "background" channel.  So, if we
-		 * are selecting, keep polling the current channel util
-		 * either a selection or reselection occurs.
-		 */
 		xor	SBLKCTL,SELBUSB;	/* Toggle to the other bus */
-		test	SSTAT0, SELDO|SELDI	jnz selection;
-		test	SCSISEQ, ENSELO	jnz poll_for_work;
-		xor	SBLKCTL,SELBUSB;	/* Toggle back */
-	}
-	cmp	WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
+        }
+        test    SSTAT0, SELDO|SELDI     jnz selection;
 test_queue:
 	/* Has the driver posted any work for us? */
+BEGIN_CRITICAL
 	if ((ahc->features & AHC_QUEUE_REGS) != 0) {
 		test	QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
-		mov	NONE, SNSCB_QOFF;
-		inc	QINPOS;
 	} else {
-		or	SEQCTL, PAUSEDIS;
+                mov     A, QINPOS;
 		cmp	KERNEL_QINPOS, A je poll_for_work_loop;
-		inc	QINPOS;
-		and	SEQCTL, ~PAUSEDIS;
 	}
+        mov     ARG_1, NEXT_QUEUED_SCB;
 
-/*
- * We have at least one queued SCB now and we don't have any 
- * SCBs in the list of SCBs awaiting selection.  If we have
- * any SCBs available for use, pull the tag from the QINFIFO
- * and get to work on it.
- */
+        /*
+         * We have at least one queued SCB now and we don't have any 
+         * SCBs in the list of SCBs awaiting selection.  Allocate a
+         * card SCB for the host's SCB and get to work on it.
+         */
 	if ((ahc->flags & AHC_PAGESCBS) != 0) {
 		mov	ALLZEROS	call	get_free_or_disc_scb;
-	}
-
-dequeue_scb:
-	add	A, -1, QINPOS;
-	mvi	QINFIFO_OFFSET call fetch_byte;
-
-	if ((ahc->flags & AHC_PAGESCBS) == 0) {
+        } else {
 		/* In the non-paging case, the SCBID == hardware SCB index */
-		mov	SCBPTR, RETURN_2;
+                mov     SCBPTR, ARG_1;
 	}
+        or      SEQ_FLAGS2, SCB_DMA;
+END_CRITICAL
 dma_queued_scb:
-/*
- * DMA the SCB from host ram into the current SCB location.
- */
+        /*
+         * DMA the SCB from host ram into the current SCB location.
+         */
 	mvi	DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
-	mov	RETURN_2	 call dma_scb;
-
-/*
- * Preset the residual fields in case we never go through a data phase.
- * This isn't done by the host so we can avoid a DMA to clear these
- * fields for the normal case of I/O that completes without underrun
- * or overrun conditions.
- */
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		bmov	SCB_RESID_DCNT, SCB_DATACNT, 3;
-	} else {
-		mov	SCB_RESID_DCNT[0],SCB_DATACNT[0];
-		mov	SCB_RESID_DCNT[1],SCB_DATACNT[1];
-		mov	SCB_RESID_DCNT[2],SCB_DATACNT[2];
+        mov     ARG_1   call dma_scb;
+        /*
+         * Check one last time to see if this SCB was canceled
+         * before we completed the DMA operation.  If it was,
+         * the QINFIFO next pointer will not match our saved
+         * value.
+         */
+        mov     A, ARG_1;
+BEGIN_CRITICAL
+        cmp     NEXT_QUEUED_SCB, A jne abort_qinscb;
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                cmp     SCB_TAG, A je . + 2;
+                mvi     SCB_MISMATCH call set_seqint;
 	}
-	mov	SCB_RESID_SGCNT, SCB_SGCOUNT;
-
-start_scb:
-	/*
-	 * Place us on the waiting list in case our selection
-	 * doesn't win during bus arbitration.
-	 */
+        mov     NEXT_QUEUED_SCB, SCB_NEXT;
 	mov	SCB_NEXT,WAITING_SCBH;
 	mov	WAITING_SCBH, SCBPTR;
+        if ((ahc->features & AHC_QUEUE_REGS) != 0) {
+                mov     NONE, SNSCB_QOFF;
+        } else {
+                inc     QINPOS;
+        }
+        and     SEQ_FLAGS2, ~SCB_DMA;
+END_CRITICAL
 start_waiting:
 	/*
-	 * Pull the first entry off of the waiting SCB list.
+         * Start the first entry on the waiting SCB list.
 	 */
 	mov	SCBPTR, WAITING_SCBH;
 	call	start_selection;
-	jmp	poll_for_work;
-
-start_selection:
-	if ((ahc->features & AHC_TWIN) != 0) {
-		and	SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
-		and	A,SELBUSB,SCB_TCL;	/* Get new channel bit */
-		or	SINDEX,A;
-		mov	SBLKCTL,SINDEX;		/* select channel */
-	}
-initialize_scsiid:
-	mov	SINDEX, SCSISEQ_TEMPLATE;
-	if ((ahc->flags & AHC_TARGETMODE) != 0) {
-		test	SCB_CONTROL, TARGET_SCB jz . + 4;
-		if ((ahc->features & AHC_ULTRA2) != 0) {
-			mov	SCSIID_ULTRA2, SCB_CMDPTR[2];
-		} else {
-			mov	SCSIID, SCB_CMDPTR[2];
-		}
-		or	SINDEX, TEMODE;
-		jmp	initialize_scsiid_fini;
-	}
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		and	A, TID, SCB_TCL;	/* Get target ID */
-		and	SCSIID_ULTRA2, OID;	/* Clear old target */
-		or	SCSIID_ULTRA2, A;
-	} else {
-		and	A, TID, SCB_TCL;	/* Get target ID */
-		and	SCSIID, OID;		/* Clear old target */
-		or	SCSIID, A;
-	}
-initialize_scsiid_fini:
-	mov	SCSISEQ, SINDEX ret;
 
-/*
- * Initialize transfer settings and clear the SCSI channel.
- * SINDEX should contain any additional bit's the client wants
- * set in SXFRCTL0.  We also assume that the current SCB is
- * a valid SCB for the target we wish to talk to.
- */
-initialize_channel:
-	or	SXFRCTL0, CLRSTCNT|CLRCHN, SINDEX;
-set_transfer_settings:
-	if ((ahc->features & AHC_ULTRA) != 0) {
-		test	SCB_CONTROL, ULTRAENB jz . + 2;
-		or	SXFRCTL0, FAST20;
-	} 
-/*
- * Initialize SCSIRATE with the appropriate value for this target.
- */
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		bmov	SCSIRATE, SCB_SCSIRATE, 2 ret;
-	} else {
-		mov	SCSIRATE, SCB_SCSIRATE ret;
-	}
+poll_for_selection:
+        /*
+         * Twin channel devices cannot handle things like SELTO
+         * interrupts on the "background" channel.  So, while
+         * selecting, keep polling the current channel until
+         * either a selection or reselection occurs.
+         */
+        test    SSTAT0, SELDO|SELDI     jz poll_for_selection;
 
 selection:
+        /*
+         * We aren't expecting a bus free, so interrupt
+         * the kernel driver if it happens.
+         */
+        mvi     CLRSINT1,CLRBUSFREE;
+        if ((ahc->features & AHC_DT) == 0) {
+                or      SIMODE1, ENBUSFREE;
+        }
+
+        /*
+         * Guard against a bus free after (re)selection
+         * but prior to enabling the busfree interrupt.  SELDI
+         * and SELDO will be cleared in that case.
+         */
+        test    SSTAT0, SELDI|SELDO     jz bus_free_sel;
 	test	SSTAT0,SELDO	jnz select_out;
-	mvi	CLRSINT0, CLRSELDI;
 select_in:
-	if ((ahc->flags & AHC_TARGETMODE) != 0) {
-		if ((ahc->flags & AHC_INITIATORMODE) != 0) {
+        if ((ahc->flags & AHC_TARGETROLE) != 0) {
+                if ((ahc->flags & AHC_INITIATORROLE) != 0) {
 			test	SSTAT0, TARGET	jz initiator_reselect;
 		}
+                mvi     CLRSINT0, CLRSELDI;
 
 		/*
 		 * We've just been selected.  Assert BSY and
@@ -228,7 +178,6 @@ select_in:
 		 * from the target.
 		 */
 		mvi	SCSISIGO, P_MESGOUT|BSYO;
-		mvi	CLRSINT1, CLRBUSFREE;
 
 		/*
 		 * Setup the DMA for sending the identify and
@@ -239,47 +188,40 @@ select_in:
 		mov     A, TQINPOS;
 		if ((ahc->features & AHC_CMD_CHAN) != 0) {
 			mvi	DINDEX, CCHADDR;
-			mvi	TMODE_CMDADDR call set_32byte_addr;
+                        mvi     SHARED_DATA_ADDR call set_32byte_addr;
 			mvi	CCSCBCTL, CCSCBRESET;
 		} else {
 			mvi	DINDEX, HADDR;
-			mvi	TMODE_CMDADDR call set_32byte_addr;
+                        mvi     SHARED_DATA_ADDR call set_32byte_addr;
 			mvi	DFCNTRL, FIFORESET;
 		}
 
 		/* Initiator that selected us */
-		and	SAVED_TCL, SELID_MASK, SELID;
-		if ((ahc->features & AHC_CMD_CHAN) != 0) {
-			mov	CCSCBRAM, SAVED_TCL;
-		} else {
-			mov	DFDAT, SAVED_TCL;
-		}
-
+                and     SAVED_SCSIID, SELID_MASK, SELID;
 		/* The Target ID we were selected at */
-		if ((ahc->features & AHC_CMD_CHAN) != 0) {
-			if ((ahc->features & AHC_MULTI_TID) != 0) {
-				and	CCSCBRAM, OID, TARGIDIN;
-			} else if ((ahc->features & AHC_ULTRA2) != 0) {
-				and	CCSCBRAM, OID, SCSIID_ULTRA2;
-			} else {
-				and	CCSCBRAM, OID, SCSIID;
-			}
+                if ((ahc->features & AHC_MULTI_TID) != 0) {
+                        and     A, OID, TARGIDIN;
+                } else if ((ahc->features & AHC_ULTRA2) != 0) {
+                        and     A, OID, SCSIID_ULTRA2;
+                } else {
+                        and     A, OID, SCSIID;
+                }
+                or      SAVED_SCSIID, A;
+                if ((ahc->features & AHC_TWIN) != 0) {
+                        test    SBLKCTL, SELBUSB jz . + 2;
+                        or      SAVED_SCSIID, TWIN_CHNLB;
+                }
+                if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                        mov     CCSCBRAM, SAVED_SCSIID;
 		} else {
-			if ((ahc->features & AHC_MULTI_TID) != 0) {
-				and	DFDAT, OID, TARGIDIN;
-			} else if ((ahc->features & AHC_ULTRA2) != 0) {
-				and	DFDAT, OID, SCSIID_ULTRA2;
-			} else {
-				and	DFDAT, OID, SCSIID;
-			}
-		}
-
-		/* No tag yet */
-		mvi	INITIATOR_TAG, SCB_LIST_NULL;
+                        mov     DFDAT, SAVED_SCSIID;
+                }
 
 		/*
 		 * If ATN isn't asserted, the target isn't interested
 		 * in talking to us.  Go directly to bus free.
+                 * XXX SCSI-1 may require us to assume lun 0 if
+                 * ATN is false.
 		 */
 		test	SCSISIGI, ATNI	jz	target_busfree;
 
@@ -294,7 +236,6 @@ select_in:
 		 * Our first message must be one of IDENTIFY, ABORT, or
 		 * BUS_DEVICE_RESET.
 		 */
-		/* XXX May need to be more lax here for older initiators... */
 		test	DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
 		/* Store for host */
 		if ((ahc->features & AHC_CMD_CHAN) != 0) {
@@ -344,6 +285,10 @@ select_in:
 			mov	DFDAT, DINDEX;
 		}
 		mov	INITIATOR_TAG, DINDEX;
+                or      SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
+                test    SCSISIGI, ATNI  jz . + 2;
+                /* Initiator still wants to give us messages */
+                call    target_inb;
 		jmp	ident_messages_done;
 
 		/*
@@ -351,8 +296,7 @@ select_in:
 		 * run it's own target mode message state engine.
 		 */
 host_target_message_loop:
-		mvi	INTSTAT, HOST_MSG_LOOP;
-		nop;
+                mvi     HOST_MSG_LOOP call set_seqint;
 		cmp	RETURN_1, EXIT_MSG_LOOP	je target_ITloop;
 		test	SSTAT0, SPIORDY jz .;
 		jmp	host_target_message_loop;
@@ -362,11 +306,11 @@ ident_messages_done:
 		if ((ahc->features & AHC_HS_MAILBOX) != 0) {
 			and	A, HOST_TQINPOS, HS_MAILBOX;
 		} else {
-		mov	A, KERNEL_TQINPOS;
+                        mov     A, KERNEL_TQINPOS;
 		}
 		cmp	TQINPOS, A jne tqinfifo_has_space;
 		mvi	P_STATUS|BSYO call change_phase;
-		cmp	INITIATOR_TAG, SCB_LIST_NULL je . + 3;
+                test    SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
 		mvi	STATUS_QUEUE_FULL call target_outb;
 		jmp	target_busfree_wait;
 		mvi	STATUS_BUSY call target_outb;
@@ -379,48 +323,110 @@ tqinfifo_has_space:
 			mvi	DFDAT, SCB_LIST_NULL;
 		}
 		or	SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN;
-		test	SCSISIGI, ATNI	jnz target_mesgout_pending_msg;
+                test    SCSISIGI, ATNI  jnz target_mesgout_pending;
 		jmp	target_ITloop;
-		
-/*
- * We carefully toggle SPIOEN to allow us to return the 
- * message byte we receive so it can be checked prior to
- * driving REQ on the bus for the next byte.
- */
-target_inb:
-		/*
-		 * Drive REQ on the bus by enabling SCSI PIO.
-		 */
-		or	SXFRCTL0, SPIOEN;
-		/* Wait for the byte */
-		test	SSTAT0, SPIORDY jz .;
-		/* Prevent our read from triggering another REQ */
-		and	SXFRCTL0, ~SPIOEN;
-		/* Save latched contents */
-		mov	DINDEX, SCSIDATL ret;
-	}
+        }
 
-if ((ahc->flags & AHC_INITIATORMODE) != 0) {
+if ((ahc->flags & AHC_INITIATORROLE) != 0) {
 /*
  * Reselection has been initiated by a target. Make a note that we've been
  * reselected, but haven't seen an IDENTIFY message from the target yet.
  */
 initiator_reselect:
-	/* XXX test for and handle ONE BIT condition */
-	and	SAVED_TCL, SELID_MASK, SELID;
-	if ((ahc->features & AHC_TWIN) != 0) {
-		test	SBLKCTL, SELBUSB	jz . + 2;
-		or	SAVED_TCL, SELBUSB;
-	}
-	or	SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
-	mvi	CLRSINT1,CLRBUSFREE;
-	or	SIMODE1, ENBUSFREE;		/*
-						 * We aren't expecting a
-						 * bus free, so interrupt
-						 * the kernel driver if it
-						 * happens.
-						 */
-	jmp	ITloop;
+        /* XXX test for and handle ONE BIT condition */
+        or      SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
+        and     SAVED_SCSIID, SELID_MASK, SELID;
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                and     A, OID, SCSIID_ULTRA2;
+        } else {
+                and     A, OID, SCSIID;
+        }
+        or      SAVED_SCSIID, A;
+        if ((ahc->features & AHC_TWIN) != 0) {
+                test    SBLKCTL, SELBUSB        jz . + 2;
+                or      SAVED_SCSIID, TWIN_CHNLB;
+        }
+        mvi     CLRSINT0, CLRSELDI;
+        jmp     ITloop;
+}
+
+abort_qinscb:
+        call    add_scb_to_free_list;
+        jmp     poll_for_work_loop;
+
+start_selection:
+        /*
+         * If bus reset interrupts have been disabled (from a previous
+         * reset), re-enable them now.  Resets are only of interest
+         * when we have outstanding transactions, so we can safely
+         * defer re-enabling the interrupt until, as an initiator,
+         * we start sending out transactions again.
+         */
+        test    SIMODE1, ENSCSIRST      jnz . + 3;
+        mvi     CLRSINT1, CLRSCSIRSTI;
+        or      SIMODE1, ENSCSIRST;
+        if ((ahc->features & AHC_TWIN) != 0) {
+                and     SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
+                test    SCB_SCSIID, TWIN_CHNLB jz . + 2;
+                or      SINDEX, SELBUSB;
+                mov     SBLKCTL,SINDEX;         /* select channel */
+        }
+initialize_scsiid:
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                mov     SCSIID_ULTRA2, SCB_SCSIID;
+        } else if ((ahc->features & AHC_TWIN) != 0) {
+                and     SCSIID, TWIN_TID|OID, SCB_SCSIID;
+        } else {
+                mov     SCSIID, SCB_SCSIID;
+        }
+        if ((ahc->flags & AHC_TARGETROLE) != 0) {
+                mov     SINDEX, SCSISEQ_TEMPLATE;
+                test    SCB_CONTROL, TARGET_SCB jz . + 2;
+                or      SINDEX, TEMODE;
+                mov     SCSISEQ, SINDEX ret;
+        } else {
+                mov     SCSISEQ, SCSISEQ_TEMPLATE ret;
+        }
+
+/*
+ * Initialize transfer settings and clear the SCSI channel.
+ * SINDEX should contain any additional bit's the client wants
+ * set in SXFRCTL0.  We also assume that the current SCB is
+ * a valid SCB for the target we wish to talk to.
+ */
+initialize_channel:
+        or      SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
+set_transfer_settings:
+        if ((ahc->features & AHC_ULTRA) != 0) {
+                test    SCB_CONTROL, ULTRAENB jz . + 2;
+                or      SXFRCTL0, FAST20;
+        } 
+        /*
+         * Initialize SCSIRATE with the appropriate value for this target.
+         */
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                bmov    SCSIRATE, SCB_SCSIRATE, 2 ret;
+        } else {
+                mov     SCSIRATE, SCB_SCSIRATE ret;
+        }
+
+if ((ahc->flags & AHC_TARGETROLE) != 0) {
+/*
+ * We carefully toggle SPIOEN to allow us to return the 
+ * message byte we receive so it can be checked prior to
+ * driving REQ on the bus for the next byte.
+ */
+target_inb:
+        /*
+         * Drive REQ on the bus by enabling SCSI PIO.
+         */
+        or      SXFRCTL0, SPIOEN;
+        /* Wait for the byte */
+        test    SSTAT0, SPIORDY jz .;
+        /* Prevent our read from triggering another REQ */
+        and     SXFRCTL0, ~SPIOEN;
+        /* Save latched contents */
+        mov     DINDEX, SCSIDATL ret;
 }
 
 /*
@@ -432,12 +438,13 @@ initiator_reselect:
 select_out:
 	/* Turn off the selection hardware */
 	and	SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
-/*and	SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP,SCSISEQ_TEMPLATE;*/
 	mvi	CLRSINT0, CLRSELDO;
 	mov	SCBPTR, WAITING_SCBH;
 	mov	WAITING_SCBH,SCB_NEXT;
-	mov	SAVED_TCL, SCB_TCL;
-	if ((ahc->flags & AHC_TARGETMODE) != 0) {
+        mov     SAVED_SCSIID, SCB_SCSIID;
+        mov     SAVED_LUN, SCB_LUN;
+        call    initialize_channel;
+        if ((ahc->flags & AHC_TARGETROLE) != 0) {
 		test	SSTAT0, TARGET	jz initiator_select;
 
 		/*
@@ -446,13 +453,11 @@ select_out:
 		 * sending our identify messages.
 		 */
 		mvi	P_MESGIN|BSYO call change_phase;
-		mvi	CLRSINT1,CLRBUSFREE;
 
 		/*
 		 * Start out with a simple identify message.
 		 */
-		and	A, LID, SCB_TCL;
-		or	A, MSG_IDENTIFYFLAG call target_outb;
+                or      SCB_LUN, MSG_IDENTIFYFLAG call target_outb;
 
 		/*
 		 * If we are the result of a tagged command, send
@@ -460,16 +465,17 @@ select_out:
 		 */
 		test	SCB_CONTROL, TAG_ENB	jz . + 3;
 		mvi	MSG_SIMPLE_Q_TAG call target_outb;
-		mov	SCB_INITIATOR_TAG call target_outb;
-		mov	INITIATOR_TAG, SCB_INITIATOR_TAG;
+                mov     SCB_TARGET_INFO[SCB_INITIATOR_TAG] call target_outb;
 target_synccmd:
 		/*
 		 * Now determine what phases the host wants us
 		 * to go through.
 		 */
-		mov	SEQ_FLAGS, SCB_TARGET_PHASES;
+                mov     SEQ_FLAGS, SCB_TARGET_INFO[SCB_TARGET_PHASES];
 		
-
+                test    SCB_CONTROL, MK_MESSAGE jz target_ITloop;
+                mvi     P_MESGIN|BSYO call change_phase;
+                jmp     host_target_message_loop;
 target_ITloop:
 		/*
 		 * Start honoring ATN signals now that
@@ -485,21 +491,22 @@ target_ITloop:
 		 * on the state of NO_DISCONNECT.
 		 */
 		test	SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; 
+                mov     RETURN_1, ALLZEROS;
+                call    complete_target_cmd;
+                cmp     RETURN_1, CONT_MSG_LOOP jne .;
 		if ((ahc->flags & AHC_PAGESCBS) != 0) {
 			mov	ALLZEROS	call	get_free_or_disc_scb;
 		}
-		mov	RETURN_1, ALLZEROS;
-		call	complete_target_cmd;
-		cmp	RETURN_1, CONT_MSG_LOOP jne .;
 		mvi	DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
 		mov	SCB_TAG	 call dma_scb;
 		jmp	target_synccmd;
 
 target_mesgout:
 		mvi	SCSISIGO, P_MESGOUT|BSYO;
+target_mesgout_continue:
 		call	target_inb;
+target_mesgout_pending:
 		/* Local Processing goes here... */
-target_mesgout_pending_msg:
 		jmp	host_target_message_loop;
 		
 target_disconnect:
@@ -509,9 +516,13 @@ target_disconnect:
 		mvi	MSG_DISCONNECT call target_outb;
 
 target_busfree_wait:
-		/* Wait for preceeding I/O session to complete. */
+                /* Wait for preceding I/O session to complete. */
 		test	SCSISIGI, ACKI jnz .;
 target_busfree:
+                and     SIMODE1, ~ENBUSFREE;
+                if ((ahc->features & AHC_ULTRA2) != 0) {
+                        clr     SCSIBUSL;
+                }
 		clr	SCSISIGO;
 		mvi	LASTPHASE, P_BUSFREE;
 		call	complete_target_cmd;
@@ -537,12 +548,12 @@ target_cmdphase:
 		 * the first byte.
 		 */
 		shr	A, CMD_GROUP_CODE_SHIFT;
-		add	SINDEX, TARG_SCSIRATE, A;
+                add     SINDEX, CMDSIZE_TABLE, A;
 		mov	A, SINDIR;
 
 		test	A, 0xFF jz command_phase_done;
+                or      SXFRCTL0, SPIOEN;
 command_loop:
-		or	SXFRCTL0, SPIOEN;
 		test	SSTAT0, SPIORDY jz .;
 		cmp	A, 1 jne . + 2;
 		and	SXFRCTL0, ~SPIOEN;	/* Last Byte */
@@ -560,22 +571,21 @@ command_phase_done:
 
 target_dphase:
 		/*
-		 * Data direction flags are from the
-		 * perspective of the initiator.
+                 * Data phases on the bus are from the
+                 * perspective of the initiator.  The dma
+                 * code looks at LASTPHASE to determine the
+                 * data direction of the DMA.  Toggle it for
+                 * target transfers.
 		 */
-		test	SCB_TARGET_PHASES[1], TARGET_DATA_IN jz . + 4;
-		mvi	LASTPHASE, P_DATAOUT;
-		mvi	P_DATAIN|BSYO call change_phase;
-		jmp	. + 3;
-		mvi	LASTPHASE, P_DATAIN;
-		mvi	P_DATAOUT|BSYO call change_phase;
-		mov	ALLZEROS call initialize_channel;
+                xor     LASTPHASE, IOI, SCB_TARGET_INFO[SCB_TARGET_DATA_DIR];
+                or      SCB_TARGET_INFO[SCB_TARGET_DATA_DIR], BSYO
+                        call change_phase;
 		jmp	p_data;
 
 target_sphase:
 		mvi	P_STATUS|BSYO call change_phase;
 		mvi	LASTPHASE, P_STATUS;
-		mov	SCB_TARGET_STATUS call target_outb;
+                mov     SCB_TARGET_INFO[SCB_TARGET_STATUS] call target_outb;
 		/* XXX Watch for ATN or parity errors??? */
 		mvi	SCSISIGO, P_MESGIN|BSYO;
 		/* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
@@ -598,9 +608,7 @@ complete_target_cmd:
 			or	DFCNTRL, FIFORESET;
 			mvi	DFWADDR, 3; /* Third 64bit word or byte 24 */
 			mov	DFDAT, ALLONES;
-			mvi	HCNT[0], 28;
-			clr	HCNT[1];
-			clr	HCNT[2];
+                        mvi     28      call set_hcnt;
 			or	DFCNTRL, HDMAEN|FIFOFLUSH;
 			call	dma_finish;
 		}
@@ -608,17 +616,8 @@ complete_target_cmd:
 		mvi	INTSTAT,CMDCMPLT ret;
 	}
 
-if ((ahc->flags & AHC_INITIATORMODE) != 0) {
+if ((ahc->flags & AHC_INITIATORROLE) != 0) {
 initiator_select:
-	mvi	SPIOEN call	initialize_channel;
-
-	/*
-	 * We aren't expecting a bus free, so interrupt
-	 * the kernel driver if it happens.
-	 */
-	mvi	CLRSINT1,CLRBUSFREE;
-	or	SIMODE1, ENBUSFREE;
-
 	/*
 	 * As soon as we get a successful selection, the target
 	 * should go into the message out phase since we have ATN
@@ -632,6 +631,7 @@ initiator_select:
 	 * target to assert REQ before checking MSG, C/D and I/O for
 	 * the bus phase.
 	 */
+mesgin_phasemis:
 ITloop:
 	call	phase_lock;
 
@@ -643,16 +643,19 @@ ITloop:
 	cmp	A,P_STATUS	je p_status;
 	cmp	A,P_MESGIN	je p_mesgin;
 
-	mvi	INTSTAT,BAD_PHASE;
+        mvi     BAD_PHASE call set_seqint;
 	jmp	ITloop;			/* Try reading the bus again. */
 
 await_busfree:
 	and	SIMODE1, ~ENBUSFREE;
 	mov	NONE, SCSIDATL;		/* Ack the last byte */
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                clr     SCSIBUSL;       /* Prevent bit leakage durint SELTO */
+        }
 	and	SXFRCTL0, ~SPIOEN;
 	test	SSTAT1,REQINIT|BUSFREE	jz .;
 	test	SSTAT1, BUSFREE jnz poll_for_work;
-	mvi	INTSTAT, BAD_PHASE;
+        mvi     MISSED_BUSFREE call set_seqint;
 }
 	
 clear_target_state:
@@ -662,6 +665,7 @@ clear_target_state:
 	 * clear DFCNTRL too.
 	 */
 	clr	DFCNTRL;
+        or      SXFRCTL0, CLRSTCNT|CLRCHN;
 
 	/*
 	 * We don't know the target we will connect to,
@@ -672,35 +676,129 @@ clear_target_state:
 		bmov	SCSIRATE, ALLZEROS, 2;
 	} else {
 		clr	SCSIRATE;
-		and	SXFRCTL0, ~(FAST20);
+                if ((ahc->features & AHC_ULTRA) != 0) {
+                        and     SXFRCTL0, ~(FAST20);
+                }
 	}
 	mvi	LASTPHASE, P_BUSFREE;
 	/* clear target specific flags */
 	clr	SEQ_FLAGS ret;
 
+sg_advance:
+        clr     A;                      /* add sizeof(struct scatter) */
+        add     SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
+        adc     SCB_RESIDUAL_SGPTR[1],A;
+        adc     SCB_RESIDUAL_SGPTR[2],A;
+        adc     SCB_RESIDUAL_SGPTR[3],A ret;
+
+if ((ahc->features & AHC_CMD_CHAN) != 0) {
+disable_ccsgen:
+        test    CCSGCTL, CCSGEN jz return;
+        test    CCSGCTL, CCSGDONE jz .;
+disable_ccsgen_fetch_done:
+        clr     CCSGCTL;
+        test    CCSGCTL, CCSGEN jnz .;
+        ret;
+idle_loop:
+        /*
+         * Do we need any more segments for this transfer?
+         */
+        test    SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
+
+        /* Did we just finish fetching segs? */
+        cmp     CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
+
+        /* Are we actively fetching segments? */
+        test    CCSGCTL, CCSGEN jnz return;
+
+        /*
+         * Do we have any prefetch left???
+         */
+        cmp     CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
+
+        /*
+         * Need to fetch segments, but we can only do that
+         * if the command channel is completely idle.  Make
+         * sure we don't have an SCB prefetch going on.
+         */
+        test    CCSCBCTL, CCSCBEN jnz return;
+
+        /*
+         * We fetch a "cacheline aligned" and sized amount of data
+         * so we don't end up referencing a non-existant page.
+         * Cacheline aligned is in quotes because the kernel will
+         * set the prefetch amount to a reasonable level if the
+         * cacheline size is unknown.
+         */
+        mvi     CCHCNT, SG_PREFETCH_CNT;
+        and     CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
+        bmov    CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
+        mvi     CCSGCTL, CCSGEN|CCSGRESET ret;
+idle_sgfetch_complete:
+        call    disable_ccsgen_fetch_done;
+        and     CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
+idle_sg_avail:
+	if ((ahc->features & AHC_ULTRA2) != 0) {
+                /* Does the hardware have space for another SG entry? */
+                test    DFSTATUS, PRELOAD_AVAIL jz return;
+                bmov    HADDR, CCSGRAM, 7;
+                test    HCNT[0], 0x1 jz . + 2;
+                xor     DATA_COUNT_ODD, 0x1;
+                bmov    SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
+                if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+                        mov     SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
+                }
+                call    sg_advance;
+                mov     SINDEX, SCB_RESIDUAL_SGPTR[0];
+                test    DATA_COUNT_ODD, 0x1 jz . + 2;
+                or      SINDEX, ODD_SEG;
+                test    SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
+                or      SINDEX, LAST_SEG;
+                mov     SG_CACHE_PRE, SINDEX;
+                /* Load the segment */
+                or      DFCNTRL, PRELOADEN;
+        }
+        ret;
+}
+
+if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
 /*
- * If we re-enter the data phase after going through another phase, the
- * STCNT may have been cleared, so restore it from the residual field.
+ * Calculate the trailing portion of this S/G segment that cannot
+ * be transferred using memory write and invalidate PCI transactions.  
+ * XXX Can we optimize this for PCI writes only???
  */
-data_phase_reinit:
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		/*
-		 * The preload circuitry requires us to
-		 * reload the address too, so pull it from
-		 * the shaddow address.
-		 */
-		bmov	HADDR, SHADDR, 4;
-		bmov	HCNT, SCB_RESID_DCNT, 3;
-	} else if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		bmov	STCNT, SCB_RESID_DCNT, 3;
-	} else {
-		mvi	DINDEX, STCNT;
-		mvi	SCB_RESID_DCNT	call bcopy_3;
-	}
-	and	DATA_COUNT_ODD, 0x1, SCB_RESID_DCNT[0];
-	jmp	data_phase_loop;
+calc_mwi_residual:
+        /*
+         * If the ending address is on a cacheline boundary,
+         * there is no need for an extra segment.
+         */
+        mov     A, HCNT[0];
+        add     A, A, HADDR[0];
+        and     A, CACHESIZE_MASK;
+        test    A, 0xFF jz return;
+
+        /*
+         * If the transfer is less than a cachline,
+         * there is no need for an extra segment.
+         */
+        test    HCNT[1], 0xFF   jnz calc_mwi_residual_final;
+        test    HCNT[2], 0xFF   jnz calc_mwi_residual_final;
+        add     NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
+        jnc     return;
+
+calc_mwi_residual_final:
+        mov     MWI_RESIDUAL, A;
+        not     A;
+        inc     A;
+        add     HCNT[0], A;
+        adc     HCNT[1], -1;
+        adc     HCNT[2], -1 ret;
+}
 
 p_data:
+        test    SEQ_FLAGS,IDENTIFY_SEEN jnz p_data_okay;
+        mvi     NO_IDENT jmp set_seqint;
+p_data_okay:
 	if ((ahc->features & AHC_ULTRA2) != 0) {
 		mvi	DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
 	} else {
@@ -708,213 +806,515 @@ p_data:
 	}
 	test	LASTPHASE, IOI jnz . + 2;
 	or	DMAPARAMS, DIRECTION;
-	call	assert;			/*
-					 * Ensure entering a data
-					 * phase is okay - seen identify, etc.
-					 */
 	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		mvi	CCSGADDR, CCSGADDR_MAX;
+                /* We don't have any valid S/G elements */
+                mvi     CCSGADDR, SG_PREFETCH_CNT;
 	}
-	test	SEQ_FLAGS, DPHASE	jnz data_phase_reinit;
-
-	/* We have seen a data phase */
+        test    SEQ_FLAGS, DPHASE       jz data_phase_initialize;
+
+        /*
+         * If we re-enter the data phase after going through another
+         * phase, our transfer location has almost certainly been
+         * corrupted by the interveining, non-data, transfers.  Ask
+         * the host driver to fix us up based on the transfer residual.
+         */
+        mvi     PDATA_REINIT    call set_seqint;
+        jmp     data_phase_loop;
+
+data_phase_initialize:
+        /* We have seen a data phase for the first time */
 	or	SEQ_FLAGS, DPHASE;
 
 	/*
 	 * Initialize the DMA address and counter from the SCB.
-	 * Also set SG_COUNT and SG_NEXT in memory since we cannot
-	 * modify the values in the SCB itself until we see a
-	 * save data pointers message.
+         * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
+         * flag in the highest byte of the data count.  We cannot
+         * modify the saved values in the SCB until we see a save
+         * data pointers message.
 	 */
+        if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+                /* The lowest address byte must be loaded last. */
+                mov     SCB_DATACNT[3] call set_hhaddr;
+        }
 	if ((ahc->features & AHC_CMD_CHAN) != 0) {
 		bmov	HADDR, SCB_DATAPTR, 7;
+                bmov    SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
 	} else {
 		mvi	DINDEX, HADDR;
 		mvi	SCB_DATAPTR	call bcopy_7;
+                mvi     DINDEX, SCB_RESIDUAL_DATACNT + 3;
+                mvi     SCB_DATACNT + 3 call bcopy_5;
 	}
-	and	DATA_COUNT_ODD, 0x1, SCB_DATACNT[0];
+        if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
+                call    calc_mwi_residual;
+        }
+        and     SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
+        and     DATA_COUNT_ODD, 0x1, HCNT[0];
 
 	if ((ahc->features & AHC_ULTRA2) == 0) {
 		if ((ahc->features & AHC_CMD_CHAN) != 0) {
 			bmov	STCNT, HCNT, 3;
 		} else {
 			call	set_stcnt_from_hcnt;
-		}
-	}
-
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		bmov	SG_COUNT, SCB_SGCOUNT, 5;
-	} else {
-		mvi	DINDEX, SG_COUNT;
-		mvi	SCB_SGCOUNT	call bcopy_5;
+                }
 	}
 
 data_phase_loop:
-/* Guard against overruns */
-	test	SG_COUNT, 0xff jnz data_phase_inbounds;
-/*
- * Turn on 'Bit Bucket' mode, set the transfer count to
- * 16meg and let the target run until it changes phase.
- * When the transfer completes, notify the host that we
- * had an overrun.
- */
+        /* Guard against overruns */
+        test    SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
+
+        /*
+         * Turn on `Bit Bucket' mode, wait until the target takes
+         * us to another phase, and then notify the host.
+         */
+        and     DMAPARAMS, DIRECTION;
+        mov     DFCNTRL, DMAPARAMS;
 	or	SXFRCTL1,BITBUCKET;
-	and	DMAPARAMS, ~(HDMAEN|SDMAEN);
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		bmov	HCNT, ALLONES, 3;
-	} else if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		bmov	STCNT, ALLONES, 3;
+        if ((ahc->features & AHC_DT) == 0) {
+                test    SSTAT1,PHASEMIS jz .;
 	} else {
-		mvi	STCNT[0], 0xFF;
-		mvi	STCNT[1], 0xFF;
-		mvi	STCNT[2], 0xFF;
+                test    SCSIPHASE, DATA_PHASE_MASK jnz .;
 	}
+        and     SXFRCTL1, ~BITBUCKET;
+        mvi     DATA_OVERRUN call set_seqint;
+        jmp     ITloop;
+
 data_phase_inbounds:
-/* If we are the last SG block, tell the hardware. */
-	cmp	SG_COUNT,0x01 jne data_phase_wideodd;
 	if ((ahc->features & AHC_ULTRA2) != 0) {
-		or	SG_CACHEPTR, LAST_SEG;
+                mov     SINDEX, SCB_RESIDUAL_SGPTR[0];
+                test    SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
+                or      SINDEX, LAST_SEG;
+                test    DATA_COUNT_ODD, 0x1 jz . + 2;
+                or      SINDEX, ODD_SEG;
+                mov     SG_CACHE_PRE, SINDEX;
+                mov     DFCNTRL, DMAPARAMS;
+ultra2_dma_loop:
+                call    idle_loop;
+                /*
+                 * The transfer is complete if either the last segment
+                 * completes or the target changes phase.
+                 */
+                test    SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
+                if ((ahc->features & AHC_DT) == 0) {
+                        if ((ahc->flags & AHC_TARGETROLE) != 0) {
+                                 /*
+                                  * As a target, we control the phases,
+                                  * so ignore PHASEMIS.
+                                  */
+                                test    SSTAT0, TARGET jnz ultra2_dma_loop;
+                        }
+                        if ((ahc->flags & AHC_INITIATORROLE) != 0) {
+                                test    SSTAT1,PHASEMIS jz ultra2_dma_loop;
+                        }
+                } else {
+                        test    DFCNTRL, SCSIEN jnz ultra2_dma_loop;
+                }
+
+ultra2_dmafinish:
+                /*
+                 * The transfer has terminated either due to a phase
+                 * change, and/or the completion of the last segment.
+                 * We have two goals here.  Do as much other work
+                 * as possible while the data fifo drains on a read
+                 * and respond as quickly as possible to the standard
+                 * messages (save data pointers/disconnect and command
+                 * complete) that usually follow a data phase.
+                 */
+                if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
+                        /*
+                         * On chips with broken auto-flush, start
+                         * the flushing process now.  We'll poke
+                         * the chip from time to time to keep the
+                         * flush process going as we complete the
+                         * data phase.
+                         */
+                        or      DFCNTRL, FIFOFLUSH;
+                }
+                /*
+                 * We assume that, even though data may still be
+                 * transferring to the host, that the SCSI side of
+                 * the DMA engine is now in a static state.  This
+                 * allows us to update our notion of where we are
+                 * in this transfer.
+                 *
+                 * If, by chance, we stopped before being able
+                 * to fetch additional segments for this transfer,
+                 * yet the last S/G was completely exhausted,
+                 * call our idle loop until it is able to load
+                 * another segment.  This will allow us to immediately
+                 * pickup on the next segment on the next data phase.
+                 *
+                 * If we happened to stop on the last segment, then
+                 * our residual information is still correct from
+                 * the idle loop and there is no need to perform
+                 * any fixups.
+                 */
+ultra2_ensure_sg:
+                test    SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
+                /* Record if we've consumed all S/G entries */
+                test    SSTAT2, SHVALID jnz residuals_correct;
+                or      SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
+                jmp     residuals_correct;
+
+ultra2_shvalid:
+                test    SSTAT2, SHVALID jnz sgptr_fixup;
+                call    idle_loop;
+                jmp     ultra2_ensure_sg;
+
+sgptr_fixup:
+                /*
+                 * Fixup the residual next S/G pointer.  The S/G preload
+                 * feature of the chip allows us to load two elements
+                 * in addition to the currently active element.  We
+                 * store the bottom byte of the next S/G pointer in
+                 * the SG_CACEPTR register so we can restore the
+                 * correct value when the DMA completes.  If the next
+                 * sg ptr value has advanced to the point where higher
+                 * bytes in the address have been affected, fix them
+                 * too.
+                 */
+                test    SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
+                test    SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
+                add     SCB_RESIDUAL_SGPTR[1], -1;
+                adc     SCB_RESIDUAL_SGPTR[2], -1; 
+                adc     SCB_RESIDUAL_SGPTR[3], -1;
+sgptr_fixup_done:
+                and     SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
+                clr     DATA_COUNT_ODD;
+                test    SG_CACHE_SHADOW, ODD_SEG jz . + 2;
+                or      DATA_COUNT_ODD, 0x1;
+                clr     SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
+residuals_correct:
+                /*
+                 * Go ahead and shut down the DMA engine now.
+                 * In the future, we'll want to handle end of
+                 * transfer messages prior to doing this, but this
+                 * requires similar restructuring for pre-ULTRA2
+                 * controllers.
+                 */
+                test    DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
+ultra2_fifoflush:
+                if ((ahc->features & AHC_DT) == 0) {
+                        if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
+                                /*
+                                 * On Rev A of the aic7890, the autoflush
+                                 * feature doesn't function correctly.
+                                 * Perform an explicit manual flush.  During
+                                 * a manual flush, the FIFOEMP bit becomes
+                                 * true every time the PCI FIFO empties
+                                 * regardless of the state of the SCSI FIFO.
+                                 * It can take up to 4 clock cycles for the
+                                 * SCSI FIFO to get data into the PCI FIFO
+                                 * and for FIFOEMP to de-assert.  Here we
+                                 * guard against this condition by making
+                                 * sure the FIFOEMP bit stays on for 5 full
+                                 * clock cycles.
+                                 */
+                                or      DFCNTRL, FIFOFLUSH;
+                                test    DFSTATUS, FIFOEMP jz ultra2_fifoflush;
+                                test    DFSTATUS, FIFOEMP jz ultra2_fifoflush;
+                                test    DFSTATUS, FIFOEMP jz ultra2_fifoflush;
+                                test    DFSTATUS, FIFOEMP jz ultra2_fifoflush;
+                        }
+                        test    DFSTATUS, FIFOEMP jz ultra2_fifoflush;
+                } else {
+                        /*
+                         * We enable the auto-ack feature on DT capable
+                         * controllers.  This means that the controller may
+                         * have already transferred some overrun bytes into
+                         * the data FIFO and acked them on the bus.  The only
+                         * way to detect this situation is to wait for
+                         * LAST_SEG_DONE to come true on a completed transfer
+                         * and then test to see if the data FIFO is non-empty.
+                         */
+                        test    SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 4;
+                        test    SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
+                        test    DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
+                        /* Overrun */
+                        jmp     data_phase_loop;
+                        test    DFSTATUS, FIFOEMP jz .;
+                }
+ultra2_fifoempty:
+                /* Don't clobber an inprogress host data transfer */
+                test    DFSTATUS, MREQPEND      jnz ultra2_fifoempty;
+ultra2_dmahalt:
+                and     DFCNTRL, ~(SCSIEN|HDMAEN);
+                test    DFCNTRL, SCSIEN|HDMAEN jnz .;
+                if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+                        /*
+                         * Keep HHADDR cleared for future, 32bit addressed
+                         * only, DMA operations.
+                         *
+                         * Due to bayonette style S/G handling, our residual
+                         * data must be "fixed up" once the transfer is halted.
+                         * Here we fixup the HSHADDR stored in the high byte
+                         * of the residual data cnt.  By postponing the fixup,
+                         * we can batch the clearing of HADDR with the fixup.
+                         * If we halted on the last segment, the residual is
+                         * already correct.   If we are not on the last
+                         * segment, copy the high address directly from HSHADDR.
+                         * We don't need to worry about maintaining the
+                         * SG_LAST_SEG flag as it will always be false in the
+                         * case where an update is required.
+                         */
+                        or      DSCOMMAND1, HADDLDSEL0;
+                        test    SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
+                        mov     SCB_RESIDUAL_DATACNT[3], SHADDR;
+                        clr     HADDR;
+                        and     DSCOMMAND1, ~HADDLDSEL0;
+                }
 	} else {
-		if ((ahc->flags & AHC_TARGETMODE) != 0) {
-			test	SSTAT0, TARGET jz . + 2;
-			test	DMAPARAMS, DIRECTION jz data_phase_wideodd;
+                /* If we are the last SG block, tell the hardware. */
+                if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
+                  && ahc->pci_cachesize != 0) {
+                        test    MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
+                }
+                test    SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
+                if ((ahc->flags & AHC_TARGETROLE) != 0) {
+                        test    SSTAT0, TARGET jz dma_last_sg;
+                        if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) {
+                                test    DMAPARAMS, DIRECTION jz dma_mid_sg;
+                        }
 		}
+dma_last_sg:
 		and	DMAPARAMS, ~WIDEODD;
-	}
-data_phase_wideodd:
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		mov	SINDEX, ALLONES;
+dma_mid_sg:
+                /* Start DMA data transfer. */
 		mov	DFCNTRL, DMAPARAMS;
-		test	SSTAT0, SDONE jnz .;/* Wait for preload to complete */
-data_phase_dma_loop:
-		test	SSTAT0,	SDONE jnz data_phase_dma_done;
-		test	SSTAT1,PHASEMIS	jz data_phase_dma_loop;	/* ie. underrun */
-	} else {
-		mov	DMAPARAMS  call dma;
-	}
-
-data_phase_dma_done:
-/* Go tell the host about any overruns */
-	test	SXFRCTL1,BITBUCKET jnz data_phase_overrun;
-
-/* See if we completed this segment */
-	test	STCNT[0], 0xff	jnz data_phase_finish;
-	test	STCNT[1], 0xff	jnz data_phase_finish;
-	test	STCNT[2], 0xff	jnz data_phase_finish;
-
-/*
- * Advance the scatter-gather pointers if needed 
- */
-sg_advance:
-	dec	SG_COUNT;	/* one less segment to go */
-
-	test	SG_COUNT, 0xff	jz data_phase_finish; /* Are we done? */
-/*
- * Load a struct scatter and set up the data address and length.
- * If the working value of the SG count is nonzero, then
- * we need to load a new set of values.
- *
- * This, like all DMA's, assumes little-endian host data storage.
- */
+dma_loop:
+                if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                        call    idle_loop;
+                }
+                test    SSTAT0,DMADONE  jnz dma_dmadone;
+                test    SSTAT1,PHASEMIS jz dma_loop;    /* ie. underrun */
+dma_phasemis:
+                /*
+                 * We will be "done" DMAing when the transfer count goes to
+                 * zero, or the target changes the phase (in light of this,
+                 * it makes sense that the DMA circuitry doesn't ACK when
+                 * PHASEMIS is active).  If we are doing a SCSI->Host transfer,
+                 * the data FIFO should be flushed auto-magically on STCNT=0
+                 * or a phase change, so just wait for FIFO empty status.
+                 */
+dma_checkfifo:
+                test    DFCNTRL,DIRECTION       jnz dma_fifoempty;
+dma_fifoflush:
+                test    DFSTATUS,FIFOEMP        jz dma_fifoflush;
+dma_fifoempty:
+                /* Don't clobber an inprogress host data transfer */
+                test    DFSTATUS, MREQPEND      jnz dma_fifoempty;
+
+                /*
+                 * Now shut off the DMA and make sure that the DMA
+                 * hardware has actually stopped.  Touching the DMA
+                 * counters, etc. while a DMA is active will result
+                 * in an ILLSADDR exception.
+                 */
+dma_dmadone:
+                and     DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
+dma_halt:
+                /*
+                 * Some revisions of the aic78XX have a problem where, if the
+                 * data fifo is full, but the PCI input latch is not empty, 
+                 * HDMAEN cannot be cleared.  The fix used here is to drain
+                 * the prefetched but unused data from the data fifo until
+                 * there is space for the input latch to drain.
+                 */
+                if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
+                        mov     NONE, DFDAT;
+                }
+                test    DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
+
+                /* See if we have completed this last segment */
+                test    STCNT[0], 0xff  jnz data_phase_finish;
+                test    STCNT[1], 0xff  jnz data_phase_finish;
+                test    STCNT[2], 0xff  jnz data_phase_finish;
+
+                /*
+                 * Advance the scatter-gather pointers if needed 
+                 */
+                if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
+                  && ahc->pci_cachesize != 0) {
+                        test    MWI_RESIDUAL, 0xFF jz no_mwi_resid;
+                        /*
+                         * Reload HADDR from SHADDR and setup the
+                         * count to be the size of our residual.
+                         */
+                        if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                                bmov    HADDR, SHADDR, 4;
+                                mov     HCNT, MWI_RESIDUAL;
+                                bmov    HCNT[1], ALLZEROS, 2;
+                        } else {
+                                mvi     DINDEX, HADDR;
+                                mvi     SHADDR call bcopy_4;
+                                mov     MWI_RESIDUAL call set_hcnt;
+                        }
+                        clr     MWI_RESIDUAL;
+                        jmp     sg_load_done;
+no_mwi_resid:
+                }
+                test    SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
+                or      SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
+                jmp     data_phase_finish;
 sg_load:
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
 		/*
-		 * Do we have any prefetch left???
+                 * Load the next SG element's data address and length
+                 * into the DMA engine.  If we don't have hardware
+                 * to perform a prefetch, we'll have to fetch the
+                 * segment from host memory first.
 		 */
-		cmp	CCSGADDR, CCSGADDR_MAX jne prefetched_segs_avail;
-
-		/*
-		 * Fetch MIN(CCSGADDR_MAX, (SG_COUNT * 8)) bytes.
-		 */
-		add	A, -(CCSGRAM_MAXSEGS + 1), SG_COUNT;
-		mvi	A, CCSGADDR_MAX;
-		jc	. + 2;
-		shl	A, 3, SG_COUNT;
-		mov	CCHCNT, A;
-		bmov	CCHADDR, SG_NEXT, 4;
-		mvi	CCSGCTL, CCSGEN|CCSGRESET;
-		test	CCSGCTL, CCSGDONE jz .;
-		and	CCSGCTL, ~CCSGEN;
-		test	CCSGCTL, CCSGEN jnz .;
-		mvi	CCSGCTL, CCSGRESET;
-prefetched_segs_avail:
-		bmov 	HADDR, CCSGRAM, 8;
-	} else {
-		mvi	DINDEX, HADDR;
-		mvi	SG_NEXT	call bcopy_4;
-
-		mvi	HCNT[0],SG_SIZEOF;
-		clr	HCNT[1];
-		clr	HCNT[2];
-
-		or	DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
-
-		call	dma_finish;
-
-		/*
-		 * Copy data from FIFO into SCB data pointer and data count.
-		 * This assumes that the SG segments are of the form:
-		 * struct ahc_dma_seg {
-		 *	u_int32_t	addr;	four bytes, little-endian order
-		 *	u_int32_t	len;	four bytes, little endian order
-		 * };
-		 */
-		mvi	HADDR	call dfdat_in_7;
-	}
-
-	/* Track odd'ness */
-	test	HCNT[0], 0x1 jz . + 2;
-	xor	DATA_COUNT_ODD, 0x1;
-
-	if ((ahc->features & AHC_ULTRA2) == 0) {
-		/* Load STCNT as well.  It is a mirror of HCNT */
+                if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                        /* Wait for the idle loop to complete */
+                        test    CCSGCTL, CCSGEN jz . + 3;
+                        call    idle_loop;
+                        test    CCSGCTL, CCSGEN jnz . - 1;
+                        bmov    HADDR, CCSGRAM, 7;
+                        /*
+                         * Workaround for flaky external SCB RAM
+                         * on certain aic7895 setups.  It seems
+                         * unable to handle direct transfers from
+                         * S/G ram to certain SCB locations.
+                         */
+                        mov     SINDEX, CCSGRAM;
+                        mov     SCB_RESIDUAL_DATACNT[3], SINDEX;
+                } else {
+                        if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+                                mov     ALLZEROS call set_hhaddr;
+                        }
+                        mvi     DINDEX, HADDR;
+                        mvi     SCB_RESIDUAL_SGPTR      call bcopy_4;
+
+                        mvi     SG_SIZEOF       call set_hcnt;
+
+                        or      DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
+
+                        call    dma_finish;
+
+                        mvi     DINDEX, HADDR;
+                        call    dfdat_in_7;
+                        mov     SCB_RESIDUAL_DATACNT[3], DFDAT;
+                }
+
+                if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+                        mov     SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
+
+                        /*
+                         * The lowest address byte must be loaded
+                         * last as it triggers the computation of
+                         * some items in the PCI block.  The ULTRA2
+                         * chips do this on PRELOAD.
+                         */
+                        mov     HADDR, HADDR;
+                }
+                if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
+                  && ahc->pci_cachesize != 0) {
+                        call calc_mwi_residual;
+                }
+
+                /* Point to the new next sg in memory */
+                call    sg_advance;
+
+sg_load_done:
 		if ((ahc->features & AHC_CMD_CHAN) != 0) {
 			bmov	STCNT, HCNT, 3;
 		} else {
 			call	set_stcnt_from_hcnt;
 		}
-	}
-
-/* Advance the SG pointer */
-	clr	A;			/* add sizeof(struct scatter) */
-	add	SG_NEXT[0],SG_SIZEOF;
-	adc	SG_NEXT[1],A;
+                /* Track odd'ness */
+                test    HCNT[0], 0x1 jz . + 2;
+                xor     DATA_COUNT_ODD, 0x1;
 
-	if ((ahc->flags & AHC_TARGETMODE) != 0) {
-		test	SSTAT0, TARGET jnz data_phase_loop;
+                if ((ahc->flags & AHC_TARGETROLE) != 0) {
+                        test    SSTAT0, TARGET jnz data_phase_loop;
+                }
 	}
-	test	SSTAT1, REQINIT jz .;
-	test	SSTAT1,PHASEMIS	jz data_phase_loop;
-
-	/* Ensure the last seg is visable at the shaddow layer */
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		mov	DFCNTRL, DMAPARAMS;
-		test	SSTAT0, SDONE jnz .;/* Wait for preload to complete */
+data_phase_finish:
+        /*
+         * If the target has left us in data phase, loop through
+         * the dma code again.  In the case of ULTRA2 adapters,
+         * we should only loop if there is a data overrun.  For
+         * all other adapters, we'll loop after each S/G element
+         * is loaded as well as if there is an overrun.
+         */
+        if ((ahc->flags & AHC_TARGETROLE) != 0) {
+                test    SSTAT0, TARGET jnz data_phase_done;
+        }
+        if ((ahc->flags & AHC_INITIATORROLE) != 0) {
+                test    SSTAT1, REQINIT jz .;
+                if ((ahc->features & AHC_DT) == 0) {
+                        test    SSTAT1,PHASEMIS jz data_phase_loop;
+                } else {
+                        test    SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
+                }
+        }
+
+data_phase_done:
+        /*
+         * After a DMA finishes, save the SG and STCNT residuals back into
+         * the SCB.  We use STCNT instead of HCNT, since it's a reflection
+         * of how many bytes were transferred on the SCSI (as opposed to the
+         * host) bus.
+         */
+        if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                /* Kill off any pending prefetch */
+                call    disable_ccsgen;
 	}
 
-data_phase_finish:
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		call	ultra2_dmafinish;
+        if ((ahc->features & AHC_ULTRA2) == 0) {
+                /*
+                 * Clear the high address byte so that all other DMA
+                 * operations, which use 32bit addressing, can assume
+                 * HHADDR is 0.
+                 */
+                if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+                        mov     ALLZEROS call set_hhaddr;
+                }
 	}
-/*
- * After a DMA finishes, save the SG and STCNT residuals back into the SCB
- * We use STCNT instead of HCNT, since it's a reflection of how many bytes 
- * were transferred on the SCSI (as opposed to the host) bus.
- */
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		bmov	SCB_RESID_DCNT, STCNT, 3;
+
+        /*
+         * Update our residual information before the information is
+         * lost by some other type of SCSI I/O (e.g. PIO).  If we have
+         * transferred all data, no update is needed.
+         *
+         */
+        test    SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
+        if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
+          && ahc->pci_cachesize != 0) {
+                if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                        test    MWI_RESIDUAL, 0xFF jz bmov_resid;
+                }
+                mov     A, MWI_RESIDUAL;
+                add     SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
+                clr     A;
+                adc     SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
+                adc     SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
+                clr     MWI_RESIDUAL;
+                if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                        jmp     . + 2;
+bmov_resid:
+                        bmov    SCB_RESIDUAL_DATACNT, STCNT, 3;
+                }
+        } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                bmov    SCB_RESIDUAL_DATACNT, STCNT, 3;
 	} else {
-		mov	SCB_RESID_DCNT[0],STCNT[0];
-		mov	SCB_RESID_DCNT[1],STCNT[1];
-		mov	SCB_RESID_DCNT[2],STCNT[2];
+                mov     SCB_RESIDUAL_DATACNT[0], STCNT[0];
+                mov     SCB_RESIDUAL_DATACNT[1], STCNT[1];
+                mov     SCB_RESIDUAL_DATACNT[2], STCNT[2];
 	}
-	mov	SCB_RESID_SGCNT, SG_COUNT;
+residual_update_done:
+        /*
+         * Since we've been through a data phase, the SCB_RESID* fields
+         * are now initialized.  Clear the full residual flag.
+         */
+        and     SCB_SGPTR[0], ~SG_FULL_RESID;
 
 	if ((ahc->features & AHC_ULTRA2) != 0) {
+                /* Clear the channel in case we return to data phase later */
+                or      SXFRCTL0, CLRSTCNT|CLRCHN;
 		or	SXFRCTL0, CLRSTCNT|CLRCHN;
 	}
 
-	if ((ahc->flags & AHC_TARGETMODE) != 0) {
+        if ((ahc->flags & AHC_TARGETROLE) != 0) {
 		test	SEQ_FLAGS, DPHASE_PENDING jz ITloop;
 		and	SEQ_FLAGS, ~DPHASE_PENDING;
 		/*
@@ -924,112 +1324,104 @@ data_phase_finish:
 		test	DFCNTRL, DIRECTION jz target_ITloop;
 		test	SSTAT1, REQINIT	jnz .;
 		jmp	target_ITloop;
-	}
-	jmp	ITloop;
-
-data_phase_overrun:
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		call	ultra2_dmafinish;
-		or	SXFRCTL0, CLRSTCNT|CLRCHN;
-	}
-/*
- * Turn off BITBUCKET mode and notify the host
- */
-	and	SXFRCTL1, ~BITBUCKET;
-	mvi	INTSTAT,DATA_OVERRUN;
-	jmp	ITloop;
-
-ultra2_dmafinish:
-	if ((ahc->features & AHC_ULTRA2) != 0) {
-		test	DFCNTRL, DIRECTION jnz ultra2_dmafifoempty;
-		and	DFCNTRL, ~SCSIEN;
-		test	DFCNTRL, SCSIEN jnz .;
-ultra2_dmafifoflush:
-		or	DFCNTRL, FIFOFLUSH;
-		/*
-		 * The FIFOEMP status bit on the Ultra2 class
-		 * of controllers seems to be a bit flaky.
-		 * It appears that if the FIFO is full and the
-		 * transfer ends with some data in the REQ/ACK
-		 * FIFO, FIFOEMP will fall temporarily
-		 * as the data is transferred to the PCI bus.
-		 * This glitch lasts for fewer than 5 clock cycles,
-		 * so we work around the problem by ensuring the
-		 * status bit stays false through a full glitch
-		 * window.
-		 */
-		test	DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
-		test	DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
-		test	DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
-		test	DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
-		test	DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
-
-ultra2_dmafifoempty:
-		/* Don't clobber an inprogress host data transfer */
-		test	DFSTATUS, MREQPEND	jnz ultra2_dmafifoempty;
-
-ultra2_dmahalt:
-		and     DFCNTRL, ~(SCSIEN|HDMAEN);
-		test	DFCNTRL, HDMAEN jnz .;
-		ret;
+        } else {
+                jmp     ITloop;
 	}
 
-if ((ahc->flags & AHC_INITIATORMODE) != 0) {
+if ((ahc->flags & AHC_INITIATORROLE) != 0) {
 /*
  * Command phase.  Set up the DMA registers and let 'er rip.
  */
 p_command:
-	call	assert;
-
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		mov	HCNT[0], SCB_CMDLEN;
-		bmov	HCNT[1], ALLZEROS, 2;
-		if ((ahc->features & AHC_ULTRA2) == 0) {
-			bmov	STCNT, HCNT, 3;
-		}
-		add	NONE, -17, SCB_CMDLEN;
-		jc	dma_cmd_data;
-		/*
-		 * The data fifo seems to require 4 byte alligned
-		 * transfers from the sequencer.  Force this to
-		 * be the case by clearing HADDR[0] even though
-		 * we aren't going to touch host memeory.
-		 */
-		bmov	HADDR[0], ALLZEROS, 1;
-		if ((ahc->features & AHC_ULTRA2) != 0) {
-			mvi	DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
+        test    SEQ_FLAGS,IDENTIFY_SEEN jnz p_command_okay;
+        mvi     NO_IDENT jmp set_seqint;
+p_command_okay:
+
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                bmov    HCNT[0], SCB_CDB_LEN,  1;
+                bmov    HCNT[1], ALLZEROS, 2;
+                mvi     SG_CACHE_PRE, LAST_SEG;
+        } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                bmov    STCNT[0], SCB_CDB_LEN, 1;
+                bmov    STCNT[1], ALLZEROS, 2;
+        } else {
+                mov     STCNT[0], SCB_CDB_LEN;
+                clr     STCNT[1];
+                clr     STCNT[2];
+        }
+        add     NONE, -13, SCB_CDB_LEN;
+        mvi     SCB_CDB_STORE jnc p_command_embedded;
+p_command_from_host:
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                bmov    HADDR[0], SCB_CDB_PTR, 4;
+                mvi     DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
+        } else {
+                if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                        bmov    HADDR[0], SCB_CDB_PTR, 4;
+                        bmov    HCNT, STCNT, 3;
+                } else {
+                        mvi     DINDEX, HADDR;
+                        mvi     SCB_CDB_PTR call bcopy_4;
+                        mov     SCB_CDB_LEN call set_hcnt;
+                }
+                mvi     DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
+        }
+        jmp     p_command_loop;
+p_command_embedded:
+        /*
+         * The data fifo seems to require 4 byte aligned
+         * transfers from the sequencer.  Force this to
+         * be the case by clearing HADDR[0] even though
+         * we aren't going to touch host memeory.
+         */
+        clr     HADDR[0];
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                mvi     DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
+                bmov    DFDAT, SCB_CDB_STORE, 12; 
+        } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
+                if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                        /*
+                         * On the 7895 the data FIFO will
+                         * get corrupted if you try to dump
+                         * data from external SCB memory into
+                         * the FIFO while it is enabled.  So,
+                         * fill the fifo and then enable SCSI
+                         * transfers.
+                         */
+                        mvi     DFCNTRL, (DIRECTION|FIFORESET);
 		} else {
 			mvi	DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
 		}
-		bmov   DFDAT, SCB_CMDSTORE, 16; 
-		jmp	cmd_loop;
-dma_cmd_data:
-		bmov	HADDR, SCB_CMDPTR, 4;
-	} else {
-		mvi	DINDEX, HADDR;
-		mvi	SCB_CMDPTR	call bcopy_5;
-		clr	HCNT[1];
-		clr	HCNT[2];
-	}
-
-	if ((ahc->features & AHC_ULTRA2) == 0) {
-		if ((ahc->features & AHC_CMD_CHAN) == 0) {
-			call	set_stcnt_from_hcnt;
+                bmov    DFDAT, SCB_CDB_STORE, 12; 
+                if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                        mvi     DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
+                } else {
+                        or      DFCNTRL, FIFOFLUSH;
 		}
-		mvi	DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
 	} else {
-		mvi	DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
+                mvi     DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
+                call    copy_to_fifo_6;
+                call    copy_to_fifo_6;
+                or      DFCNTRL, FIFOFLUSH;
 	}
-cmd_loop:
-	test	SSTAT0, SDONE jnz . + 2;
-	test    SSTAT1, PHASEMIS jz cmd_loop;
-	/*
-	 * Wait for our ACK to go-away on it's own
-	 * instead of being killed by SCSIEN getting cleared.
-	 */
-	test	SCSISIGI, ACKI jnz .;
+p_command_loop:
+        if ((ahc->features & AHC_DT) == 0) {
+                test    SSTAT0, SDONE jnz . + 2;
+                test    SSTAT1, PHASEMIS jz p_command_loop;
+                /*
+                 * Wait for our ACK to go-away on it's own
+                 * instead of being killed by SCSIEN getting cleared.
+                 */
+                test    SCSISIGI, ACKI jnz .;
+        } else {
+                test    DFCNTRL, SCSIEN jnz p_command_loop;
+        }
 	and	DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
 	test	DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                /* Drop any residual from the S/G Preload queue */
+                or      SXFRCTL0, CLRSTCNT;
+        }
 	jmp	ITloop;
 
 /*
@@ -1037,9 +1429,10 @@ cmd_loop:
  * and store it into the SCB.
  */
 p_status:
-	call	assert;
-
-	mov	SCB_TARGET_STATUS, SCSIDATL;
+        test    SEQ_FLAGS,IDENTIFY_SEEN jnz p_status_okay;
+        mvi     NO_IDENT jmp set_seqint;
+p_status_okay:
+        mov     SCB_SCSI_STATUS, SCSIDATL;
 	jmp	ITloop;
 
 /*
@@ -1067,41 +1460,20 @@ p_status:
  * reason.
  */
 p_mesgout_retry:
-	or	SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */
+        /* Turn on ATN for the retry */
+        if ((ahc->features & AHC_DT) == 0) {
+                or      SCSISIGO, ATNO, LASTPHASE;
+        } else {
+                mvi     SCSISIGO, ATNO;
+        }
 p_mesgout:
 	mov	SINDEX, MSG_OUT;
 	cmp	SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
 	test	SCB_CONTROL,MK_MESSAGE	jnz host_message_loop;
-	mov	FUNCTION1, SCB_TCL;
-	mov	A, FUNCTION1;
-	if ((ahc->features & AHC_HS_MAILBOX) != 0) {
-		/*
-		 * Work around a pausing bug in at least the aic7890.
-		 * If the host needs to update the TARGET_MSG_REQUEST
-		 * bit field, it will set the HS_MAILBOX to 1.  In
-		 * response, we pause with a specific interrupt code
-		 * asking for the mask to be updated before we continue.
-		 * Ugh.
-		 */
-		test	HS_MAILBOX, 0xF0	jz . + 2;
-		mvi	INTSTAT, UPDATE_TMSG_REQ;
-		nop;
-	}
-	mov	SINDEX, TARGET_MSG_REQUEST[0];
-	if ((ahc->features & AHC_TWIN) != 0) {
-		/* Second Channel uses high byte bits */
-		test	SCB_TCL, SELBUSB	jz . + 2;
-		mov	SINDEX, TARGET_MSG_REQUEST[1];
-	} else if ((ahc->features & AHC_WIDE) != 0) {
-		test	SCB_TCL, 0x80		jz . + 2; /* target > 7 */
-		mov	SINDEX, TARGET_MSG_REQUEST[1];
-	}
-	test	SINDEX, A	jnz host_message_loop;
 p_mesgout_identify:
-	and	SINDEX,LID,SCB_TCL;	/* lun */
-	and	A,DISCENB,SCB_CONTROL;	/* mask off disconnect privledge */
-	or	SINDEX,A;		/* or in disconnect privledge */
-	or	SINDEX,MSG_IDENTIFYFLAG;
+        or      SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
+        test    SCB_CONTROL, DISCENB jnz . + 2;
+        and     SINDEX, ~DISCENB;
 /*
  * Send a tag message if TAG_ENB is set in the SCB control block.
  * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
@@ -1151,6 +1523,7 @@ p_mesgin:
 	cmp	A,MSG_SAVEDATAPOINTER	je mesgin_sdptrs;
 	cmp	ALLZEROS,A		je mesgin_complete;
 	cmp	A,MSG_RESTOREPOINTERS	je mesgin_rdptrs;
+        cmp     A,MSG_IGN_WIDE_RESIDUE  je mesgin_ign_wide_residue;
 	cmp	A,MSG_NOOP		je mesgin_done;
 
 /*
@@ -1163,70 +1536,78 @@ p_mesgin:
  * shouldn't hurt, but why do it twice...
  */
 host_message_loop:
-	mvi	INTSTAT, HOST_MSG_LOOP;
+        mvi     HOST_MSG_LOOP call set_seqint;
 	call	phase_lock;
 	cmp	RETURN_1, EXIT_MSG_LOOP	je ITloop + 1;
 	jmp	host_message_loop;
 
+mesgin_ign_wide_residue:
+if ((ahc->features & AHC_WIDE) != 0) {
+        test    SCSIRATE, WIDEXFER jz mesgin_reject;
+        /* Pull the residue byte */
+        mvi     ARG_1   call inb_next;
+        cmp     ARG_1, 0x01 jne mesgin_reject;
+        test    SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
+        test    DATA_COUNT_ODD, 0x1     jz mesgin_done;
+        mvi     IGN_WIDE_RES call set_seqint;
+        jmp     mesgin_done;
+}
+
+mesgin_reject:
+        mvi     MSG_MESSAGE_REJECT      call mk_mesg;
 mesgin_done:
 	mov	NONE,SCSIDATL;		/*dummy read from latch to ACK*/
 	jmp	ITloop;
 
-
 mesgin_complete:
 /*
- * We got a "command complete" message, so put the SCB_TAG into the QOUTFIFO,
+ * We received a "command complete" message.  Put the SCB_TAG into the QOUTFIFO,
  * and trigger a completion interrupt.  Before doing so, check to see if there
  * is a residual or the status byte is something other than STATUS_GOOD (0).
  * In either of these conditions, we upload the SCB back to the host so it can
  * process this information.  In the case of a non zero status byte, we 
  * additionally interrupt the kernel driver synchronously, allowing it to
  * decide if sense should be retrieved.  If the kernel driver wishes to request
- * sense, it will fill the kernel SCB with a request sense command and set
- * RETURN_1 to SEND_SENSE.  If RETURN_1 is set to SEND_SENSE we redownload
- * the SCB, and process it as the next command by adding it to the waiting list.
- * If the kernel driver does not wish to request sense, it need only clear
- * RETURN_1, and the command is allowed to complete normally.  We don't bother
- * to post to the QOUTFIFO in the error cases since it would require extra
- * work in the kernel driver to ensure that the entry was removed before the
- * command complete code tried processing it.
+ * sense, it will fill the kernel SCB with a request sense command, requeue
+ * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting 
+ * RETURN_1 to SEND_SENSE.
+ */
+
+/*
+ * If ATN is raised, we still want to give the target a message.
+ * Perhaps there was a parity error on this last message byte.
+ * Either way, the target should take us to message out phase
+ * and then attempt to complete the command again.  We should use a
+ * critical section here to guard against a timeout triggering
+ * for this command and setting ATN while we are still processing
+ * the completion.
+        test    SCSISIGI, ATNI jnz mesgin_done;
+ */
+
+/*
+ * See if we attempted to deliver a message but the target ingnored us.
  */
+        test    SCB_CONTROL, MK_MESSAGE jz . + 2;
+        mvi     MKMSG_FAILED call set_seqint;
 
 /*
- * First check for residuals
+ * Check for residuals
  */
-	test	SCB_RESID_SGCNT,0xff	jnz upload_scb;
-	test	SCB_TARGET_STATUS,0xff	jz complete;	/* Good Status? */
+        test    SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
+        test    SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
+        test    SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
+check_status:
+        test    SCB_SCSI_STATUS,0xff    jz complete;    /* Good Status? */
 upload_scb:
+        or      SCB_SGPTR, SG_RESID_VALID;
 	mvi	DMAPARAMS, FIFORESET;
 	mov	SCB_TAG		call dma_scb;
-check_status:
-	test	SCB_TARGET_STATUS,0xff	jz complete;	/* Just a residual? */
-	mvi	INTSTAT,BAD_STATUS;			/* let driver know */
-	nop;
+        test    SCB_SCSI_STATUS, 0xff   jz complete;    /* Just a residual? */
+        mvi     BAD_STATUS call set_seqint;             /* let driver know */
 	cmp	RETURN_1, SEND_SENSE	jne complete;
-	/* This SCB becomes the next to execute as it will retrieve sense */
-	mvi	DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
-	mov	SCB_TAG		call dma_scb;
-add_to_waiting_list:
-	mov	SCB_NEXT,WAITING_SCBH;
-	mov	WAITING_SCBH, SCBPTR;
-	/*
-	 * Prepare our selection hardware before the busfree so we have a
-	 * high probability of winning arbitration.
-	 */
-	call	start_selection;
+        call    add_scb_to_free_list;
 	jmp	await_busfree;
-
 complete:
-	/* If we are untagged, clear our address up in host ram */
-	test	SCB_CONTROL, TAG_ENB jnz complete_queue;
-	mov	A, SAVED_TCL;
-	/* fvdl - let ahc_intr clear this to avoid race conditions */
-	/* mvi	UNTAGGEDSCB_OFFSET call post_byte_setup; */
-	/* mvi	SCB_LIST_NULL call post_byte; */
-
-complete_queue:
 	mov	SCB_TAG call complete_post;
 	jmp	await_busfree;
 }
@@ -1247,14 +1628,32 @@ complete_post:
 	}
 	mvi	INTSTAT,CMDCMPLT ret;
 
-if ((ahc->flags & AHC_INITIATORMODE) != 0) {
+if ((ahc->flags & AHC_INITIATORROLE) != 0) {
 /*
  * Is it a disconnect message?  Set a flag in the SCB to remind us
- * and await the bus going free.
+ * and await the bus going free.  If this is an untagged transaction
+ * store the SCB id for it in our untagged target table for lookup on
+ * a reselction.
  */
 mesgin_disconnect:
+        /*
+         * If ATN is raised, we still want to give the target a message.
+         * Perhaps there was a parity error on this last message byte
+         * or we want to abort this command.  Either way, the target
+         * should take us to message out phase and then attempt to
+         * disconnect again.
+         * XXX - Wait for more testing.
+        test    SCSISIGI, ATNI jnz mesgin_done;
+         */
+
 	or	SCB_CONTROL,DISCONNECTED;
-	call	add_scb_to_disc_list;
+        if ((ahc->flags & AHC_PAGESCBS) != 0) {
+                call    add_scb_to_disc_list;
+        }
+        test    SCB_CONTROL, TAG_ENB jnz await_busfree;
+        mov     ARG_1, SCB_TAG;
+        mov     SAVED_LUN, SCB_LUN;
+        mov     SCB_SCSIID      call set_busy_target;
 	jmp	await_busfree;
 
 /*
@@ -1263,29 +1662,52 @@ mesgin_disconnect:
  * only if we've actually been into a data phase to change them.  This
  * protects against bogus data in scratch ram and the residual counts
  * since they are only initialized when we go into data_in or data_out.
+ * Ack the message as soon as possible.  For chips without S/G pipelining,
+ * we can only ack the message after SHADDR has been saved.  On these
+ * chips, SHADDR increments with every bus transaction, even PIO.
  */
 mesgin_sdptrs:
-	test	SEQ_FLAGS, DPHASE	jz mesgin_done;
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                mov     NONE,SCSIDATL;          /*dummy read from latch to ACK*/
+                test    SEQ_FLAGS, DPHASE       jz ITloop;
+        } else {
+                test    SEQ_FLAGS, DPHASE       jz mesgin_done;
+        }
 
 	/*
-	 * The SCB SGPTR becomes the next one we'll download,
-	 * and the SCB DATAPTR becomes the current SHADDR.
+         * If we are asked to save our position at the end of the
+         * transfer, just mark us at the end rather than perform a
+         * full save.
+         */
+        test    SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
+        or      SCB_SGPTR, SG_LIST_NULL;
+        if ((ahc->features & AHC_ULTRA2) != 0) {
+                jmp     ITloop;
+        } else {
+                jmp     mesgin_done;
+        }
+
+mesgin_sdptrs_full:
+
+        /*
+         * The SCB_SGPTR becomes the next one we'll download,
+         * and the SCB_DATAPTR becomes the current SHADDR.
 	 * Use the residual number since STCNT is corrupted by
 	 * any message transfer.
 	 */
 	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		bmov	SCB_SGCOUNT, SG_COUNT, 5;
 		bmov	SCB_DATAPTR, SHADDR, 4;
-		bmov	SCB_DATACNT, SCB_RESID_DCNT, 3;
+                if ((ahc->features & AHC_ULTRA2) == 0) {
+                        mov     NONE,SCSIDATL;  /*dummy read from latch to ACK*/
+                }
+                bmov    SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8;
 	} else {
-		mvi	DINDEX, SCB_SGCOUNT;
-		mvi	SG_COUNT call bcopy_5;
-	
 		mvi	DINDEX, SCB_DATAPTR;
-		mvi	SHADDR		call bcopy_4;
-		mvi	SCB_RESID_DCNT	call bcopy_3;
+                mvi     SHADDR call bcopy_4;
+                mov     NONE,SCSIDATL;  /*dummy read from latch to ACK*/
+                mvi     SCB_RESIDUAL_DATACNT call bcopy_8;
 	}
-	jmp	mesgin_done;
+        jmp     ITloop;
 
 /*
  * Restore pointers message?  Data pointers are recopied from the
@@ -1302,87 +1724,172 @@ mesgin_rdptrs:
 	jmp	mesgin_done;
 
 /*
+ * Index into our Busy Target table.  SINDEX and DINDEX are modified
+ * upon return.  SCBPTR may be modified by this action.
+ */
+set_busy_target:
+        shr     DINDEX, 4, SINDEX;
+        if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                mov     SCBPTR, SAVED_LUN;
+                add     DINDEX, SCB_64_BTT;
+        } else {
+                add     DINDEX, BUSY_TARGETS;
+        }
+        mov     DINDIR, ARG_1 ret;
+
+/*
  * Identify message?  For a reconnecting target, this tells us the lun
  * that the reconnection is for - find the correct SCB and switch to it,
  * clearing the "disconnected" bit so we don't "find" it by accident later.
  */
 mesgin_identify:
-	if ((ahc->features & AHC_WIDE) != 0) {
-		and	A,0x0f;		/* lun in lower four bits */
+        /*
+         * Determine whether a target is using tagged or non-tagged
+         * transactions by first looking at the transaction stored in
+         * the busy target array.  If there is no untagged transaction
+         * for this target or the transaction is for a different lun, then
+         * this must be an untagged transaction.
+         */
+        shr     SINDEX, 4, SAVED_SCSIID;
+        and     SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
+        if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                add     SINDEX, SCB_64_BTT;
+                mov     SCBPTR, SAVED_LUN;
+                if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                        add     NONE, -SCB_64_BTT, SINDEX;
+                        jc      . + 2;
+                        mvi     INTSTAT, OUT_OF_RANGE;
+                        nop;
+                        add     NONE, -(SCB_64_BTT + 16), SINDEX;
+                        jnc     . + 2;
+                        mvi     INTSTAT, OUT_OF_RANGE;
+                        nop;
+                }
 	} else {
-		and	A,0x07;		/* lun in lower three bits */
+                add     SINDEX, BUSY_TARGETS;
+                if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                        add     NONE, -BUSY_TARGETS, SINDEX;
+                        jc      . + 2;
+                        mvi     INTSTAT, OUT_OF_RANGE;
+                        nop;
+                        add     NONE, -(BUSY_TARGETS + 16), SINDEX;
+                        jnc     . + 2;
+                        mvi     INTSTAT, OUT_OF_RANGE;
+                        nop;
+                }
 	}
-	or      SAVED_TCL,A;		/* SAVED_TCL should be complete now */
-
-	mvi	ARG_2, SCB_LIST_NULL;	/* SCBID of prev SCB in disc List */
-	call	get_untagged_SCBID;
+        mov     ARG_1, SINDIR;
 	cmp	ARG_1, SCB_LIST_NULL	je snoop_tag;
 	if ((ahc->flags & AHC_PAGESCBS) != 0) {
-		test	SEQ_FLAGS, SCBPTR_VALID	jz use_retrieveSCB;
+                mov     ARG_1 call findSCB;
+        } else {
+                mov     SCBPTR, ARG_1;
 	}
-	/*
-	 * If the SCB was found in the disconnected list (as is
-	 * always the case in non-paging scenarios), SCBPTR is already
-	 * set to the correct SCB.  So, simply setup the SCB and get
-	 * on with things.
-	 */
-	call	rem_scb_from_disc_list;
-	jmp	setup_SCB;
+        if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                jmp setup_SCB_id_lun_okay;
+        } else {
+                /*
+                 * We only allow one untagged command per-target
+                 * at a time.  So, if the lun doesn't match, look
+                 * for a tag message.
+                 */
+                mov     A, SCB_LUN;
+                cmp     SAVED_LUN, A    je setup_SCB_id_lun_okay;
+                if ((ahc->flags & AHC_PAGESCBS) != 0) {
+                        /*
+                         * findSCB removes the SCB from the
+                         * disconnected list, so we must replace
+                         * it there should this SCB be for another
+                         * lun.
+                         */
+                        call    cleanup_scb;
+                }
+        }
+
 /*
  * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
  * If we get one, we use the tag returned to find the proper
- * SCB.  With SCB paging, this requires using search for both tagged
- * and non-tagged transactions since the SCB may exist in any slot.
- * If we're not using SCB paging, we can use the tag as the direct
- * index to the SCB.
+ * SCB.  With SCB paging, we must search for non-tagged
+ * transactions since the SCB may exist in any slot.  If we're not
+ * using SCB paging, we can use the tag as the direct index to the
+ * SCB.
  */
 snoop_tag:
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                or      SEQ_FLAGS, 0x80;
+        }
 	mov	NONE,SCSIDATL;		/* ACK Identify MSG */
-snoop_tag_loop:
 	call	phase_lock;
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                or      SEQ_FLAGS, 0x1;
+        }
 	cmp	LASTPHASE, P_MESGIN	jne not_found;
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                or      SEQ_FLAGS, 0x2;
+        }
 	cmp	SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
 get_tag:
-	mvi	ARG_1	call inb_next;	/* tag value */
+        if ((ahc->flags & AHC_PAGESCBS) != 0) {
+                mvi     ARG_1   call inb_next;  /* tag value */
+                mov     ARG_1   call findSCB;
+        } else {
+                mvi     ARG_1   call inb_next;  /* tag value */
+                mov     SCBPTR, ARG_1;
+        }
 
-	/*
-	 * Ensure that the SCB the tag points to is for
-	 * an SCB transaction to the reconnecting target.
-	 */
-use_retrieveSCB:
-	call	retrieveSCB;
+/*
+ * Ensure that the SCB the tag points to is for
+ * an SCB transaction to the reconnecting target.
+ */
 setup_SCB:
-	mov	A, SAVED_TCL;
-	cmp	SCB_TCL, A	jne not_found_cleanup_scb;
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                or      SEQ_FLAGS, 0x4;
+        }
+        mov     A, SCB_SCSIID;
+        cmp     SAVED_SCSIID, A jne not_found_cleanup_scb;
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                or      SEQ_FLAGS, 0x8;
+        }
+setup_SCB_id_okay:
+        mov     A, SCB_LUN;
+        cmp     SAVED_LUN, A    jne not_found_cleanup_scb;
+setup_SCB_id_lun_okay:
+        if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
+                or      SEQ_FLAGS, 0x10;
+        }
 	test	SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
 	and	SCB_CONTROL,~DISCONNECTED;
-	or	SEQ_FLAGS,IDENTIFY_SEEN;	/* make note of IDENTIFY */
+        test    SCB_CONTROL, TAG_ENB    jnz setup_SCB_tagged;
+        if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                mov     A, SCBPTR;
+        }
+        mvi     ARG_1, SCB_LIST_NULL;
+        mov     SAVED_SCSIID    call    set_busy_target;
+        if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                mov     SCBPTR, A;
+        }
+setup_SCB_tagged:
+        mvi     SEQ_FLAGS,IDENTIFY_SEEN;        /* make note of IDENTIFY */
 	call	set_transfer_settings;
 	/* See if the host wants to send a message upon reconnection */
 	test	SCB_CONTROL, MK_MESSAGE jz mesgin_done;
-	and	SCB_CONTROL, ~MK_MESSAGE;
 	mvi	HOST_MSG	call mk_mesg;
 	jmp	mesgin_done;
 
 not_found_cleanup_scb:
-	test	SCB_CONTROL, DISCONNECTED jz . + 3;
-	call	add_scb_to_disc_list;
-	jmp	not_found;
-	call	add_scb_to_free_list;
+        if ((ahc->flags & AHC_PAGESCBS) != 0) {
+                call    cleanup_scb;
+        }
 not_found:
-	mvi	INTSTAT, NO_MATCH;
+        mvi     NO_MATCH call set_seqint;
 	jmp	mesgin_done;
 
-/*
- * [ ADD MORE MESSAGE HANDLING HERE ]
- */
-
-/*
- * Locking the driver out, build a one-byte message passed in SINDEX
- * if there is no active message already.  SINDEX is returned intact.
- */
 mk_mesg:
-	or	SCSISIGO,ATNO,LASTPHASE;/* turn on ATNO */
+        if ((ahc->features & AHC_DT) == 0) {
+                or      SCSISIGO, ATNO, LASTPHASE;
+        } else {
+                mvi     SCSISIGO, ATNO;
+        }
 	mov	MSG_OUT,SINDEX ret;
 
 /*
@@ -1401,7 +1908,7 @@ mk_mesg:
  * use the same calling convention as inb.
  */
 inb_next_wait_perr:
-	mvi	INTSTAT, PERR_DETECTED;
+        mvi     PERR_DETECTED call set_seqint;
 	jmp	inb_next_wait;
 inb_next:
 	mov	NONE,SCSIDATL;		/*dummy read from latch to ACK*/
@@ -1423,7 +1930,7 @@ inb_last:
 	mov	NONE,SCSIDATL ret;		/*dummy read from latch to ACK*/
 }
 
-if ((ahc->flags & AHC_TARGETMODE) != 0) {
+if ((ahc->flags & AHC_TARGETROLE) != 0) {
 /*
  * Change to a new phase.  If we are changing the state of the I/O signal,
  * from out to in, wait an additional data release delay before continuing.
@@ -1440,7 +1947,7 @@ change_phase:
 	/*
 	 * If the data direction has changed, from
 	 * out (initiator driving) to in (target driving),
-	 * we must waitat least a data release delay plus
+         * we must wait at least a data release delay plus
 	 * the normal bus settle delay. [SCSI III SPI 10.11.0]
 	 */
 	cmp 	DINDEX, A je change_phase_wait;
@@ -1463,197 +1970,62 @@ target_outb:
 	and	SXFRCTL0, ~SPIOEN ret;
 }
 	
-mesgin_phasemis:
-/*
- * We expected to receive another byte, but the target changed phase
- */
-	mvi	INTSTAT, MSGIN_PHASEMIS;
-	jmp	ITloop;
-
-/*
- * DMA data transfer.  HADDR and HCNT must be loaded first, and
- * SINDEX should contain the value to load DFCNTRL with - 0x3d for
- * host->scsi, or 0x39 for scsi->host.  The SCSI channel is cleared
- * during initialization.
- */
-dma:
-	mov	DFCNTRL,SINDEX;
-dma_loop:
-	test	SSTAT0,DMADONE	jnz dma_dmadone;
-	test	SSTAT1,PHASEMIS	jz dma_loop;	/* ie. underrun */
-dma_phasemis:
-
-/*
- * We will be "done" DMAing when the transfer count goes to zero, or
- * the target changes the phase (in light of this, it makes sense that
- * the DMA circuitry doesn't ACK when PHASEMIS is active).  If we are
- * doing a SCSI->Host transfer, the data FIFO should be flushed auto-
- * magically on STCNT=0 or a phase change, so just wait for FIFO empty
- * status.
- */
-dma_checkfifo:
-	test	DFCNTRL,DIRECTION	jnz dma_fifoempty;
-dma_fifoflush:
-	test	DFSTATUS,FIFOEMP	jz dma_fifoflush;
-
-dma_fifoempty:
-	/* Don't clobber an inprogress host data transfer */
-	test	DFSTATUS, MREQPEND	jnz dma_fifoempty;
-/*
- * Now shut the DMA enables off and make sure that the DMA enables are 
- * actually off first lest we get an ILLSADDR.
- */
-dma_dmadone:
-	and	DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
-dma_halt:
-	/*
-	 * Some revisions of the aic7880 have a problem where, if the
-	 * data fifo is full, but the PCI input latch is not empty, 
-	 * HDMAEN cannot be cleared.  The fix used here is to attempt
-	 * to drain the data fifo until there is space for the input
-	 * latch to drain and HDMAEN de-asserts.
-	 */
-	if ((ahc->features & AHC_ULTRA2) == 0) {
-		mov	NONE, DFDAT;
-	}
-	test	DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
-return:
-	ret;
-
 /*
- * Assert that if we've been reselected, then we've seen an IDENTIFY
- * message.
- */
-assert:
-	test	SEQ_FLAGS,IDENTIFY_SEEN	jnz return;	/* seen IDENTIFY? */
-
-	mvi	INTSTAT,NO_IDENT 	ret;	/* no - tell the kernel */
-
-/*
- * Locate a disconnected SCB either by SAVED_TCL (ARG_1 is SCB_LIST_NULL)
- * or by the SCBID ARG_1.  The search begins at the SCB index passed in
- * via SINDEX which is an SCB that must be on the disconnected list.  If
- * the SCB cannot be found, SINDEX will be SCB_LIST_NULL, otherwise, SCBPTR
- * is set to the proper SCB.
+ * Locate a disconnected SCB by SCBID.  Upon return, SCBPTR and SINDEX will
+ * be set to the position of the SCB.  If the SCB cannot be found locally,
+ * it will be paged in from host memory.  RETURN_2 stores the address of the
+ * preceding SCB in the disconnected list which can be used to speed up
+ * removal of the found SCB from the disconnected list.
  */
+if ((ahc->flags & AHC_PAGESCBS) != 0) {
+BEGIN_CRITICAL
 findSCB:
-	mov	SCBPTR,SINDEX;			/* Initialize SCBPTR */
-	cmp	ARG_1, SCB_LIST_NULL	jne findSCB_by_SCBID;
-	mov	A, SAVED_TCL;
-	mvi	SCB_TCL	jmp findSCB_loop;	/* &SCB_TCL -> SINDEX */
-findSCB_by_SCBID:
-	mov	A, ARG_1;			/* Tag passed in ARG_1 */
-	mvi	SCB_TAG	jmp findSCB_loop;	/* &SCB_TAG -> SINDEX */
+        mov     A, SINDEX;                      /* Tag passed in SINDEX */
+        cmp     DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound;
+        mov     SCBPTR, DISCONNECTED_SCBH;      /* Initialize SCBPTR */
+        mvi     ARG_2, SCB_LIST_NULL;           /* Head of list */
+        jmp     findSCB_loop;
 findSCB_next:
+        cmp     SCB_NEXT, SCB_LIST_NULL je findSCB_notFound;
 	mov	ARG_2, SCBPTR;
-	cmp	SCB_NEXT, SCB_LIST_NULL je notFound;
 	mov	SCBPTR,SCB_NEXT;
-	dec	SINDEX;		/* Last comparison moved us too far */
 findSCB_loop:
-	cmp	SINDIR, A	jne findSCB_next;
-	mov	SINDEX, SCBPTR 	ret;
-notFound:
-	mvi	SINDEX, SCB_LIST_NULL	ret;
-
-/*
- * Retrieve an SCB by SCBID first searching the disconnected list falling
- * back to DMA'ing the SCB down from the host.  This routine assumes that
- * ARG_1 is the SCBID of interrest and that SINDEX is the position in the
- * disconnected list to start the search from.  If SINDEX is SCB_LIST_NULL,
- * we go directly to the host for the SCB.
- */
-retrieveSCB:
-	test	SEQ_FLAGS, SCBPTR_VALID	jz retrieve_from_host;
-	mov	SCBPTR	call findSCB;	/* Continue the search */
-	cmp	SINDEX, SCB_LIST_NULL	je retrieve_from_host;
-
-/*
- * This routine expects SINDEX to contain the index of the SCB to be
- * removed, SCBPTR to be pointing to that SCB, and ARG_2 to be the
- * SCBID of the SCB just previous to this one in the list or SCB_LIST_NULL
- * if it is at the head.
- */
+        cmp     SCB_TAG, A      jne findSCB_next;
 rem_scb_from_disc_list:
-/* Remove this SCB from the disconnection list */
 	cmp	ARG_2, SCB_LIST_NULL	je rHead;
 	mov	DINDEX, SCB_NEXT;
+        mov     SINDEX, SCBPTR;
 	mov	SCBPTR, ARG_2;
 	mov	SCB_NEXT, DINDEX;
 	mov	SCBPTR, SINDEX ret;
 rHead:
 	mov	DISCONNECTED_SCBH,SCB_NEXT ret;
-
-retrieve_from_host:
-/*
- * We didn't find it.  Pull an SCB and DMA down the one we want.
- * We should never get here in the non-paging case.
- */
-	mov	ALLZEROS	call	get_free_or_disc_scb;
+END_CRITICAL
+findSCB_notFound:
+        /*
+         * We didn't find it.  Page in the SCB.
+         */
+        mov     ARG_1, A; /* Save tag */
+        mov     ALLZEROS call get_free_or_disc_scb;
 	mvi	DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
-	/* Jump instead of call as we want to return anyway */
 	mov	ARG_1	jmp dma_scb;
-
-/*
- * Determine whether a target is using tagged or non-tagged transactions
- * by first looking for a matching transaction based on the TCL and if
- * that fails, looking up this device in the host's untagged SCB array.
- * The TCL to search for is assumed to be in SAVED_TCL.  The value is
- * returned in ARG_1 (SCB_LIST_NULL for tagged, SCBID for non-tagged).
- * The SCBPTR_VALID bit is set in SEQ_FLAGS if we found the information
- * in an SCB instead of having to go to the host.
- */
-get_untagged_SCBID:
-	cmp	DISCONNECTED_SCBH, SCB_LIST_NULL je get_SCBID_from_host;
-	mvi	ARG_1, SCB_LIST_NULL;
-	mov	DISCONNECTED_SCBH call findSCB;
-	cmp	SINDEX, SCB_LIST_NULL	je get_SCBID_from_host;
-	or	SEQ_FLAGS, SCBPTR_VALID;/* Was in disconnected list */
-	test	SCB_CONTROL, TAG_ENB	jnz . + 2;
-	mov	ARG_1, SCB_TAG	ret;
-	mvi	ARG_1, SCB_LIST_NULL ret;
-
-/*
- * Fetch a byte from host memory given an index of (A + (256 * SINDEX))
- * and a base address of SCBID_ADDR.  The byte is returned in RETURN_2.
- */
-fetch_byte:
-	mov	ARG_2, SINDEX;
-	if ((ahc->features & AHC_CMD_CHAN) != 0) {
-		mvi	DINDEX, CCHADDR;
-		mvi	SCBID_ADDR call set_1byte_addr;
-		mvi	CCHCNT, 1;
-		mvi	CCSGCTL, CCSGEN|CCSGRESET;
-		test	CCSGCTL, CCSGDONE jz .;
-		mvi	CCSGCTL, CCSGRESET;
-		bmov	RETURN_2, CCSGRAM, 1 ret;
-	} else {
-		mvi	DINDEX, HADDR;
-		mvi	SCBID_ADDR call set_1byte_addr;
-		mvi	HCNT[0], 1;
-		clr	HCNT[1];
-		clr	HCNT[2];
-		mvi	DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
-		call	dma_finish;
-		mov	RETURN_2, DFDAT ret;
-	}
+}
 
 /*
  * Prepare the hardware to post a byte to host memory given an
- * index of (A + (256 * SINDEX)) and a base address of SCBID_ADDR.
+ * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR.
  */
 post_byte_setup:
 	mov	ARG_2, SINDEX;
 	if ((ahc->features & AHC_CMD_CHAN) != 0) {
 		mvi	DINDEX, CCHADDR;
-		mvi	SCBID_ADDR call	set_1byte_addr;
+                mvi     SHARED_DATA_ADDR call   set_1byte_addr;
 		mvi	CCHCNT, 1;
 		mvi	CCSCBCTL, CCSCBRESET ret;
 	} else {
 		mvi	DINDEX, HADDR;
-		mvi	SCBID_ADDR call	set_1byte_addr;
-		mvi	HCNT[0], 1;
-		clr	HCNT[1];
-		clr	HCNT[2];
+                mvi     SHARED_DATA_ADDR call   set_1byte_addr;
+                mvi     1       call set_hcnt;
 		mvi	DFCNTRL, FIFORESET ret;
 	}
 
@@ -1669,13 +2041,8 @@ post_byte:
 		jmp	dma_finish;
 	}
 
-get_SCBID_from_host:
-	mov	A, SAVED_TCL;
-	mvi	UNTAGGEDSCB_OFFSET call fetch_byte;
-	mov	RETURN_1,  RETURN_2 ret;
-
 phase_lock_perr:
-	mvi	INTSTAT, PERR_DETECTED;
+        mvi     PERR_DETECTED call set_seqint;
 phase_lock:     
 	/*
 	 * If there is a parity error, wait for the kernel to
@@ -1685,15 +2052,25 @@ phase_lock:
 	test	SSTAT1, REQINIT jz phase_lock;
 	test	SSTAT1, SCSIPERR jnz phase_lock_perr;
 phase_lock_latch_phase:
-	and	SCSISIGO, PHASE_MASK, SCSISIGI;
+        if ((ahc->features & AHC_DT) == 0) {
+                and     SCSISIGO, PHASE_MASK, SCSISIGI;
+        }
 	and	LASTPHASE, PHASE_MASK, SCSISIGI ret;
 
 if ((ahc->features & AHC_CMD_CHAN) == 0) {
+set_hcnt:
+        mov     HCNT[0], SINDEX;
+clear_hcnt:
+        clr     HCNT[1];
+        clr     HCNT[2] ret;
+
 set_stcnt_from_hcnt:
 	mov	STCNT[0], HCNT[0];
 	mov	STCNT[1], HCNT[1];
 	mov	STCNT[2], HCNT[2] ret;
 
+bcopy_8:
+        mov     DINDIR, SINDIR;
 bcopy_7:
 	mov	DINDIR, SINDIR;
 	mov	DINDIR, SINDIR;
@@ -1707,7 +2084,7 @@ bcopy_3:
 	mov	DINDIR, SINDIR ret;
 }
 
-if ((ahc->flags & AHC_TARGETMODE) != 0) {
+if ((ahc->flags & AHC_TARGETROLE) != 0) {
 /*
  * Setup addr assuming that A is an index into
  * an array of 32byte objects, SINDEX contains
@@ -1733,7 +2110,7 @@ set_64byte_addr:
 	shl	A, 6;
 
 /*
- * Setup addr assuming that A + (ARG_1 * 256) is an
+ * Setup addr assuming that A + (ARG_2 * 256) is an
  * index into an array of 1byte objects, SINDEX contains
  * the base address of that array, and DINDEX contains
  * the base address of the location to store the computed
@@ -1758,17 +2135,27 @@ dma_scb:
 		mvi	HSCB_ADDR call set_64byte_addr;
 		mov	CCSCBPTR, SCBPTR;
 		test	DMAPARAMS, DIRECTION jz dma_scb_tohost;
-		mvi	CCHCNT, SCB_64BYTE_SIZE;
+                if ((ahc->flags & AHC_SCB_BTT) != 0) {
+                        mvi     CCHCNT, SCB_DOWNLOAD_SIZE_64;
+                } else {
+                        mvi     CCHCNT, SCB_DOWNLOAD_SIZE;
+                }
 		mvi	CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
 		cmp	CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
 		jmp	dma_scb_finish;
 dma_scb_tohost:
-		mvi	CCHCNT, SCB_32BYTE_SIZE;
-		if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
+                mvi     CCHCNT, SCB_UPLOAD_SIZE;
+                if ((ahc->features & AHC_ULTRA2) == 0) {
 			mvi	CCSCBCTL, CCSCBRESET;
-			bmov	CCSCBRAM, SCB_CONTROL, SCB_32BYTE_SIZE;
+                        bmov    CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE;
 			or	CCSCBCTL, CCSCBEN|CCSCBRESET;
 			test	CCSCBCTL, CCSCBDONE jz .;
+                } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
+                        mvi     CCSCBCTL, CCARREN|CCSCBRESET;
+                        cmp     CCSCBCTL, ARRDONE|CCARREN jne .;
+                        mvi     CCHCNT, SCB_UPLOAD_SIZE;
+                        mvi     CCSCBCTL, CCSCBEN|CCSCBRESET;
+                        cmp     CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
 		} else {
 			mvi	CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
 			cmp	CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
@@ -1780,45 +2167,97 @@ dma_scb_finish:
 	} else {
 		mvi	DINDEX, HADDR;
 		mvi	HSCB_ADDR call set_64byte_addr;
-		mvi	HCNT[0], SCB_32BYTE_SIZE;
-		clr	HCNT[1];
-		clr	HCNT[2];
+                mvi     SCB_DOWNLOAD_SIZE call set_hcnt;
 		mov	DFCNTRL, DMAPARAMS;
 		test	DMAPARAMS, DIRECTION	jnz dma_scb_fromhost;
 		/* Fill it with the SCB data */
 copy_scb_tofifo:
-		mvi	SINDEX, SCB_CONTROL;
-		add	A, SCB_32BYTE_SIZE, SINDEX;
+                mvi     SINDEX, SCB_BASE;
+                add     A, SCB_DOWNLOAD_SIZE, SINDEX;
 copy_scb_tofifo_loop:
-		mov	DFDAT,SINDIR;
-		mov	DFDAT,SINDIR;
-		mov	DFDAT,SINDIR;
-		mov	DFDAT,SINDIR;
-		mov	DFDAT,SINDIR;
-		mov	DFDAT,SINDIR;
-		mov	DFDAT,SINDIR;
+                call    copy_to_fifo_8;
 		cmp	SINDEX, A jne copy_scb_tofifo_loop;
 		or	DFCNTRL, HDMAEN|FIFOFLUSH;
+                jmp     dma_finish;
 dma_scb_fromhost:
-		call	dma_finish;
+                mvi     DINDEX, SCB_BASE;
+                if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
+                        /*
+                         * The PCI module will only issue a PCI
+                         * retry if the data FIFO is empty.  If the
+                         * host disconnects in the middle of a
+                         * transfer, we must empty the fifo of all
+                         * available data to force the chip to
+                         * continue the transfer.  This does not
+                         * happen for SCSI transfers as the SCSI module
+                         * will drain the FIFO as data is made available.
+                         * When the hang occurs, we know that a multiple
+                         * of 8 bytes are in the FIFO because the PCI
+                         * module has an 8 byte input latch that only
+                         * dumps to the FIFO when HCNT == 0 or the
+                         * latch is full.
+                         */
+                        clr     A;
+                        /* Wait for at least 8 bytes of data to arrive. */
+dma_scb_hang_fifo:
+                        test    DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
+dma_scb_hang_wait:
+                        test    DFSTATUS, MREQPEND jnz dma_scb_hang_wait;
+                        test    DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
+                        test    DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
+                        test    DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
+                        /*
+                         * The PCI module no longer intends to perform
+                         * a PCI transaction.  Drain the fifo.
+                         */
+dma_scb_hang_dma_drain_fifo:
+                        not     A, HCNT;
+                        add     A, SCB_DOWNLOAD_SIZE+SCB_BASE+1;
+                        and     A, ~0x7;
+                        mov     DINDIR,DFDAT;
+                        cmp     DINDEX, A jne . - 1;
+                        cmp     DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE
+                                je      dma_finish_nowait;
+                        /* Restore A as the lines left to transfer. */
+                        add     A, -SCB_BASE, DINDEX;
+                        shr     A, 3;
+                        jmp     dma_scb_hang_fifo;
+dma_scb_hang_dma_done:
+                        and     DFCNTRL, ~HDMAEN;
+                        test    DFCNTRL, HDMAEN jnz .;
+                        add     SEQADDR0, A;
+                } else {
+                        call    dma_finish;
+                }
 		/* If we were putting the SCB, we are done */
-		test	DMAPARAMS, DIRECTION	jz	return;
-		mvi	SCB_CONTROL  call dfdat_in_7;
-		call	dfdat_in_7_continued;
-		call	dfdat_in_7_continued;
-		jmp	dfdat_in_7_continued;
+                call    dfdat_in_8;
+                call    dfdat_in_8;
+                call    dfdat_in_8;
+dfdat_in_8:
+                mov     DINDIR,DFDAT;
 dfdat_in_7:
-		mov     DINDEX,SINDEX;
-dfdat_in_7_continued:
 		mov	DINDIR,DFDAT;
 		mov	DINDIR,DFDAT;
 		mov	DINDIR,DFDAT;
 		mov	DINDIR,DFDAT;
 		mov	DINDIR,DFDAT;
+dfdat_in_2:
 		mov	DINDIR,DFDAT;
 		mov	DINDIR,DFDAT ret;
 	}
 
+copy_to_fifo_8:
+        mov     DFDAT,SINDIR;
+        mov     DFDAT,SINDIR;
+copy_to_fifo_6:
+        mov     DFDAT,SINDIR;
+copy_to_fifo_5:
+        mov     DFDAT,SINDIR;
+copy_to_fifo_4:
+        mov     DFDAT,SINDIR;
+        mov     DFDAT,SINDIR;
+        mov     DFDAT,SINDIR;
+        mov     DFDAT,SINDIR ret;
 
 /*
  * Wait for DMA from host memory to data FIFO to complete, then disable
@@ -1826,37 +2265,59 @@ dfdat_in_7_continued:
  */
 dma_finish:
 	test	DFSTATUS,HDONE	jz dma_finish;
+dma_finish_nowait:
 	/* Turn off DMA */
 	and	DFCNTRL, ~HDMAEN;
 	test	DFCNTRL, HDMAEN jnz .;
 	ret;
 
+/*
+ * Restore an SCB that failed to match an incoming reselection
+ * to the correct/safe state.  If the SCB is for a disconnected
+ * transaction, it must be returned to the disconnected list.
+ * If it is not in the disconnected state, it must be free.
+ */
+cleanup_scb:
+        if ((ahc->flags & AHC_PAGESCBS) != 0) {
+                test    SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list;
+        }
 add_scb_to_free_list:
 	if ((ahc->flags & AHC_PAGESCBS) != 0) {
+BEGIN_CRITICAL
 		mov	SCB_NEXT, FREE_SCBH;
 		mvi	SCB_TAG, SCB_LIST_NULL;
 		mov	FREE_SCBH, SCBPTR ret;
+END_CRITICAL
 	} else {
 		mvi	SCB_TAG, SCB_LIST_NULL ret;
 	}
 
+if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
+set_hhaddr:
+        or      DSCOMMAND1, HADDLDSEL0;
+        and     HADDR, SG_HIGH_ADDR_BITS, SINDEX;
+        and     DSCOMMAND1, ~HADDLDSEL0 ret;
+}
+
 if ((ahc->flags & AHC_PAGESCBS) != 0) {
 get_free_or_disc_scb:
+BEGIN_CRITICAL
 	cmp	FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
 	cmp	DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
 return_error:
+        mvi     NO_FREE_SCB call set_seqint;
 	mvi	SINDEX, SCB_LIST_NULL	ret;
 dequeue_disc_scb:
 	mov	SCBPTR, DISCONNECTED_SCBH;
-dma_up_scb:
+        mov     DISCONNECTED_SCBH, SCB_NEXT;
+END_CRITICAL
 	mvi	DMAPARAMS, FIFORESET;
-	mov	SCB_TAG		call dma_scb;
-unlink_disc_scb:
-	mov	DISCONNECTED_SCBH, SCB_NEXT ret;
+        mov     SCB_TAG jmp dma_scb;
+BEGIN_CRITICAL
 dequeue_free_scb:
 	mov	SCBPTR, FREE_SCBH;
 	mov	FREE_SCBH, SCB_NEXT ret;
-}
+END_CRITICAL
 
 add_scb_to_disc_list:
 /*
@@ -1864,5 +2325,13 @@ add_scb_to_disc_list:
  * candidates for paging out an SCB if one is needed for a new command.
  * Modifying the disconnected list is a critical(pause dissabled) section.
  */
+BEGIN_CRITICAL
 	mov	SCB_NEXT, DISCONNECTED_SCBH;
 	mov	DISCONNECTED_SCBH, SCBPTR ret;
+END_CRITICAL
+}
+set_seqint:
+        mov     INTSTAT, SINDEX;
+        nop;
+return:
+        ret;
diff --git a/sys/dev/microcode/aic7xxx/aic7xxx_seq.h b/sys/dev/microcode/aic7xxx/aic7xxx_seq.h
index 9a1bde59aff..445e5c0dc49 100644
--- a/sys/dev/microcode/aic7xxx/aic7xxx_seq.h
+++ b/sys/dev/microcode/aic7xxx/aic7xxx_seq.h
@@ -1,738 +1,942 @@
+/* $OpenBSD: aic7xxx_seq.h,v 1.4 2002/02/16 04:36:33 smurph Exp $ */
 /*
- * DO NOT EDIT - This file is automatically generated.
+ * DO NOT EDIT - This file is automatically generated
+ *               from the following source files:
+ *
+ * $Id: aic7xxx_seq.h,v 1.4 2002/02/16 04:36:33 smurph Exp $
+ * $Id: aic7xxx_seq.h,v 1.4 2002/02/16 04:36:33 smurph Exp $
  */
 static u_int8_t seqprog[] = {
-	0xff, 0x6a, 0x06, 0x08,
-	0x08, 0x6a, 0x68, 0x00,
-	0x7f, 0x02, 0x04, 0x08,
-	0x32, 0x58, 0x00, 0x08,
-	0xff, 0x6a, 0xd6, 0x09,
-	0xff, 0x6a, 0xdc, 0x09,
-	0x00, 0x65, 0xec, 0x59,
+	0xb2, 0x00, 0x00, 0x08,
+	0xf7, 0x11, 0x22, 0x08,
+	0x00, 0x65, 0xde, 0x59,
 	0xf7, 0x01, 0x02, 0x08,
-	0xff, 0x4e, 0xc8, 0x08,
-	0xbf, 0x60, 0xc0, 0x08,
-	0x60, 0x0b, 0x7c, 0x68,
-	0x40, 0x00, 0x12, 0x68,
+	0xff, 0x6a, 0x24, 0x08,
+	0x40, 0x00, 0x40, 0x68,
 	0x08, 0x1f, 0x3e, 0x10,
-	0x60, 0x0b, 0x7c, 0x68,
-	0x40, 0x00, 0x0c, 0x68,
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-	0x00, 0x6a, 0x90, 0x5d,
-	0x0d, 0x6a, 0x6a, 0x00,
-	0x00, 0x52, 0x1a, 0x45,
-	0xff, 0x3f, 0xe0, 0x74,
+	0x01, 0x65, 0xc8, 0x30,
+	0xff, 0x41, 0x94, 0x75,
+	0x01, 0x41, 0x20, 0x31,
 	0xff, 0x6a, 0xa4, 0x00,
-	0x00, 0x3f, 0x5a, 0x5c,
-	0xff, 0x65, 0xe0, 0x74,
-	0x40, 0x36, 0x6c, 0x00,
-	0x20, 0xa0, 0x9a, 0x6c,
-	0xff, 0xb9, 0xa4, 0x0c,
-	0xff, 0x6a, 0xa4, 0x04,
-	0xff, 0x65, 0xa6, 0x08,
+	0x00, 0x65, 0x84, 0x45,
+	0xff, 0xbf, 0x94, 0x75,
+	0x01, 0x90, 0xa4, 0x30,
+	0x01, 0xbf, 0x20, 0x31,
+	0x00, 0xbb, 0x7e, 0x65,
+	0xff, 0x52, 0x92, 0x75,
+	0x01, 0xbf, 0xcc, 0x30,
+	0x01, 0x90, 0xca, 0x30,
+	0x01, 0x52, 0x20, 0x31,
+	0x01, 0x66, 0x7e, 0x31,
+	0x01, 0x65, 0x20, 0x35,
+	0x01, 0xbf, 0x82, 0x34,
+	0x01, 0x64, 0xa2, 0x30,
+	0x00, 0x6a, 0xa6, 0x5e,
+	0x0d, 0x6a, 0x76, 0x00,
+	0x00, 0x51, 0xf8, 0x45,
+	0x01, 0x65, 0xa4, 0x30,
 	0xe0, 0x6a, 0xcc, 0x00,
-	0x45, 0x6a, 0x0e, 0x5d,
-	0x01, 0x6a, 0xd0, 0x01,
-	0x09, 0x6a, 0xd6, 0x01,
-	0x80, 0xeb, 0xa6, 0x7c,
-	0x01, 0x6a, 0xd6, 0x01,
-	0x01, 0xe9, 0xa6, 0x34,
-	0x88, 0x6a, 0xcc, 0x00,
-	0x45, 0x6a, 0x0e, 0x5d,
-	0x01, 0x6a, 0x18, 0x01,
-	0xff, 0x6a, 0x1a, 0x09,
-	0xff, 0x6a, 0x1c, 0x09,
-	0x0d, 0x6a, 0x26, 0x01,
-	0x00, 0x65, 0x80, 0x5d,
-	0xff, 0x99, 0xa6, 0x0c,
-	0xff, 0x65, 0xa6, 0x08,
-	0xe0, 0x6a, 0xcc, 0x00,
-	0x45, 0x6a, 0x0e, 0x5d,
+	0x48, 0x6a, 0xec, 0x5d,
 	0x01, 0x6a, 0xd0, 0x01,
 	0x01, 0x6a, 0xdc, 0x05,
 	0x88, 0x6a, 0xcc, 0x00,
-	0x45, 0x6a, 0x0e, 0x5d,
-	0x01, 0x6a, 0x18, 0x01,
-	0xff, 0x6a, 0x1a, 0x09,
-	0xff, 0x6a, 0x1c, 0x09,
+	0x48, 0x6a, 0xec, 0x5d,
+	0x01, 0x6a, 0xc6, 0x5d,
 	0x01, 0x6a, 0x26, 0x05,
 	0x01, 0x65, 0xd8, 0x31,
 	0x09, 0xee, 0xdc, 0x01,
-	0x80, 0xee, 0xd6, 0x7c,
+	0x80, 0xee, 0xb2, 0x7d,
 	0xff, 0x6a, 0xdc, 0x0d,
-	0xff, 0x65, 0x32, 0x09,
+	0x01, 0x65, 0x32, 0x31,
 	0x0a, 0x93, 0x26, 0x01,
-	0x00, 0x65, 0x80, 0x45,
-	0xff, 0x37, 0xc8, 0x08,
-	0x02, 0x6a, 0x9c, 0x5c,
-	0xff, 0x53, 0xa4, 0x0c,
-	0xb1, 0x6a, 0x22, 0x01,
-	0x01, 0x0c, 0xe8, 0x7c,
-	0x04, 0x0c, 0xe6, 0x6c,
+	0x00, 0x65, 0x8e, 0x46,
+	0x81, 0x6a, 0xbe, 0x5e,
+	0x01, 0x0c, 0xbe, 0x7d,
+	0x04, 0x0c, 0xbc, 0x6d,
 	0xe0, 0x03, 0x06, 0x08,
-	0xe0, 0x03, 0x7a, 0x0c,
-	0xff, 0x8c, 0x10, 0x08,
-	0xff, 0x8d, 0x12, 0x08,
-	0xff, 0x8e, 0x14, 0x0c,
-	0xff, 0x6c, 0xda, 0x08,
-	0xff, 0x6c, 0xda, 0x08,
-	0xff, 0x6c, 0xda, 0x08,
-	0xff, 0x6c, 0xda, 0x08,
-	0xff, 0x6c, 0xda, 0x08,
-	0xff, 0x6c, 0xda, 0x08,
-	0xff, 0x6c, 0xda, 0x0c,
-	0x3d, 0x64, 0xa6, 0x28,
+	0xe0, 0x03, 0x7e, 0x0c,
+	0x01, 0x65, 0x18, 0x31,
+	0xff, 0x6a, 0x1a, 0x09,
+	0xff, 0x6a, 0x1c, 0x0d,
+	0x01, 0x8c, 0x10, 0x30,
+	0x01, 0x8d, 0x12, 0x30,
+	0x01, 0x8e, 0x14, 0x34,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x30,
+	0x01, 0x6c, 0xda, 0x34,
+	0x3d, 0x64, 0xa4, 0x28,
 	0x55, 0x64, 0xc8, 0x28,
-	0x00, 0x65, 0x0e, 0x45,
-	0x2e, 0x64, 0xa6, 0x28,
+	0x00, 0x65, 0xec, 0x45,
+	0x2e, 0x64, 0xa4, 0x28,
 	0x66, 0x64, 0xc8, 0x28,
 	0x00, 0x6c, 0xda, 0x18,
-	0xff, 0x53, 0xc8, 0x08,
+	0x01, 0x52, 0xc8, 0x30,
 	0x00, 0x6c, 0xda, 0x20,
 	0xff, 0x6a, 0xc8, 0x08,
 	0x00, 0x6c, 0xda, 0x20,
 	0x00, 0x6c, 0xda, 0x24,
-	0xff, 0x65, 0xc8, 0x08,
+	0x01, 0x65, 0xc8, 0x30,
 	0xe0, 0x6a, 0xcc, 0x00,
-	0x41, 0x6a, 0x0a, 0x5d,
-	0xff, 0x90, 0xe2, 0x09,
-	0x04, 0x35, 0x2c, 0x7d,
+	0x44, 0x6a, 0xe8, 0x5d,
+	0x01, 0x90, 0xe2, 0x31,
+	0x04, 0x3b, 0x0c, 0x7e,
 	0x30, 0x6a, 0xd0, 0x01,
+	0x20, 0x6a, 0xd0, 0x01,
 	0x1d, 0x6a, 0xdc, 0x01,
-	0xdc, 0xee, 0x28, 0x65,
-	0x00, 0x65, 0x3a, 0x45,
-	0x1c, 0x6a, 0xd0, 0x01,
+	0xdc, 0xee, 0x08, 0x66,
+	0x00, 0x65, 0x24, 0x46,
+	0x20, 0x6a, 0xd0, 0x01,
 	0x01, 0x6a, 0xdc, 0x01,
-	0x1c, 0xa0, 0xd8, 0x31,
+	0x20, 0xa0, 0xd8, 0x31,
 	0x09, 0xee, 0xdc, 0x01,
-	0x80, 0xee, 0x34, 0x7d,
+	0x80, 0xee, 0x14, 0x7e,
+	0x11, 0x6a, 0xdc, 0x01,
+	0x50, 0xee, 0x18, 0x66,
+	0x20, 0x6a, 0xd0, 0x01,
+	0x09, 0x6a, 0xdc, 0x01,
+	0x88, 0xee, 0x1e, 0x66,
 	0x19, 0x6a, 0xdc, 0x01,
-	0xd8, 0xee, 0x38, 0x65,
+	0xd8, 0xee, 0x22, 0x66,
 	0xff, 0x6a, 0xdc, 0x09,
-	0x18, 0xee, 0x3c, 0x6d,
+	0x18, 0xee, 0x26, 0x6e,
 	0xff, 0x6a, 0xd4, 0x0c,
 	0x88, 0x6a, 0xcc, 0x00,
-	0x41, 0x6a, 0x0a, 0x5d,
-	0x1c, 0x6a, 0x18, 0x01,
-	0xff, 0x6a, 0x1a, 0x09,
-	0xff, 0x6a, 0x1c, 0x09,
-	0xff, 0x35, 0x26, 0x09,
-	0x04, 0x35, 0x64, 0x6d,
+	0x44, 0x6a, 0xe8, 0x5d,
+	0x20, 0x6a, 0xc6, 0x5d,
+	0x01, 0x3b, 0x26, 0x31,
+	0x04, 0x3b, 0x40, 0x6e,
 	0xa0, 0x6a, 0xca, 0x00,
-	0x1c, 0x65, 0xc8, 0x18,
-	0xff, 0x6c, 0x32, 0x09,
-	0xff, 0x6c, 0x32, 0x09,
-	0xff, 0x6c, 0x32, 0x09,
-	0xff, 0x6c, 0x32, 0x09,
-	0xff, 0x6c, 0x32, 0x09,
-	0xff, 0x6c, 0x32, 0x09,
-	0xff, 0x6c, 0x32, 0x09,
-	0x00, 0x65, 0x52, 0x65,
+	0x20, 0x65, 0xc8, 0x18,
+	0x00, 0x65, 0x7e, 0x5e,
+	0x00, 0x65, 0x38, 0x66,
 	0x0a, 0x93, 0x26, 0x01,
-	0x00, 0x65, 0x80, 0x5d,
-	0x04, 0x35, 0x54, 0x7c,
-	0xa0, 0x6a, 0x70, 0x5d,
-	0x00, 0x65, 0x72, 0x5d,
-	0x00, 0x65, 0x72, 0x5d,
-	0x00, 0x65, 0x72, 0x45,
-	0xff, 0x65, 0xcc, 0x08,
-	0xff, 0x99, 0xda, 0x08,
-	0xff, 0x99, 0xda, 0x08,
-	0xff, 0x99, 0xda, 0x08,
-	0xff, 0x99, 0xda, 0x08,
-	0xff, 0x99, 0xda, 0x08,
-	0xff, 0x99, 0xda, 0x08,
-	0xff, 0x99, 0xda, 0x0c,
-	0x08, 0x94, 0x80, 0x7d,
+	0x00, 0x65, 0x8e, 0x46,
+	0xa0, 0x6a, 0xcc, 0x00,
+	0xff, 0x6a, 0xc8, 0x08,
+	0x20, 0x94, 0x44, 0x6e,
+	0x10, 0x94, 0x46, 0x6e,
+	0x08, 0x94, 0x60, 0x6e,
+	0x08, 0x94, 0x60, 0x6e,
+	0x08, 0x94, 0x60, 0x6e,
+	0xff, 0x8c, 0xc8, 0x10,
+	0xc1, 0x64, 0xc8, 0x18,
+	0xf8, 0x64, 0xc8, 0x08,
+	0x01, 0x99, 0xda, 0x30,
+	0x00, 0x66, 0x54, 0x66,
+	0xc0, 0x66, 0x90, 0x76,
+	0x60, 0x66, 0xc8, 0x18,
+	0x3d, 0x64, 0xc8, 0x28,
+	0x00, 0x65, 0x44, 0x46,
+	0xf7, 0x93, 0x26, 0x09,
+	0x08, 0x93, 0x62, 0x6e,
+	0x00, 0x62, 0xc4, 0x18,
+	0x00, 0x65, 0x8e, 0x5e,
+	0x00, 0x65, 0x6e, 0x5e,
+	0x00, 0x65, 0x6e, 0x5e,
+	0x00, 0x65, 0x6e, 0x5e,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x30,
+	0x01, 0x99, 0xda, 0x34,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x31,
+	0x01, 0x6c, 0x32, 0x35,
+	0x08, 0x94, 0x8e, 0x7e,
 	0xf7, 0x93, 0x26, 0x09,
-	0x08, 0x93, 0x84, 0x6d,
+	0x08, 0x93, 0x92, 0x6e,
 	0xff, 0x6a, 0xd4, 0x0c,
-	0xff, 0x40, 0x74, 0x09,
-	0xff, 0x6a, 0x72, 0x01,
-	0xff, 0x90, 0x80, 0x0c,
-	0xff, 0x6a, 0x72, 0x05,
-	0xff, 0x40, 0x9e, 0x65,
-	0xff, 0x3f, 0x96, 0x65,
+	0x04, 0xb8, 0xba, 0x6e,
+	0x01, 0x42, 0x7e, 0x31,
+	0xff, 0x6a, 0x76, 0x01,
+	0x01, 0x90, 0x84, 0x34,
+	0xff, 0x6a, 0x76, 0x05,
+	0x01, 0x85, 0x0a, 0x01,
+	0x7f, 0x65, 0x10, 0x09,
+	0xfe, 0x85, 0x0a, 0x0d,
+	0xff, 0x42, 0xb6, 0x66,
+	0xff, 0x41, 0xae, 0x66,
+	0xd1, 0x6a, 0xbe, 0x5e,
 	0xff, 0x6a, 0xca, 0x04,
-	0xff, 0x3f, 0x20, 0x09,
-	0x01, 0x6a, 0x6a, 0x00,
-	0x00, 0xb9, 0x1a, 0x5d,
-	0xff, 0xba, 0x7e, 0x0c,
-	0xff, 0x40, 0x20, 0x09,
-	0xff, 0xba, 0x80, 0x0c,
-	0xff, 0x3f, 0x74, 0x09,
-	0xff, 0x90, 0x7e, 0x0c,
+	0x01, 0x41, 0x20, 0x31,
+	0x01, 0xbf, 0x82, 0x30,
+	0x01, 0x6a, 0x76, 0x00,
+	0x00, 0xbb, 0xf8, 0x45,
+	0x01, 0x42, 0x20, 0x31,
+	0x01, 0xbf, 0x84, 0x34,
+	0x01, 0x41, 0x7e, 0x31,
+	0x01, 0x90, 0x82, 0x34,
+	0x01, 0x65, 0x22, 0x31,
+	0xff, 0x6a, 0xd4, 0x08,
+	0xff, 0x6a, 0xd4, 0x0c
 };
 
+static int ahc_patch23_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch23_func(struct ahc_softc *ahc)
+{
+	return ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0);
+}
+
+static int ahc_patch22_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch22_func(struct ahc_softc *ahc)
+{
+	return ((ahc->features & AHC_CMD_CHAN) == 0);
+}
+
+static int ahc_patch21_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch21_func(struct ahc_softc *ahc)
+{
+	return ((ahc->features & AHC_QUEUE_REGS) == 0);
+}
+
+static int ahc_patch20_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch20_func(struct ahc_softc *ahc)
+{
+	return ((ahc->features & AHC_WIDE) != 0);
+}
+
+static int ahc_patch19_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch19_func(struct ahc_softc *ahc)
+{
+	return ((ahc->flags & AHC_SCB_BTT) != 0);
+}
+
+static int ahc_patch18_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch18_func(struct ahc_softc *ahc)
+{
+	return ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0);
+}
+
+static int ahc_patch17_func(struct ahc_softc *ahc);
+
+static int
+ahc_patch17_func(struct ahc_softc *ahc)
+{
+	return ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0);
+}
+
 static int ahc_patch16_func(struct ahc_softc *ahc);
 
 static int
 ahc_patch16_func(struct ahc_softc *ahc)
 {
-	return ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895);
+	return ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0);
 }
 
 static int ahc_patch15_func(struct ahc_softc *ahc);
@@ -740,7 +944,7 @@ static int ahc_patch15_func(struct ahc_softc *ahc);
 static int
 ahc_patch15_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_WIDE) != 0);
+	return ((ahc->features & AHC_ULTRA2) == 0);
 }
 
 static int ahc_patch14_func(struct ahc_softc *ahc);
@@ -748,7 +952,7 @@ static int ahc_patch14_func(struct ahc_softc *ahc);
 static int
 ahc_patch14_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_CMD_CHAN) == 0);
+	return ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0);
 }
 
 static int ahc_patch13_func(struct ahc_softc *ahc);
@@ -756,7 +960,7 @@ static int ahc_patch13_func(struct ahc_softc *ahc);
 static int
 ahc_patch13_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_ULTRA2) == 0);
+	return ((ahc->flags & AHC_39BIT_ADDRESSING) != 0);
 }
 
 static int ahc_patch12_func(struct ahc_softc *ahc);
@@ -764,7 +968,7 @@ static int ahc_patch12_func(struct ahc_softc *ahc);
 static int
 ahc_patch12_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_HS_MAILBOX) != 0);
+	return ((ahc->features & AHC_ULTRA) != 0);
 }
 
 static int ahc_patch11_func(struct ahc_softc *ahc);
@@ -772,7 +976,7 @@ static int ahc_patch11_func(struct ahc_softc *ahc);
 static int
 ahc_patch11_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_MULTI_TID) != 0);
+	return ((ahc->features & AHC_HS_MAILBOX) != 0);
 }
 
 static int ahc_patch10_func(struct ahc_softc *ahc);
@@ -780,7 +984,7 @@ static int ahc_patch10_func(struct ahc_softc *ahc);
 static int
 ahc_patch10_func(struct ahc_softc *ahc)
 {
-	return ((ahc->flags & AHC_INITIATORMODE) != 0);
+	return ((ahc->features & AHC_MULTI_TID) != 0);
 }
 
 static int ahc_patch9_func(struct ahc_softc *ahc);
@@ -788,7 +992,7 @@ static int ahc_patch9_func(struct ahc_softc *ahc);
 static int
 ahc_patch9_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_ULTRA) != 0);
+	return ((ahc->features & AHC_CMD_CHAN) != 0);
 }
 
 static int ahc_patch8_func(struct ahc_softc *ahc);
@@ -796,7 +1000,7 @@ static int ahc_patch8_func(struct ahc_softc *ahc);
 static int
 ahc_patch8_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_ULTRA2) != 0);
+	return ((ahc->flags & AHC_INITIATORROLE) != 0);
 }
 
 static int ahc_patch7_func(struct ahc_softc *ahc);
@@ -804,7 +1008,7 @@ static int ahc_patch7_func(struct ahc_softc *ahc);
 static int
 ahc_patch7_func(struct ahc_softc *ahc)
 {
-	return ((ahc->flags & AHC_TARGETMODE) != 0);
+	return ((ahc->flags & AHC_TARGETROLE) != 0);
 }
 
 static int ahc_patch6_func(struct ahc_softc *ahc);
@@ -812,7 +1016,7 @@ static int ahc_patch6_func(struct ahc_softc *ahc);
 static int
 ahc_patch6_func(struct ahc_softc *ahc)
 {
-	return ((ahc->flags & AHC_PAGESCBS) == 0);
+	return ((ahc->features & AHC_DT) == 0);
 }
 
 static int ahc_patch5_func(struct ahc_softc *ahc);
@@ -820,7 +1024,7 @@ static int ahc_patch5_func(struct ahc_softc *ahc);
 static int
 ahc_patch5_func(struct ahc_softc *ahc)
 {
-	return ((ahc->flags & AHC_PAGESCBS) != 0);
+	return ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0);
 }
 
 static int ahc_patch4_func(struct ahc_softc *ahc);
@@ -828,7 +1032,7 @@ static int ahc_patch4_func(struct ahc_softc *ahc);
 static int
 ahc_patch4_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_QUEUE_REGS) != 0);
+	return ((ahc->flags & AHC_PAGESCBS) != 0);
 }
 
 static int ahc_patch3_func(struct ahc_softc *ahc);
@@ -836,7 +1040,7 @@ static int ahc_patch3_func(struct ahc_softc *ahc);
 static int
 ahc_patch3_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_TWIN) != 0);
+	return ((ahc->features & AHC_QUEUE_REGS) != 0);
 }
 
 static int ahc_patch2_func(struct ahc_softc *ahc);
@@ -844,7 +1048,7 @@ static int ahc_patch2_func(struct ahc_softc *ahc);
 static int
 ahc_patch2_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_QUEUE_REGS) == 0);
+	return ((ahc->features & AHC_TWIN) != 0);
 }
 
 static int ahc_patch1_func(struct ahc_softc *ahc);
@@ -852,7 +1056,7 @@ static int ahc_patch1_func(struct ahc_softc *ahc);
 static int
 ahc_patch1_func(struct ahc_softc *ahc)
 {
-	return ((ahc->features & AHC_CMD_CHAN) != 0);
+	return ((ahc->features & AHC_ULTRA2) != 0);
 }
 
 static int ahc_patch0_func(struct ahc_softc *ahc);
@@ -870,139 +1074,221 @@ struct patch {
 			skip_instr :10,
 			skip_patch :12;
 } patches[] = {
-	{ ahc_patch1_func, 4, 2, 1 },
-	{ ahc_patch2_func, 8, 1, 1 },
+	{ ahc_patch1_func, 4, 1, 1 },
+	{ ahc_patch2_func, 6, 2, 1 },
 	{ ahc_patch2_func, 9, 1, 1 },
-	{ ahc_patch3_func, 12, 4, 1 },
-	{ ahc_patch4_func, 17, 3, 2 },
-	{ ahc_patch0_func, 20, 4, 1 },
-	{ ahc_patch5_func, 24, 1, 1 },
-	{ ahc_patch6_func, 27, 1, 1 },
-	{ ahc_patch1_func, 30, 1, 2 },
-	{ ahc_patch0_func, 31, 3, 1 },
-	{ ahc_patch3_func, 40, 4, 1 },
-	{ ahc_patch7_func, 45, 5, 3 },
-	{ ahc_patch8_func, 46, 1, 2 },
-	{ ahc_patch0_func, 47, 1, 1 },
-	{ ahc_patch8_func, 50, 3, 2 },
-	{ ahc_patch0_func, 53, 3, 1 },
-	{ ahc_patch9_func, 58, 2, 1 },
-	{ ahc_patch8_func, 60, 1, 2 },
+	{ ahc_patch3_func, 11, 1, 2 },
+	{ ahc_patch0_func, 12, 2, 1 },
+	{ ahc_patch4_func, 15, 1, 2 },
+	{ ahc_patch0_func, 16, 1, 1 },
+	{ ahc_patch5_func, 22, 2, 1 },
+	{ ahc_patch3_func, 27, 1, 2 },
+	{ ahc_patch0_func, 28, 1, 1 },
+	{ ahc_patch6_func, 34, 1, 1 },
+	{ ahc_patch7_func, 37, 62, 21 },
+	{ ahc_patch8_func, 37, 1, 1 },
+	{ ahc_patch9_func, 42, 3, 2 },
+	{ ahc_patch0_func, 45, 3, 1 },
+	{ ahc_patch10_func, 49, 1, 2 },
+	{ ahc_patch0_func, 50, 2, 3 },
+	{ ahc_patch1_func, 50, 1, 2 },
+	{ ahc_patch0_func, 51, 1, 1 },
+	{ ahc_patch2_func, 53, 2, 1 },
+	{ ahc_patch9_func, 55, 1, 2 },
+	{ ahc_patch0_func, 56, 1, 1 },
+	{ ahc_patch9_func, 60, 1, 2 },
 	{ ahc_patch0_func, 61, 1, 1 },
-	{ ahc_patch7_func, 64, 65, 26 },
-	{ ahc_patch10_func, 64, 1, 1 },
-	{ ahc_patch1_func, 69, 3, 2 },
-	{ ahc_patch0_func, 72, 3, 1 },
-	{ ahc_patch1_func, 76, 1, 2 },
-	{ ahc_patch0_func, 77, 1, 1 },
-	{ ahc_patch1_func, 78, 3, 6 },
-	{ ahc_patch11_func, 78, 1, 2 },
-	{ ahc_patch0_func, 79, 2, 3 },
-	{ ahc_patch8_func, 79, 1, 2 },
-	{ ahc_patch0_func, 80, 1, 1 },
-	{ ahc_patch0_func, 81, 3, 5 },
-	{ ahc_patch11_func, 81, 1, 2 },
-	{ ahc_patch0_func, 82, 2, 3 },
-	{ ahc_patch8_func, 82, 1, 2 },
-	{ ahc_patch0_func, 83, 1, 1 },
-	{ ahc_patch1_func, 88, 1, 2 },
-	{ ahc_patch0_func, 89, 1, 1 },
-	{ ahc_patch1_func, 98, 1, 2 },
-	{ ahc_patch0_func, 99, 1, 1 },
-	{ ahc_patch1_func, 102, 1, 2 },
-	{ ahc_patch0_func, 103, 1, 1 },
-	{ ahc_patch12_func, 111, 1, 2 },
-	{ ahc_patch0_func, 112, 1, 1 },
-	{ ahc_patch1_func, 120, 1, 2 },
-	{ ahc_patch0_func, 121, 1, 1 },
-	{ ahc_patch10_func, 129, 7, 2 },
-	{ ahc_patch3_func, 130, 2, 1 },
-	{ ahc_patch7_func, 141, 85, 8 },
-	{ ahc_patch5_func, 156, 1, 1 },
-	{ ahc_patch1_func, 178, 1, 2 },
-	{ ahc_patch0_func, 179, 1, 1 },
-	{ ahc_patch1_func, 188, 1, 2 },
-	{ ahc_patch0_func, 189, 1, 1 },
-	{ ahc_patch1_func, 210, 6, 2 },
-	{ ahc_patch0_func, 216, 8, 1 },
-	{ ahc_patch10_func, 226, 20, 1 },
-	{ ahc_patch8_func, 247, 1, 2 },
-	{ ahc_patch0_func, 248, 2, 1 },
-	{ ahc_patch8_func, 252, 2, 2 },
-	{ ahc_patch0_func, 254, 3, 3 },
-	{ ahc_patch1_func, 254, 1, 2 },
-	{ ahc_patch0_func, 255, 2, 1 },
-	{ ahc_patch8_func, 259, 1, 2 },
-	{ ahc_patch0_func, 260, 1, 1 },
-	{ ahc_patch1_func, 264, 1, 1 },
-	{ ahc_patch1_func, 267, 1, 2 },
-	{ ahc_patch0_func, 268, 2, 1 },
-	{ ahc_patch13_func, 271, 2, 3 },
-	{ ahc_patch1_func, 271, 1, 2 },
-	{ ahc_patch0_func, 272, 1, 1 },
-	{ ahc_patch1_func, 273, 1, 2 },
-	{ ahc_patch0_func, 274, 2, 1 },
-	{ ahc_patch8_func, 279, 1, 2 },
-	{ ahc_patch0_func, 280, 4, 3 },
-	{ ahc_patch1_func, 280, 1, 2 },
-	{ ahc_patch0_func, 281, 3, 1 },
-	{ ahc_patch8_func, 285, 1, 2 },
-	{ ahc_patch0_func, 286, 3, 2 },
-	{ ahc_patch7_func, 286, 2, 1 },
-	{ ahc_patch8_func, 289, 5, 2 },
-	{ ahc_patch0_func, 294, 1, 1 },
-	{ ahc_patch1_func, 301, 13, 2 },
-	{ ahc_patch0_func, 314, 8, 1 },
-	{ ahc_patch13_func, 324, 2, 3 },
-	{ ahc_patch1_func, 324, 1, 2 },
-	{ ahc_patch0_func, 325, 1, 1 },
-	{ ahc_patch7_func, 329, 1, 1 },
-	{ ahc_patch8_func, 332, 2, 1 },
-	{ ahc_patch8_func, 334, 1, 1 },
-	{ ahc_patch1_func, 335, 1, 2 },
-	{ ahc_patch0_func, 336, 3, 1 },
-	{ ahc_patch8_func, 340, 1, 1 },
-	{ ahc_patch7_func, 341, 5, 1 },
-	{ ahc_patch8_func, 347, 2, 1 },
-	{ ahc_patch8_func, 352, 13, 1 },
-	{ ahc_patch10_func, 365, 96, 13 },
-	{ ahc_patch1_func, 366, 11, 5 },
-	{ ahc_patch13_func, 368, 1, 1 },
-	{ ahc_patch8_func, 372, 1, 2 },
-	{ ahc_patch0_func, 373, 1, 1 },
-	{ ahc_patch0_func, 377, 4, 1 },
-	{ ahc_patch13_func, 381, 2, 3 },
-	{ ahc_patch14_func, 381, 1, 1 },
-	{ ahc_patch0_func, 383, 1, 1 },
-	{ ahc_patch12_func, 399, 3, 1 },
-	{ ahc_patch3_func, 403, 2, 2 },
-	{ ahc_patch0_func, 405, 2, 2 },
-	{ ahc_patch15_func, 405, 2, 1 },
-	{ ahc_patch4_func, 463, 1, 2 },
-	{ ahc_patch0_func, 464, 1, 1 },
-	{ ahc_patch2_func, 467, 1, 1 },
-	{ ahc_patch10_func, 469, 58, 6 },
-	{ ahc_patch1_func, 473, 3, 2 },
-	{ ahc_patch0_func, 476, 5, 1 },
-	{ ahc_patch15_func, 484, 1, 2 },
-	{ ahc_patch0_func, 485, 1, 1 },
-	{ ahc_patch5_func, 490, 1, 1 },
-	{ ahc_patch7_func, 527, 16, 1 },
-	{ ahc_patch13_func, 552, 1, 1 },
-	{ ahc_patch1_func, 591, 7, 2 },
-	{ ahc_patch0_func, 598, 8, 1 },
-	{ ahc_patch1_func, 607, 4, 2 },
-	{ ahc_patch0_func, 611, 6, 1 },
-	{ ahc_patch1_func, 617, 4, 2 },
-	{ ahc_patch0_func, 621, 3, 1 },
-	{ ahc_patch14_func, 632, 10, 1 },
-	{ ahc_patch7_func, 642, 3, 1 },
-	{ ahc_patch1_func, 654, 18, 4 },
-	{ ahc_patch16_func, 663, 4, 2 },
-	{ ahc_patch0_func, 667, 2, 1 },
-	{ ahc_patch0_func, 672, 32, 1 },
-	{ ahc_patch5_func, 708, 3, 2 },
-	{ ahc_patch0_func, 711, 1, 1 },
-	{ ahc_patch5_func, 712, 9, 1 },
-
+	{ ahc_patch9_func, 70, 1, 2 },
+	{ ahc_patch0_func, 71, 1, 1 },
+	{ ahc_patch9_func, 74, 1, 2 },
+	{ ahc_patch0_func, 75, 1, 1 },
+	{ ahc_patch11_func, 85, 1, 2 },
+	{ ahc_patch0_func, 86, 1, 1 },
+	{ ahc_patch9_func, 94, 1, 2 },
+	{ ahc_patch0_func, 95, 1, 1 },
+	{ ahc_patch8_func, 99, 9, 4 },
+	{ ahc_patch1_func, 101, 1, 2 },
+	{ ahc_patch0_func, 102, 1, 1 },
+	{ ahc_patch2_func, 104, 2, 1 },
+	{ ahc_patch2_func, 113, 4, 1 },
+	{ ahc_patch1_func, 117, 1, 2 },
+	{ ahc_patch0_func, 118, 2, 3 },
+	{ ahc_patch2_func, 118, 1, 2 },
+	{ ahc_patch0_func, 119, 1, 1 },
+	{ ahc_patch7_func, 120, 4, 2 },
+	{ ahc_patch0_func, 124, 1, 1 },
+	{ ahc_patch12_func, 126, 2, 1 },
+	{ ahc_patch1_func, 128, 1, 2 },
+	{ ahc_patch0_func, 129, 1, 1 },
+	{ ahc_patch7_func, 130, 4, 1 },
+	{ ahc_patch7_func, 141, 80, 9 },
+	{ ahc_patch4_func, 159, 1, 1 },
+	{ ahc_patch1_func, 172, 1, 1 },
+	{ ahc_patch9_func, 180, 1, 2 },
+	{ ahc_patch0_func, 181, 1, 1 },
+	{ ahc_patch9_func, 190, 1, 2 },
+	{ ahc_patch0_func, 191, 1, 1 },
+	{ ahc_patch9_func, 207, 6, 2 },
+	{ ahc_patch0_func, 213, 6, 1 },
+	{ ahc_patch8_func, 221, 18, 2 },
+	{ ahc_patch1_func, 234, 1, 1 },
+	{ ahc_patch1_func, 241, 1, 2 },
+	{ ahc_patch0_func, 242, 2, 2 },
+	{ ahc_patch12_func, 243, 1, 1 },
+	{ ahc_patch9_func, 251, 31, 3 },
+	{ ahc_patch1_func, 267, 14, 2 },
+	{ ahc_patch13_func, 272, 1, 1 },
+	{ ahc_patch14_func, 282, 14, 1 },
+	{ ahc_patch1_func, 298, 1, 2 },
+	{ ahc_patch0_func, 299, 1, 1 },
+	{ ahc_patch9_func, 302, 1, 1 },
+	{ ahc_patch13_func, 307, 1, 1 },
+	{ ahc_patch9_func, 308, 2, 2 },
+	{ ahc_patch0_func, 310, 4, 1 },
+	{ ahc_patch14_func, 314, 1, 1 },
+	{ ahc_patch15_func, 317, 2, 3 },
+	{ ahc_patch9_func, 317, 1, 2 },
+	{ ahc_patch0_func, 318, 1, 1 },
+	{ ahc_patch6_func, 323, 1, 2 },
+	{ ahc_patch0_func, 324, 1, 1 },
+	{ ahc_patch1_func, 328, 50, 11 },
+	{ ahc_patch6_func, 337, 2, 4 },
+	{ ahc_patch7_func, 337, 1, 1 },
+	{ ahc_patch8_func, 338, 1, 1 },
+	{ ahc_patch0_func, 339, 1, 1 },
+	{ ahc_patch16_func, 340, 1, 1 },
+	{ ahc_patch6_func, 359, 6, 3 },
+	{ ahc_patch16_func, 359, 5, 1 },
+	{ ahc_patch0_func, 365, 5, 1 },
+	{ ahc_patch13_func, 373, 5, 1 },
+	{ ahc_patch0_func, 378, 54, 17 },
+	{ ahc_patch14_func, 378, 1, 1 },
+	{ ahc_patch7_func, 380, 2, 2 },
+	{ ahc_patch17_func, 381, 1, 1 },
+	{ ahc_patch9_func, 384, 1, 1 },
+	{ ahc_patch18_func, 391, 1, 1 },
+	{ ahc_patch14_func, 396, 9, 3 },
+	{ ahc_patch9_func, 397, 3, 2 },
+	{ ahc_patch0_func, 400, 3, 1 },
+	{ ahc_patch9_func, 408, 6, 2 },
+	{ ahc_patch0_func, 414, 9, 2 },
+	{ ahc_patch13_func, 414, 1, 1 },
+	{ ahc_patch13_func, 423, 2, 1 },
+	{ ahc_patch14_func, 425, 1, 1 },
+	{ ahc_patch9_func, 427, 1, 2 },
+	{ ahc_patch0_func, 428, 1, 1 },
+	{ ahc_patch7_func, 431, 1, 1 },
+	{ ahc_patch7_func, 432, 1, 1 },
+	{ ahc_patch8_func, 433, 3, 3 },
+	{ ahc_patch6_func, 434, 1, 2 },
+	{ ahc_patch0_func, 435, 1, 1 },
+	{ ahc_patch9_func, 436, 1, 1 },
+	{ ahc_patch15_func, 437, 1, 2 },
+	{ ahc_patch13_func, 437, 1, 1 },
+	{ ahc_patch14_func, 439, 9, 4 },
+	{ ahc_patch9_func, 439, 1, 1 },
+	{ ahc_patch9_func, 446, 2, 1 },
+	{ ahc_patch0_func, 448, 4, 3 },
+	{ ahc_patch9_func, 448, 1, 2 },
+	{ ahc_patch0_func, 449, 3, 1 },
+	{ ahc_patch1_func, 453, 2, 1 },
+	{ ahc_patch7_func, 455, 5, 2 },
+	{ ahc_patch0_func, 460, 1, 1 },
+	{ ahc_patch8_func, 461, 109, 23 },
+	{ ahc_patch1_func, 463, 3, 2 },
+	{ ahc_patch0_func, 466, 5, 3 },
+	{ ahc_patch9_func, 466, 2, 2 },
+	{ ahc_patch0_func, 468, 3, 1 },
+	{ ahc_patch1_func, 473, 2, 2 },
+	{ ahc_patch0_func, 475, 6, 3 },
+	{ ahc_patch9_func, 475, 2, 2 },
+	{ ahc_patch0_func, 477, 3, 1 },
+	{ ahc_patch1_func, 483, 2, 2 },
+	{ ahc_patch0_func, 485, 9, 7 },
+	{ ahc_patch9_func, 485, 5, 6 },
+	{ ahc_patch19_func, 485, 1, 2 },
+	{ ahc_patch0_func, 486, 1, 1 },
+	{ ahc_patch19_func, 488, 1, 2 },
+	{ ahc_patch0_func, 489, 1, 1 },
+	{ ahc_patch0_func, 490, 4, 1 },
+	{ ahc_patch6_func, 494, 3, 2 },
+	{ ahc_patch0_func, 497, 1, 1 },
+	{ ahc_patch1_func, 500, 1, 1 },
+	{ ahc_patch6_func, 506, 1, 2 },
+	{ ahc_patch0_func, 507, 1, 1 },
+	{ ahc_patch20_func, 544, 7, 1 },
+	{ ahc_patch3_func, 572, 1, 2 },
+	{ ahc_patch0_func, 573, 1, 1 },
+	{ ahc_patch21_func, 576, 1, 1 },
+	{ ahc_patch8_func, 578, 104, 33 },
+	{ ahc_patch4_func, 579, 1, 1 },
+	{ ahc_patch1_func, 585, 2, 2 },
+	{ ahc_patch0_func, 587, 1, 1 },
+	{ ahc_patch1_func, 590, 1, 2 },
+	{ ahc_patch0_func, 591, 1, 1 },
+	{ ahc_patch9_func, 592, 3, 3 },
+	{ ahc_patch15_func, 593, 1, 1 },
+	{ ahc_patch0_func, 595, 4, 1 },
+	{ ahc_patch19_func, 603, 2, 2 },
+	{ ahc_patch0_func, 605, 1, 1 },
+	{ ahc_patch19_func, 609, 10, 3 },
+	{ ahc_patch5_func, 611, 8, 1 },
+	{ ahc_patch0_func, 619, 9, 2 },
+	{ ahc_patch5_func, 620, 8, 1 },
+	{ ahc_patch4_func, 630, 1, 2 },
+	{ ahc_patch0_func, 631, 1, 1 },
+	{ ahc_patch19_func, 632, 1, 2 },
+	{ ahc_patch0_func, 633, 3, 2 },
+	{ ahc_patch4_func, 635, 1, 1 },
+	{ ahc_patch5_func, 636, 1, 1 },
+	{ ahc_patch5_func, 639, 1, 1 },
+	{ ahc_patch5_func, 641, 1, 1 },
+	{ ahc_patch4_func, 643, 2, 2 },
+	{ ahc_patch0_func, 645, 2, 1 },
+	{ ahc_patch5_func, 647, 1, 1 },
+	{ ahc_patch5_func, 650, 1, 1 },
+	{ ahc_patch5_func, 653, 1, 1 },
+	{ ahc_patch19_func, 657, 1, 1 },
+	{ ahc_patch19_func, 660, 1, 1 },
+	{ ahc_patch4_func, 666, 1, 1 },
+	{ ahc_patch6_func, 669, 1, 2 },
+	{ ahc_patch0_func, 670, 1, 1 },
+	{ ahc_patch7_func, 682, 16, 1 },
+	{ ahc_patch4_func, 698, 20, 1 },
+	{ ahc_patch9_func, 719, 4, 2 },
+	{ ahc_patch0_func, 723, 4, 1 },
+	{ ahc_patch9_func, 727, 4, 2 },
+	{ ahc_patch0_func, 731, 3, 1 },
+	{ ahc_patch6_func, 737, 1, 1 },
+	{ ahc_patch22_func, 739, 14, 1 },
+	{ ahc_patch7_func, 753, 3, 1 },
+	{ ahc_patch9_func, 765, 24, 8 },
+	{ ahc_patch19_func, 769, 1, 2 },
+	{ ahc_patch0_func, 770, 1, 1 },
+	{ ahc_patch15_func, 775, 4, 2 },
+	{ ahc_patch0_func, 779, 7, 3 },
+	{ ahc_patch23_func, 779, 5, 2 },
+	{ ahc_patch0_func, 784, 2, 1 },
+	{ ahc_patch0_func, 789, 42, 3 },
+	{ ahc_patch18_func, 801, 18, 2 },
+	{ ahc_patch0_func, 819, 1, 1 },
+	{ ahc_patch4_func, 843, 1, 1 },
+	{ ahc_patch4_func, 844, 3, 2 },
+	{ ahc_patch0_func, 847, 1, 1 },
+	{ ahc_patch13_func, 848, 3, 1 },
+	{ ahc_patch4_func, 851, 12, 1 }
+};
+struct cs {
+        u_int16_t       begin;
+        u_int16_t       end;
+} critical_sections[] = {
+	{ 11, 18 },
+	{ 21, 30 },
+	{ 698, 714 },
+	{ 844, 847 },
+	{ 851, 857 },
+	{ 859, 861 },
+	{ 861, 863 }
 };
+const int num_critical_sections = sizeof(critical_sections)
+                                 / sizeof(*critical_sections);
diff --git a/sys/dev/microcode/aic7xxx/aicasm.c b/sys/dev/microcode/aic7xxx/aicasm.c
index c293601fe8a..befd0444523 100644
--- a/sys/dev/microcode/aic7xxx/aicasm.c
+++ b/sys/dev/microcode/aic7xxx/aicasm.c
@@ -1,8 +1,8 @@
-/* $OpenBSD: aicasm.c,v 1.1 2000/03/22 02:50:49 smurph Exp $ */
+/* $OpenBSD: aicasm.c,v 1.2 2002/02/16 04:36:33 smurph Exp $ */
 /*
  * Aic7xxx SCSI host adapter firmware asssembler
  *
- * Copyright (c) 1997, 1998 Justin T. Gibbs.
+ * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,6 +14,9 @@
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -26,7 +29,9 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aicasm.c,v 1.23 1999/08/28 00:41:25 peter Exp $
+ * $Id: aicasm.c,v 1.2 2002/02/16 04:36:33 smurph Exp $
+ *
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm.c,v 1.32 2001/07/18 21:03:32 gibbs Exp $
  */
 #include <sys/types.h>
 #include <sys/mman.h>
@@ -72,6 +77,7 @@ char *listfilename;
 FILE *listfile;
 
 static TAILQ_HEAD(,instruction) seq_program;
+struct cs_tailq cs_tailq;
 struct scope_list scope_stack;
 symlist_t patch_functions;
 
@@ -97,6 +103,7 @@ main(argc, argv)
 	TAILQ_INIT(&patches);
 	SLIST_INIT(&search_path);
 	TAILQ_INIT(&seq_program);
+        TAILQ_INIT(&cs_tailq);
 	SLIST_INIT(&scope_stack);
 
 	/* Set Sentinal scope node */
@@ -299,28 +306,39 @@ output_code(ofile)
 {
 	struct instruction *cur_instr;
 	patch_t *cur_patch;
+        critical_section_t *cs;
 	symbol_node_t *cur_node;
 	int instrcount;
 
 	instrcount = 0;
 	fprintf(ofile,
 "/*
- * DO NOT EDIT - This file is automatically generated.
- */\n");
+ * DO NOT EDIT - This file is automatically generated
+ *               from the following source files:
+ *
+%s */\n", versions);
 
 	fprintf(ofile, "static u_int8_t seqprog[] = {\n");
 	for(cur_instr = seq_program.tqh_first;
 	    cur_instr != NULL;
 	    cur_instr = cur_instr->links.tqe_next) {
 
-		fprintf(ofile, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x,\n",
+                fprintf(ofile, "%s\t0x%02x, 0x%02x, 0x%02x, 0x%02x",
+                        cur_instr == seq_program.tqh_first ? "" : ",\n",
+#if BYTE_ORDER == LITTLE_ENDIAN
 			cur_instr->format.bytes[0],
 			cur_instr->format.bytes[1],
 			cur_instr->format.bytes[2],
 			cur_instr->format.bytes[3]);
+#else
+                        cur_instr->format.bytes[3],
+                        cur_instr->format.bytes[2],
+                        cur_instr->format.bytes[1],
+                        cur_instr->format.bytes[0]);
+#endif
 		instrcount++;
 	}
-	fprintf(ofile, "};\n\n");
+        fprintf(ofile, "\n};\n\n");
 
 	/*
 	 *  Output patch information.  Patch functions first.
@@ -352,14 +370,35 @@ struct patch {
 
 	for(cur_patch = TAILQ_FIRST(&patches);
 	    cur_patch != NULL;
-	    cur_patch = TAILQ_NEXT(cur_patch,links)) {
-		fprintf(ofile, "\t{ ahc_patch%d_func, %d, %d, %d },\n",
+            cur_patch = TAILQ_NEXT(cur_patch,links)) {
+                fprintf(ofile, "%s\t{ ahc_patch%d_func, %d, %d, %d }",
+                        cur_patch == TAILQ_FIRST(&patches) ? "" : ",\n",
 			cur_patch->patch_func, cur_patch->begin,
 			cur_patch->skip_instr, cur_patch->skip_patch);
+        }
+
+        fprintf(ofile, "\n};\n");
+
+        fprintf(ofile,
+"struct cs {
+        u_int16_t       begin;
+        u_int16_t       end;
+} critical_sections[] = {\n");
+
+        for(cs = TAILQ_FIRST(&cs_tailq);
+            cs != NULL;
+            cs = TAILQ_NEXT(cs, links)) {
+                fprintf(ofile, "%s\t{ %d, %d }",
+                        cs == TAILQ_FIRST(&cs_tailq) ? "" : ",\n",
+                        cs->begin_addr, cs->end_addr);
 	}
 
 	fprintf(ofile, "\n};\n");
 
+        fprintf(ofile,
+"const int num_critical_sections = sizeof(critical_sections)
+                                 / sizeof(*critical_sections);\n");
+
 	fprintf(stderr, "%s: %d instructions used\n", appname, instrcount);
 }
 
@@ -454,6 +493,7 @@ output_listing(FILE *listfile, char *ifilename)
 	    cur_func = SLIST_NEXT(cur_func, links))
 		func_count++;
 
+        func_values = NULL;
 	if (func_count != 0) {
 		func_values = (int *)malloc(func_count * sizeof(int));
 
@@ -518,10 +558,17 @@ output_listing(FILE *listfile, char *ifilename)
 				line++;
 		}
 		fprintf(listfile, "%03x %02x%02x%02x%02x", instrptr,
+#if BYTE_ORDER == LITTLE_ENDIAN
 			cur_instr->format.bytes[0],
 			cur_instr->format.bytes[1],
 			cur_instr->format.bytes[2],
 			cur_instr->format.bytes[3]);
+#else
+                        cur_instr->format.bytes[3],
+                        cur_instr->format.bytes[2],
+                        cur_instr->format.bytes[1],
+                        cur_instr->format.bytes[0]);
+#endif
 		fgets(buf, sizeof(buf), ifile);
 		fprintf(listfile, "\t%s", buf);
 		line++;
@@ -634,6 +681,20 @@ seq_alloc()
 	return new_instr;
 }
 
+critical_section_t *
+cs_alloc()
+{
+        critical_section_t *new_cs;
+
+        new_cs= (critical_section_t *)malloc(sizeof(critical_section_t));
+        if (new_cs == NULL)
+                stop("Unable to malloc critical_section object", EX_SOFTWARE);
+        memset(new_cs, 0, sizeof(*new_cs));
+        
+        TAILQ_INSERT_TAIL(&cs_tailq, new_cs, links);
+        return new_cs;
+}
+
 scope_t *
 scope_alloc()
 {
diff --git a/sys/dev/microcode/aic7xxx/aicasm.h b/sys/dev/microcode/aic7xxx/aicasm.h
index 92f7e17a62b..da57c52d723 100644
--- a/sys/dev/microcode/aic7xxx/aicasm.h
+++ b/sys/dev/microcode/aic7xxx/aicasm.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: aicasm.h,v 1.1 2000/03/22 02:50:49 smurph Exp $ */
+/* $OpenBSD: aicasm.h,v 1.2 2002/02/16 04:36:33 smurph Exp $ */
 /*
  * Assembler for the sequencer program downloaded to Aic7xxx SCSI host adapters
  *
@@ -14,6 +14,9 @@
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -26,7 +29,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aicasm.h,v 1.6 1999/12/06 18:23:30 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm.h,v 1.13 2001/07/18 21:03:32 gibbs Exp $
  */
 
 #include <sys/queue.h>
@@ -54,15 +57,18 @@ typedef enum {
 SLIST_HEAD(path_list, path_entry);
 
 extern struct path_list search_path;
+extern struct cs_tailq cs_tailq;
 extern struct scope_list scope_stack;
 extern struct symlist patch_functions;
 extern int includes_search_curdir;		/* False if we've seen -I- */
 extern char *appname;
 extern int yylineno;
 extern char *yyfilename;
+extern char *versions;
 
 void stop(const char *errstring, int err_code);
 void include_file(char *file_name, include_type type);
 struct instruction *seq_alloc(void);
+struct critical_section *cs_alloc(void);
 struct scope *scope_alloc(void);
 void process_scope(struct scope *);
diff --git a/sys/dev/microcode/aic7xxx/aicasm_gram.y b/sys/dev/microcode/aic7xxx/aicasm_gram.y
index 38b0dbcb53e..c2889c5c2ba 100644
--- a/sys/dev/microcode/aic7xxx/aicasm_gram.y
+++ b/sys/dev/microcode/aic7xxx/aicasm_gram.y
@@ -2,7 +2,7 @@
 /*
  * Parser for the Aic7xxx SCSI Host adapter sequencer assembler.
  *
- * Copyright (c) 1997-1998 Justin T. Gibbs.
+ * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,6 +14,9 @@
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -26,7 +29,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aicasm_gram.y,v 1.8 1999/12/06 18:23:30 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_gram.y,v 1.15 2001/07/18 21:03:32 gibbs Exp $
  */
 
 #include <stdio.h>
@@ -43,6 +46,7 @@
 
 int yylineno;
 char *yyfilename;
+char *versions;
 static symbol_t *cur_symbol;
 static symtype cur_symtype;
 static symbol_t *accumulator;
@@ -53,6 +57,7 @@ static symbol_ref_t sindex;
 static int instruction_ptr;
 static int sram_or_scb_offset;
 static int download_constant_count;
+static int in_critical_section;
 
 static void process_bitmask __P((int mask_type, symbol_t *sym, int mask));
 static void initialize_symbol __P((symbol_t *symbol));
@@ -71,6 +76,7 @@ static void type_check __P((symbol_t *symbol, expression_t *expression,
 			    int and_op));
 static void make_expression __P((expression_t *immed, int value));
 static void add_conditional __P((symbol_t *symbol));
+static void add_version __P((const char *));
 static int  is_download_const __P((expression_t *immed));
 
 #define YYDEBUG 1
@@ -106,17 +112,21 @@ static int  is_download_const __P((expression_t *immed));
 
 %token <value> T_MODE
 
+%token T_BEGIN_CS
+
+%token T_END_CS
+
 %token T_BIT
 
 %token T_MASK
 
 %token <value> T_NUMBER
 
-%token <str> T_PATH
+%token <str> T_PATH T_STRING
 
 %token <sym> T_CEXPR
 
-%token T_EOF T_INCLUDE 
+%token T_EOF T_INCLUDE T_VERSION
 
 %token <value> T_SHR T_SHL T_ROR T_ROL
 
@@ -130,7 +140,7 @@ static int  is_download_const __P((expression_t *immed));
 
 %token <value> T_STC T_CLC
 
-%token <value> T_CMP T_XOR
+%token <value> T_CMP T_NOT T_XOR
 
 %token <value> T_TEST T_AND
 
@@ -168,6 +178,8 @@ static int  is_download_const __P((expression_t *immed));
 program:
 	include
 |	program include
+|       version
+|       program version
 |	register
 |	program register
 |	constant
@@ -178,6 +190,10 @@ program:
 |	program scb
 |	label
 |	program label
+|       critical_section_start
+|       program critical_section_start
+|       critical_section_end
+|       program critical_section_end
 |	conditional
 |	program conditional
 |	code
@@ -186,9 +202,18 @@ program:
 
 include:
 	T_INCLUDE '<' T_PATH '>'
-	{ include_file($3, BRACKETED_INCLUDE); }
+        {
+                include_file($3, BRACKETED_INCLUDE);
+        }
 |	T_INCLUDE '"' T_PATH '"'
-	{ include_file($3, QUOTED_INCLUDE); }
+        {
+                include_file($3, QUOTED_INCLUDE);
+        }
+;
+
+version:
+        T_VERSION '=' T_STRING
+        { add_version($3); }
 ;
 
 register:
@@ -527,6 +552,8 @@ scb:
 			}
 			cur_symbol->type = SCBLOC;
 			initialize_symbol(cur_symbol);
+                        /* 64 bytes of SCB space */
+                        cur_symbol->info.rinfo->size = 64;
 		}
 		reg_address
 		{
@@ -551,6 +578,21 @@ reg_symbol:
 		$$.symbol = $1;
 		$$.offset = 0;
 	}
+|       T_SYMBOL '[' T_SYMBOL ']'
+        {
+                process_register(&$1);
+                if ($3->type != CONST) {
+                        stop("register offset must be a constant", EX_DATAERR);
+                        /* NOTREACHED */
+                }
+                if (($3->info.cinfo->value + 1) > $1->info.rinfo->size) {
+                        stop("Accessing offset beyond range of register",
+                             EX_DATAERR);
+                        /* NOTREACHED */
+                }
+                $$.symbol = $1;
+                $$.offset = $3->info.cinfo->value;
+        }
 |	T_SYMBOL '[' T_NUMBER ']'
 	{
 		process_register(&$1);
@@ -621,6 +663,35 @@ ret:
 	{ $$ = 1; }
 ;
 
+critical_section_start:
+        T_BEGIN_CS
+        {
+                critical_section_t *cs;
+
+                if (in_critical_section != FALSE) {
+                        stop("Critical Section within Critical Section",
+                             EX_DATAERR);
+                        /* NOTREACHED */
+                }
+                cs = cs_alloc();
+                cs->begin_addr = instruction_ptr;
+                in_critical_section = TRUE;
+        }
+
+critical_section_end:
+        T_END_CS
+        {
+                critical_section_t *cs;
+
+                if (in_critical_section == FALSE) {
+                        stop("Unballanced 'end_cs'", EX_DATAERR);
+                        /* NOTREACHED */
+                }
+                cs = TAILQ_LAST(&cs_tailq, cs_tailq);
+                cs->end_addr = instruction_ptr;
+                in_critical_section = FALSE;
+        }
+
 label:
 	T_SYMBOL ':'
 	{
@@ -732,7 +803,6 @@ conditional:
 	'}'
 	{
 		scope_t *scope_context;
-		scope_t *last_scope;
 
 		scope_context = SLIST_FIRST(&scope_stack);
 		if (scope_context->type == SCOPE_ROOT) {
@@ -838,8 +908,8 @@ code:
 	{
 		expression_t immed;
 
-		make_expression(&immed, 0xff);
-		format_1_instr(AIC_OP_AND, &$2, &immed, &$4, $5);
+                make_expression(&immed, 1);
+                format_1_instr(AIC_OP_BMOV, &$2, &immed, &$4, $5);
 	}
 ;
 
@@ -847,6 +917,16 @@ code:
 	T_MVI destination ',' immediate_or_a ret ';'
 	{
 		format_1_instr(AIC_OP_OR, &$2, &$4, &allzeros, $5);
+        }
+;
+
+code:
+        T_NOT destination opt_source ret ';'
+        {
+                expression_t immed;
+
+                make_expression(&immed, 0xff);
+                format_1_instr(AIC_OP_XOR, &$2, &immed, &$3, $4);
 	}
 ;
 
@@ -1391,6 +1471,27 @@ add_conditional(symbol)
 	symlist_add(&patch_functions, symbol, SYMLIST_INSERT_HEAD);
 }
 
+static void
+add_version(verstring)
+const char *verstring;
+{
+        const char prefix[] = " * ";
+        int newlen;
+        int oldlen;
+
+        newlen = strlen(verstring) + strlen(prefix);
+        oldlen = 0;
+        if (versions != NULL)
+                oldlen = strlen(versions);
+        versions = realloc(versions, newlen + oldlen + 2);
+        if (versions == NULL)
+                stop("Can't allocate version string", EX_SOFTWARE);
+        strcpy(&versions[oldlen], prefix);
+        strcpy(&versions[oldlen + strlen(prefix)], verstring);
+        versions[newlen + oldlen] = '\n';
+        versions[newlen + oldlen + 1] = '\0';
+}
+
 void
 yyerror(string)
 	const char *string;
diff --git a/sys/dev/microcode/aic7xxx/sequencer.h b/sys/dev/microcode/aic7xxx/aicasm_insformat.h
index 4c57a8d5405..d944973adeb 100644
--- a/sys/dev/microcode/aic7xxx/sequencer.h
+++ b/sys/dev/microcode/aic7xxx/aicasm_insformat.h
@@ -1,9 +1,8 @@
-/* $OpenBSD: sequencer.h,v 1.1 2000/03/22 02:50:50 smurph Exp $ */
 /*
  * Instruction formats for the sequencer program downloaded to
  * Aic7xxx SCSI host adapters
  *
- * Copyright (c) 1997, 1998 Justin T. Gibbs.
+ * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -16,7 +15,7 @@
  *    derived from this software without specific prior written permission.
  *
  * Alternatively, this software may be distributed under the terms of the
- * the GNU Public License ("GPL").
+ * GNU Public License ("GPL").
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -30,41 +29,75 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/sequencer.h,v 1.6 1999/12/06 18:23:31 gibbs Exp $
+ * $Id: aicasm_insformat.h,v 1.1 2002/02/16 04:36:33 smurph Exp $
+ *
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_insformat.h,v 1.4 2000/11/10 19:54:17 gibbs Exp $
  */
 
+#if linux
+#include <endian.h>
+#else
+#include <machine/endian.h>
+#endif
+
 struct ins_format1 {
-	u_int32_t	immediate	: 8,
+#if BYTE_ORDER == LITTLE_ENDIAN
+	uint32_t	immediate	: 8,
 			source		: 9,
 			destination	: 9,
 			ret		: 1,
 			opcode		: 4,
 			parity		: 1;
+#else
+	uint32_t	parity		: 1,
+			opcode		: 4,
+			ret		: 1,
+			destination	: 9,
+			source		: 9,
+			immediate	: 8;
+#endif
 };
 
 struct ins_format2 {
-	u_int32_t	shift_control	: 8,
+#if BYTE_ORDER == LITTLE_ENDIAN
+	uint32_t	shift_control	: 8,
 			source		: 9,
 			destination	: 9,
 			ret		: 1,
 			opcode		: 4,
 			parity		: 1;
+#else
+	uint32_t	parity		: 1,
+			opcode		: 4,
+			ret		: 1,
+			destination	: 9,
+			source		: 9,
+			shift_control	: 8;
+#endif
 };
 
 struct ins_format3 {
-	u_int32_t	immediate	: 8,
+#if BYTE_ORDER == LITTLE_ENDIAN
+	uint32_t	immediate	: 8,
 			source		: 9,
 			address		: 10,
 			opcode		: 4,
 			parity		: 1;
+#else
+	uint32_t	parity		: 1,
+			opcode		: 4,
+			address		: 10,
+			source		: 9,
+			immediate	: 8;
+#endif
 };
 
 union ins_formats {
 		struct ins_format1 format1;
 		struct ins_format2 format2;
 		struct ins_format3 format3;
-		u_int8_t	   bytes[4];
-		u_int32_t	   integer;
+		uint8_t		   bytes[4];
+		uint32_t	   integer;
 };
 struct instruction {
 	union	ins_formats format;
diff --git a/sys/dev/microcode/aic7xxx/aicasm_scan.l b/sys/dev/microcode/aic7xxx/aicasm_scan.l
index 20cae61b096..c3098c3aae3 100644
--- a/sys/dev/microcode/aic7xxx/aicasm_scan.l
+++ b/sys/dev/microcode/aic7xxx/aicasm_scan.l
@@ -2,7 +2,7 @@
 /*
  * Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler.
  *
- * Copyright (c) 1997-1998 Justin T. Gibbs.
+ * Copyright (c) 1997, 1998 Justin T. Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -14,6 +14,9 @@
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -26,7 +29,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aicasm_scan.l,v 1.8 1999/12/06 18:23:30 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm_scan.l,v 1.15 1999/12/06 18:23:30 gibbs Exp $
  */
 
 #include <sys/types.h>
@@ -45,8 +48,11 @@
 char string_buf[MAX_STR_CONST];
 char *string_buf_ptr;
 int  parren_count;
+int  quote_count;
 %}
 
+%option nounput
+
 PATH		[-/A-Za-z0-9_.]*[./][-/A-Za-z0-9_.]*
 WORD		[A-Za-z_][-A-Za-z_0-9]*
 SPACE		[ \t]+
@@ -54,6 +60,7 @@ SPACE		[ \t]+
 %x COMMENT
 %x CEXPR
 %x INCLUDE
+%x STRING
 
 %%
 \n			{ ++yylineno; }
@@ -85,12 +92,41 @@ if[ \t]*\(		{
 			}
 <CEXPR>\n		{ ++yylineno; }
 <CEXPR>[^()\n]+		{
-				char *yptr = yytext;
-
-				while (*yptr != '\0')
+                                char *yptr;
+
+                                yptr = yytext;
+                                while (*yptr != '\0') {
+                                        /* Remove duplicate spaces */
+                                        if (*yptr == '\t')
+                                                *yptr = ' ';
+                                        if (*yptr == ' '
+                                         && string_buf_ptr != string_buf
+                                         && string_buf_ptr[-1] == ' ')
+                                                yptr++;
+                                        else 
 					*string_buf_ptr++ = *yptr++;
-			}
+                                }
+                        }
 
+VERSION                 { return T_VERSION; }
+\"                      {
+                                string_buf_ptr = string_buf;
+                                BEGIN STRING;
+			}
+<STRING>[^"]+           {
+                                char *yptr;
+
+                                yptr = yytext;
+                                while (*yptr)
+                                        *string_buf_ptr++ = *yptr++;
+                        }
+<STRING>\"              {
+                                /* All done */
+                                BEGIN INITIAL;
+                                *string_buf_ptr = '\0';
+                                yylval.str = string_buf;
+                                return T_STRING;
+                        }
 {SPACE}			;
 
 	/* Register/SCB/SRAM definition keywords */
@@ -108,6 +144,8 @@ RW|RO|WO		{
 					yylval.value = WO;
 				 return T_MODE;
 			}
+BEGIN_CRITICAL          { return T_BEGIN_CS; }
+END_CRITICAL            { return T_END_CS; }
 bit			{ return T_BIT; }
 mask			{ return T_MASK; }
 alias			{ return T_ALIAS; }
@@ -145,6 +183,7 @@ dec			{ return T_DEC; }
 stc			{ return T_STC;	}
 clc			{ return T_CLC; }
 cmp			{ return T_CMP;	}
+not                     { return T_NOT; }
 xor			{ return T_XOR;	}
 test			{ return T_TEST;}
 and			{ return T_AND;	}
@@ -154,7 +193,7 @@ nop			{ return T_NOP; }
 else			{ return T_ELSE; }
 
 	/* Allowed Symbols */
-[-+,:()~|&."{};<>[\]!]	{ return yytext[0]; }
+[-+,:()~|&."{};<>[\]!=] { return yytext[0]; }
 
 	/* Number processing */
 0[0-7]*			{
@@ -173,17 +212,36 @@ else			{ return T_ELSE; }
 			}
 
 	/* Include Files */
-#include		{ return T_INCLUDE; BEGIN INCLUDE;}
-<INCLUDE>[<>\"]		{ return yytext[0]; }
-<INCLUDE>{PATH}		{ yylval.str = strdup(yytext); return T_PATH; }
-<INCLUDE>;		{ BEGIN INITIAL; return yytext[0]; }
+#include{SPACE}         {
+                                BEGIN INCLUDE;
+                                quote_count = 0;
+                                return T_INCLUDE;
+                        }
+<INCLUDE>[<]            { return yytext[0]; }
+<INCLUDE>[>]            { BEGIN INITIAL; return yytext[0]; }
+<INCLUDE>[\"]           {
+                                if (quote_count != 0)
+                                        BEGIN INITIAL;
+                                quote_count++;
+                                return yytext[0];
+                        }
 <INCLUDE>.		{ stop("Invalid include line", EX_DATAERR); }
 
 	/* For parsing C include files with #define foo */
 #define			{ yylval.value = TRUE; return T_CONST; }
 	/* Throw away macros */
 #define[^\n]*[()]+[^\n]* ;
-{PATH}			{ yylval.str = strdup(yytext); return T_PATH; }
+<INITIAL,INCLUDE>{PATH} {
+                                char *yptr;
+
+                                yptr = yytext;
+                                string_buf_ptr = string_buf;
+                                while (*yptr)
+                                        *string_buf_ptr++ = *yptr++;
+                                yylval.str = string_buf;
+                                *string_buf_ptr = '\0';
+                                return T_PATH;
+                        }
 
 {WORD}			{ yylval.sym = symtable_get(yytext);  return T_SYMBOL; }
 
diff --git a/sys/dev/microcode/aic7xxx/aicasm_symbol.c b/sys/dev/microcode/aic7xxx/aicasm_symbol.c
index 4f799bcbc50..5c2f5c47afd 100644
--- a/sys/dev/microcode/aic7xxx/aicasm_symbol.c
+++ b/sys/dev/microcode/aic7xxx/aicasm_symbol.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: aicasm_symbol.c,v 1.1 2000/03/22 02:50:49 smurph Exp $ */
+/* $OpenBSD: aicasm_symbol.c,v 1.2 2002/02/16 04:36:33 smurph Exp $ */
 /*
  * Aic7xxx SCSI host adapter firmware asssembler symbol table implementation
  *
@@ -14,6 +14,9 @@
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -26,10 +29,9 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aicasm_symbol.c,v 1.8 1999/12/06 18:23:30 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_symbol.c,v 1.14 2001/07/18 21:03:32 gibbs Exp $
  */
 
-
 #include <sys/types.h>
 
 #include <db.h>
@@ -394,9 +396,11 @@ symtable_dump(ofile)
 		/* Output what we have */
 		fprintf(ofile,
 "/*
- * DO NOT EDIT - This file is automatically generated.
- */\n");
-		while (registers.slh_first != NULL) {
+ * DO NOT EDIT - This file is automatically generated
+ *               from the following source files:
+ *
+%s */\n", versions);
+                while (registers.slh_first != NULL) {
 			symbol_node_t *curnode;
 			u_int8_t value;
 			char *tab_str;
@@ -470,4 +474,3 @@ symtable_dump(ofile)
 		}
 	}
 }
-
diff --git a/sys/dev/microcode/aic7xxx/aicasm_symbol.h b/sys/dev/microcode/aic7xxx/aicasm_symbol.h
index 201b1c043f0..f691c8f8be3 100644
--- a/sys/dev/microcode/aic7xxx/aicasm_symbol.h
+++ b/sys/dev/microcode/aic7xxx/aicasm_symbol.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: aicasm_symbol.h,v 1.1 2000/03/22 02:50:50 smurph Exp $ */
+/* $OpenBSD: aicasm_symbol.h,v 1.2 2002/02/16 04:36:33 smurph Exp $ */
 /*
  * Aic7xxx SCSI host adapter firmware asssembler symbol table definitions
  *
@@ -14,6 +14,9 @@
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -26,7 +29,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/dev/aic7xxx/aicasm_symbol.h,v 1.6 1999/12/06 18:23:31 gibbs Exp $
+ * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_symbol.h,v 1.12 2000/11/10 19:54:17 gibbs Exp $
  */
 
 #include <sys/queue.h>
@@ -111,6 +114,12 @@ typedef struct symbol_node {
 	symbol_t *symbol;
 }symbol_node_t;
 
+typedef struct critical_section {
+        TAILQ_ENTRY(critical_section) links;
+        int begin_addr;
+        int end_addr;
+} critical_section_t;
+
 typedef enum {
 	SCOPE_ROOT,
 	SCOPE_IF,
@@ -135,6 +144,7 @@ typedef struct scope {
 	int func_num;
 } scope_t;
 
+TAILQ_HEAD(cs_tailq, critical_section);
 SLIST_HEAD(scope_list, scope);
 TAILQ_HEAD(scope_tailq, scope);
 
@@ -160,3 +170,4 @@ void	symlist_free __P((symlist_t *symlist));
 void	symlist_merge __P((symlist_t *symlist_dest, symlist_t *symlist_src1,
 			   symlist_t *symlist_src2));
 void	symtable_dump __P((FILE *ofile));
+