regen

1 files changed, 87 insertions, 86 deletions

diff --git a/sys/dev/mii/miidevs.h b/sys/dev/mii/miidevs.h
index 10719be38d4..0cc51f1b82a 100644
--- a/sys/dev/mii/miidevs.h
+++ b/sys/dev/mii/miidevs.h
@@ -1,10 +1,10 @@
-/*	$OpenBSD: miidevs.h,v 1.104 2008/09/25 20:51:20 brad Exp $	*/
+/*	$OpenBSD: miidevs.h,v 1.105 2008/10/24 23:04:30 brad Exp $	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	OpenBSD: miidevs,v 1.101 2008/09/25 20:51:10 brad Exp 
+ *	OpenBSD: miidevs,v 1.102 2008/10/24 23:01:50 brad Exp 
  */
 /* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
 
@@ -41,67 +41,66 @@
 /*
  * List of known MII OUIs
  */
-
-#define	MII_OUI_VITESSE	0x0001c1	/* Vitesse */
-#define	MII_OUI_3COM	0x00105a	/* 3com */
-#define	MII_OUI_LUCENT	0x00601d	/* Lucent Technologies */
-#define	MII_OUI_ALTIMA	0x0010a9	/* Altima Communications */
 #define	MII_OUI_AMD	0x00001a	/* Advanced Micro Devices */
-#define	MII_OUI_ATHEROS	0x001374	/* Atheros Communications */
+#define	MII_OUI_REALTEK	0x000020	/* Realtek Semiconductor */
+#define	MII_OUI_VITESSE	0x0001c1	/* Vitesse */
+#define	MII_OUI_CICADA	0x0003f1	/* Cicada Semiconductor */
+#define	MII_OUI_CENIX	0x000749	/* CENiX Inc. */
+#define	MII_OUI_BROADCOM2	0x000af7	/* Broadcom Corporation */
 #define	MII_OUI_ASIX	0x000ec6	/* ASIX Electronics */
 #define	MII_OUI_BROADCOM	0x001018	/* Broadcom Corporation */
-#define	MII_OUI_BROADCOM2	0x000af7	/* Broadcom Corporation */
-#define	MII_OUI_CENIX	0x000749	/* CENiX Inc. */
-#define	MII_OUI_CICADA	0x0003f1	/* Cicada Semiconductor */
+#define	MII_OUI_3COM	0x00105a	/* 3com */
+#define	MII_OUI_ALTIMA	0x0010a9	/* Altima Communications */
 #define	MII_OUI_ENABLESEMI	0x0010dd	/* Enable Semiconductor */
-#define	MII_OUI_DAVICOM	0x00606e	/* Davicom Semiconductor */
+#define	MII_OUI_ATHEROS	0x001374	/* Atheros Communications */
+#define	MII_OUI_JMICRON	0x001b8c	/* JMicron Technologies */
+#define	MII_OUI_LEVEL1	0x00207b	/* Level 1 */
+#define	MII_OUI_VIA	0x004063	/* VIA Networking Technologies */
 #define	MII_OUI_MARVELL	0x005043	/* Marvell Semiconductor */
+#define	MII_OUI_LUCENT	0x00601d	/* Lucent Technologies */
+#define	MII_OUI_QUALSEMI	0x006051	/* Quality Semiconductor */
+#define	MII_OUI_DAVICOM	0x00606e	/* Davicom Semiconductor */
+#define	MII_OUI_SMSC	0x00800f	/* Standard Microsystems */
 #define	MII_OUI_ICPLUS	0x0090c3	/* IC Plus Corp. */
+#define	MII_OUI_TOPIC	0x0090c3	/* Topic Semiconductor */
 #define	MII_OUI_AGERE	0x00a0bc	/* Agere */
 #define	MII_OUI_ICS	0x00a0be	/* Integrated Circuit Systems */
+#define	MII_OUI_SEEQ	0x00a07d	/* Seeq */
 #define	MII_OUI_INTEL	0x00aa00	/* Intel */
-#define	MII_OUI_JATO	0x00e083	/* Jato Technologies */
-#define	MII_OUI_JMICRON	0x001b8c	/* JMicron Technologies */
-#define	MII_OUI_LEVEL1	0x00207b	/* Level 1 */
+#define	MII_OUI_TSC	0x00c039	/* TDK Semiconductor */
 #define	MII_OUI_MYSON	0x00c0b4	/* Myson Technology */
-#define	MII_OUI_NATSEMI	0x080017	/* National Semiconductor */
-#define	MII_OUI_PLESSEY	0x046b40	/* Plessey Semiconductor */
 #define	MII_OUI_PMCSIERRA	0x00e004	/* PMC-Sierra */
-#define	MII_OUI_QUALSEMI	0x006051	/* Quality Semiconductor */
-#define	MII_OUI_REALTEK	0x000020	/* Realtek Semiconductor */
-#define	MII_OUI_REALTEK2	0x00e04c	/* Realtek Semiconductor */
-#define	MII_OUI_SEEQ	0x00a07d	/* Seeq */
 #define	MII_OUI_SIS	0x00e006	/* Silicon Integrated Systems */
-#define	MII_OUI_SMSC	0x00800f	/* Standard Microsystems */
-#define	MII_OUI_TI	0x080028	/* Texas Instruments */
-#define	MII_OUI_TOPIC	0x0090c3	/* Topic Semiconductor */
-#define	MII_OUI_TSC	0x00c039	/* TDK Semiconductor */
-#define	MII_OUI_VIA	0x004063	/* VIA Networking Technologies */
+#define	MII_OUI_REALTEK2	0x00e04c	/* Realtek Semiconductor */
+#define	MII_OUI_JATO	0x00e083	/* Jato Technologies */
 #define	MII_OUI_XAQTI	0x00e0ae	/* XaQti Corp. */
+#define	MII_OUI_PLESSEY	0x046b40	/* Plessey Semiconductor */
+#define	MII_OUI_NATSEMI	0x080017	/* National Semiconductor */
+#define	MII_OUI_TI	0x080028	/* Texas Instruments */
 
 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
 #define	MII_OUI_xxALTIMA	0x000895	/* Altima Communications */
 #define	MII_OUI_xxAMD	0x00606e	/* Advanced Micro Devices */
-#define	MII_OUI_xxINTEL	0x00f800	/* Intel (alt) */
 #define	MII_OUI_xxCICADA	0x00c08f	/* Cicada Semiconductor (alt) */
+#define	MII_OUI_xxINTEL	0x00f800	/* Intel (alt) */
 
 /* some vendors have the bits swapped within bytes
 	(ie, ordered as on the wire) */
-#define	MII_OUI_xxBROADCOM	0x000818	/* Broadcom Corporation */
 #define	MII_OUI_xxICS	0x00057d	/* Integrated Circuit Systems */
 #define	MII_OUI_xxSEEQ	0x0005be	/* Seeq */
 #define	MII_OUI_xxSIS	0x000760	/* Silicon Integrated Systems */
+#define	MII_OUI_xxBROADCOM	0x000818	/* Broadcom Corporation */
 #define	MII_OUI_xxTI	0x100014	/* Texas Instruments */
 #define	MII_OUI_xxXAQTI	0x350700	/* XaQti Corp. */
 
 /* Level 1 is completely different - from right to left.
 	(Two bits get lost in the third OUI byte.) */
-#define	MII_OUI_xxLEVEL1	0x1e0400	/* Level 1 */
 #define	MII_OUI_xxLEVEL1a	0x0004de	/* Level 1 */
+#define	MII_OUI_xxLEVEL1	0x1e0400	/* Level 1 */
 
 /* Don't know what's going on here. */
-#define	MII_OUI_xxDAVICOM	0x006040	/* Davicom Semiconductor */
 #define	MII_OUI_xxBROADCOM2	0x0050ef	/* Broadcom Corporation */
+#define	MII_OUI_xxDAVICOM	0x006040	/* Davicom Semiconductor */
 
 /* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */
 #define	MII_OUI_xxREALTEK	0x000732	/* Realtek Semiconductor */
@@ -118,10 +117,10 @@
 /* Advanced Micro Devices PHYs */
 #define	MII_MODEL_xxAMD_79C873	0x0000
 #define	MII_STR_xxAMD_79C873	"Am79C873 10/100 PHY"
-#define	MII_MODEL_AMD_79C873phy	0x0036
-#define	MII_STR_AMD_79C873phy	"Am79C873 internal PHY"
 #define	MII_MODEL_AMD_79C875phy	0x0014
 #define	MII_STR_AMD_79C875phy	"Am79C875 quad PHY"
+#define	MII_MODEL_AMD_79C873phy	0x0036
+#define	MII_STR_AMD_79C873phy	"Am79C873 internal PHY"
 
 /* Agere PHYs */
 #define	MII_MODEL_AGERE_ET1011	0x0004
@@ -136,10 +135,10 @@
 /* Altima Communications PHYs */
 #define	MII_MODEL_xxALTIMA_AC_UNKNOWN	0x0001
 #define	MII_STR_xxALTIMA_AC_UNKNOWN	"AC_UNKNOWN 10/100 PHY"
-#define	MII_MODEL_xxALTIMA_AC101	0x0021
-#define	MII_STR_xxALTIMA_AC101	"AC101 10/100 PHY"
 #define	MII_MODEL_xxALTIMA_AC101L	0x0012
 #define	MII_STR_xxALTIMA_AC101L	"AC101L 10/100 PHY"
+#define	MII_MODEL_xxALTIMA_AC101	0x0021
+#define	MII_STR_xxALTIMA_AC101	"AC101 10/100 PHY"
 
 /* Broadcom Corp. PHYs */
 #define	MII_MODEL_xxBROADCOM_BCM5400	0x0004
@@ -160,12 +159,12 @@
 #define	MII_STR_xxBROADCOM_BCM5706	"BCM5706 10/100/1000baseT/SX PHY"
 #define	MII_MODEL_xxBROADCOM_BCM5703	0x0016
 #define	MII_STR_xxBROADCOM_BCM5703	"BCM5703 10/100/1000baseT PHY"
+#define	MII_MODEL_xxBROADCOM_BCM5750	0x0018
+#define	MII_STR_xxBROADCOM_BCM5750	"BCM5750 10/100/1000baseT PHY"
 #define	MII_MODEL_xxBROADCOM_BCM5704	0x0019
 #define	MII_STR_xxBROADCOM_BCM5704	"BCM5704 10/100/1000baseT PHY"
 #define	MII_MODEL_xxBROADCOM_BCM5705	0x001a
 #define	MII_STR_xxBROADCOM_BCM5705	"BCM5705 10/100/1000baseT PHY"
-#define	MII_MODEL_xxBROADCOM_BCM5750	0x0018
-#define	MII_STR_xxBROADCOM_BCM5750	"BCM5750 10/100/1000baseT PHY"
 #define	MII_MODEL_xxBROADCOM_BCM54K2	0x002e
 #define	MII_STR_xxBROADCOM_BCM54K2	"BCM54K2 10/100/1000baseT PHY"
 #define	MII_MODEL_xxBROADCOM_BCM5714	0x0034
@@ -208,6 +207,8 @@
 #define	MII_STR_BROADCOM2_BCM5906	"BCM5906 10/100baseTX PHY"
 
 /* Cicada Semiconductor PHYs (now owned by Vitesse) */
+#define	MII_MODEL_xxCICADA_CS8201B	0x0021
+#define	MII_STR_xxCICADA_CS8201B	"Cicada CS8201 10/100/1000TX PHY"
 #define	MII_MODEL_CICADA_CS8201	0x0001
 #define	MII_STR_CICADA_CS8201	"Cicada CS8201 10/100/1000TX PHY"
 #define	MII_MODEL_CICADA_CS8204	0x0004
@@ -218,10 +219,6 @@
 #define	MII_STR_CICADA_CS8201A	"Cicada CS8201 10/100/1000TX PHY"
 #define	MII_MODEL_CICADA_CS8201B	0x0021
 #define	MII_STR_CICADA_CS8201B	"Cicada CS8201 10/100/1000TX PHY"
-#define	MII_MODEL_xxCICADA_CS8201B	0x0021
-#define	MII_STR_xxCICADA_CS8201B	"Cicada CS8201 10/100/1000TX PHY"
-#define	MII_MODEL_VITESSE_VSC8601	0x0002
-#define	MII_STR_VITESSE_VSC8601	"VSC8601 10/100/1000 PHY"
 
 /* Davicom Semiconductor PHYs */
 #define	MII_MODEL_xxDAVICOM_DM9101	0x0000
@@ -231,6 +228,10 @@
 #define	MII_MODEL_DAVICOM_DM9601	0x000c
 #define	MII_STR_DAVICOM_DM9601	"DM9601 10/100 PHY"
 
+/* Contrived vendor/model for dcphy */
+#define	MII_MODEL_xxDEC_xxDC	0x0001
+#define	MII_STR_xxDEC_xxDC	"DC"
+
 /* Enable Semiconductor PHYs (Agere) */
 #define	MII_MODEL_ENABLESEMI_LU3X31FT	0x0001
 #define	MII_STR_ENABLESEMI_LU3X31FT	"Enable LU3X31FT"
@@ -241,48 +242,6 @@
 #define	MII_MODEL_ENABLESEMI_88E1000	0x0005
 #define	MII_STR_ENABLESEMI_88E1000	"Enable 88E1000"
 
-/* Marvell Semiconductor PHYs */
-#define	MII_MODEL_MARVELL_E1000_1	0x0000
-#define	MII_STR_MARVELL_E1000_1	"Marvell 88E1000 1 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1011	0x0002
-#define	MII_STR_MARVELL_E1011	"Marvell 88E1011 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1000_2	0x0003
-#define	MII_STR_MARVELL_E1000_2	"Marvell 88E1000 2 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1000S	0x0004
-#define	MII_STR_MARVELL_E1000S	"Marvell 88E1000S Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1000_3	0x0005
-#define	MII_STR_MARVELL_E1000_3	"Marvell 88E1000 3 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1000_4	0x0006
-#define	MII_STR_MARVELL_E1000_4	"Marvell 88E1000 4 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E3082	0x0008
-#define	MII_STR_MARVELL_E3082	"Marvell 88E3082 10/100 PHY"
-#define	MII_MODEL_MARVELL_E1112	0x0009
-#define	MII_STR_MARVELL_E1112	"Marvell 88E1112 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1149	0x000b
-#define	MII_STR_MARVELL_E1149	"Marvell 88E1149 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1111	0x000c
-#define	MII_STR_MARVELL_E1111	"Marvell 88E1111 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1116	0x0021
-#define	MII_STR_MARVELL_E1116	"Marvell 88E1116 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1118	0x0022
-#define	MII_STR_MARVELL_E1118	"Marvell 88E1118 Gigabit PHY"
-#define	MII_MODEL_MARVELL_E1116R	0x0024
-#define	MII_STR_MARVELL_E1116R	"Marvell 88E1116R Gigabit PHY"
-#define	MII_MODEL_MARVELL_E3016	0x0026
-#define	MII_STR_MARVELL_E3016	"Marvell 88E3016 10/100 PHY"
-#define	MII_MODEL_xxMARVELL_E1000_5	0x0002
-#define	MII_STR_xxMARVELL_E1000_5	"Marvell 88E1000 5 Gigabit PHY"
-#define	MII_MODEL_xxMARVELL_E1000_6	0x0003
-#define	MII_STR_xxMARVELL_E1000_6	"Marvell 88E1000 6 Gigabit PHY"
-#define	MII_MODEL_xxMARVELL_E1000_7	0x0005
-#define	MII_STR_xxMARVELL_E1000_7	"Marvell 88E1000 7 Gigabit PHY"
-#define	MII_MODEL_xxMARVELL_E1111	0x000c
-#define	MII_STR_xxMARVELL_E1111	"Marvell 88E1111 Gigabit PHY"
-
-/* Contrived vendor/model for dcphy */
-#define	MII_MODEL_xxDEC_xxDC	0x0001
-#define	MII_STR_xxDEC_xxDC	"DC"
-
 /* IC Plus Corp. PHYs */
 #define	MII_MODEL_ICPLUS_IP100	0x0004
 #define	MII_STR_ICPLUS_IP100	"IP100 10/100 PHY"
@@ -328,12 +287,12 @@
 /* Level 1 PHYs */
 #define	MII_MODEL_xxLEVEL1_LXT970	0x0000
 #define	MII_STR_xxLEVEL1_LXT970	"LXT970 10/100 PHY"
+#define	MII_MODEL_xxLEVEL1a_LXT971	0x000e
+#define	MII_STR_xxLEVEL1a_LXT971	"LXT971 10/100 PHY"
 #define	MII_MODEL_LEVEL1_LXT1000_OLD	0x0003
 #define	MII_STR_LEVEL1_LXT1000_OLD	"LXT1000 10/100/1000 PHY"
 #define	MII_MODEL_LEVEL1_LXT1000	0x000c
 #define	MII_STR_LEVEL1_LXT1000	"LXT1000 10/100/1000 PHY"
-#define	MII_MODEL_xxLEVEL1a_LXT971	0x000e
-#define	MII_STR_xxLEVEL1a_LXT971	"LXT971 10/100 PHY"
 
 /* Lucent Technologies PHYs */
 #define	MII_MODEL_LUCENT_LU6612	0x000c
@@ -343,6 +302,44 @@
 #define	MII_MODEL_LUCENT_LU3X54FT	0x0036
 #define	MII_STR_LUCENT_LU3X54FT	"LU3X54FT 10/100 PHY"
 
+/* Marvell Semiconductor PHYs */
+#define	MII_MODEL_xxMARVELL_E1000_5	0x0002
+#define	MII_STR_xxMARVELL_E1000_5	"Marvell 88E1000 5 Gigabit PHY"
+#define	MII_MODEL_xxMARVELL_E1000_6	0x0003
+#define	MII_STR_xxMARVELL_E1000_6	"Marvell 88E1000 6 Gigabit PHY"
+#define	MII_MODEL_xxMARVELL_E1000_7	0x0005
+#define	MII_STR_xxMARVELL_E1000_7	"Marvell 88E1000 7 Gigabit PHY"
+#define	MII_MODEL_xxMARVELL_E1111	0x000c
+#define	MII_STR_xxMARVELL_E1111	"Marvell 88E1111 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_1	0x0000
+#define	MII_STR_MARVELL_E1000_1	"Marvell 88E1000 1 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1011	0x0002
+#define	MII_STR_MARVELL_E1011	"Marvell 88E1011 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_2	0x0003
+#define	MII_STR_MARVELL_E1000_2	"Marvell 88E1000 2 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000S	0x0004
+#define	MII_STR_MARVELL_E1000S	"Marvell 88E1000S Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_3	0x0005
+#define	MII_STR_MARVELL_E1000_3	"Marvell 88E1000 3 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_4	0x0006
+#define	MII_STR_MARVELL_E1000_4	"Marvell 88E1000 4 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E3082	0x0008
+#define	MII_STR_MARVELL_E3082	"Marvell 88E3082 10/100 PHY"
+#define	MII_MODEL_MARVELL_E1112	0x0009
+#define	MII_STR_MARVELL_E1112	"Marvell 88E1112 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1149	0x000b
+#define	MII_STR_MARVELL_E1149	"Marvell 88E1149 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1111	0x000c
+#define	MII_STR_MARVELL_E1111	"Marvell 88E1111 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1116	0x0021
+#define	MII_STR_MARVELL_E1116	"Marvell 88E1116 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1118	0x0022
+#define	MII_STR_MARVELL_E1118	"Marvell 88E1118 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1116R	0x0024
+#define	MII_STR_MARVELL_E1116R	"Marvell 88E1116R Gigabit PHY"
+#define	MII_MODEL_MARVELL_E3016	0x0026
+#define	MII_STR_MARVELL_E3016	"Marvell 88E3016 10/100 PHY"
+
 /* Myson Technology PHYs */
 #define	MII_MODEL_MYSON_MTD972	0x0000
 #define	MII_STR_MYSON_MTD972	"MTD972 10/100 PHY"
@@ -372,10 +369,10 @@
 #define	MII_STR_QUALSEMI_QS6612	"QS6612 10/100 PHY"
 
 /* Realtek Semiconductor PHYs */
-#define	MII_MODEL_REALTEK_RTL8201L	0x0020
-#define	MII_STR_REALTEK_RTL8201L	"RTL8201L 10/100 PHY"
 #define	MII_MODEL_xxREALTEK_RTL8169S	0x0011
 #define	MII_STR_xxREALTEK_RTL8169S	"RTL8169S/8110S PHY"
+#define	MII_MODEL_REALTEK_RTL8201L	0x0020
+#define	MII_STR_REALTEK_RTL8201L	"RTL8201L 10/100 PHY"
 
 /* Seeq PHYs */
 #define	MII_MODEL_xxSEEQ_80220	0x0003
@@ -413,6 +410,10 @@
 #define	MII_MODEL_VIA_VT6103_2	0x0034
 #define	MII_STR_VIA_VT6103_2	"VT6103 10/100 PHY"
 
+/* Vitesse PHYs */
+#define	MII_MODEL_VITESSE_VSC8601	0x0002
+#define	MII_STR_VITESSE_VSC8601	"VSC8601 10/100/1000 PHY"
+
 /* XaQti Corp. PHYs */
 #define	MII_MODEL_XAQTI_XMACII	0x0000
 #define	MII_STR_XAQTI_XMACII	"XaQti Corp. XMAC II Gigabit PHY"