summaryrefslogtreecommitdiff
path: root/sys/dev/pci/drm/amd/amdgpu
diff options
context:
space:
mode:
authorMark Kettenis <kettenis@cvs.openbsd.org>2020-10-26 22:05:02 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2020-10-26 22:05:02 +0000
commita8cdbdf061bb5801d09f09a43e6e0f92e895d772 (patch)
tree56c661e9284390631287f43403534655949a768b /sys/dev/pci/drm/amd/amdgpu
parentdd18849a466442e20ef8b6b74f844028d4635058 (diff)
Make mapping the "I/O Space" BAR optional. POWER9 systems don't support
"I/O Space" on their PCIe host bridges and for most (all) Radeon variants there is an alternative method to access the relevant registers. ok jsg@
Diffstat (limited to 'sys/dev/pci/drm/amd/amdgpu')
-rw-r--r--sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c21
1 files changed, 7 insertions, 14 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
index f706d5e8409..a77a6c97ff9 100644
--- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
+++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
@@ -1609,22 +1609,15 @@ amdgpu_attach(struct device *parent, struct device *self, void *aux)
adev->fb_aper_offset = base;
}
- for (i = PCI_MAPREG_START; i < PCI_MAPREG_END ;) {
+ for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
- if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_IO) {
- if (type & PCI_MAPREG_MEM_TYPE_64BIT)
- i += 8;
- else
- i += 4;
- continue;
- }
- if (pci_mapreg_map(pa, i, type, 0,
- &adev->rio_mem_bst, &adev->rio_mem_bsh, NULL,
- &adev->rio_mem_size, 0)) {
- printf(": can't map rio space\n");
- return;
+ if (type == PCI_MAPREG_TYPE_IO) {
+ pci_mapreg_map(pa, i, type, 0, &adev->rio_mem_bst,
+ &adev->rio_mem_bsh, NULL, &adev->rio_mem_size, 0);
+ break;
}
- break;
+ if (type == PCI_MAPREG_MEM_TYPE_64BIT)
+ i += 4;
}
if (adev->family >= CHIP_BONAIRE) {