diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2019-07-04 03:25:22 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2019-07-04 03:25:22 +0000 |
| commit | f8ee7028518fb7444e11c6c68be4603c8fb48a44 (patch) | |
| tree | 977c6891c29c0028a7c68ca4b9534b52d75fa8fb /sys/dev/pci/drm/amd/amdgpu | |
| parent | 3aef28d5b0c26662575cf01356e7219599510136 (diff) | |
drm/amdgpu: add picasso support for sdma_v4
From Likun Gao
84ad2e1bd6e6fededa7ed389d0a171d0822abaac in mainline linux
Diffstat (limited to 'sys/dev/pci/drm/amd/amdgpu')
| -rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c b/sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c index 49e96a6cb3a..5dd0018c1c7 100644 --- a/sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c @@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); +MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L @@ -176,6 +177,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) ARRAY_SIZE(golden_settings_sdma_4_2)); break; case CHIP_RAVEN: + case CHIP_PICASSO: soc15_program_register_sequence(adev, golden_settings_sdma_4_1, ARRAY_SIZE(golden_settings_sdma_4_1)); @@ -224,6 +226,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) case CHIP_RAVEN: chip_name = "raven"; break; + case CHIP_PICASSO: + chip_name = "picasso"; + break; default: BUG(); } @@ -804,6 +809,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_RAVEN: + case CHIP_PICASSO: sdma_v4_1_init_power_gating(adev); sdma_v4_1_update_power_gating(adev, true); break; @@ -1211,7 +1217,7 @@ static int sdma_v4_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->asic_type == CHIP_RAVEN) + if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) adev->sdma.num_instances = 1; else adev->sdma.num_instances = 2; @@ -1554,6 +1560,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle, case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_RAVEN: + case CHIP_PICASSO: sdma_v4_0_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); sdma_v4_0_update_medium_grain_light_sleep(adev, @@ -1572,6 +1579,7 @@ static int sdma_v4_0_set_powergating_state(void *handle, switch (adev->asic_type) { case CHIP_RAVEN: + case CHIP_PICASSO: sdma_v4_1_update_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); break; |