diff options
author | Jonathan Gray <jsg@cvs.openbsd.org> | 2023-08-13 10:40:46 +0000 |
---|---|---|
committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2023-08-13 10:40:46 +0000 |
commit | a9e9e4d4b045d193d001040a931ed7e77df1b188 (patch) | |
tree | f3056ef919e74c21b846608f787f48073f68240d /sys/dev/pci/drm/i915/display | |
parent | 9cfcbf400dfb8573836b9fe6072a75e91e4b6298 (diff) |
Revert "drm/i915: Disable DC states for all commits"
From Greg Kroah-Hartman
673cdde74fd13fff0acc4c6c41f5f949434156a5 in linux-6.1.y/6.1.45
Diffstat (limited to 'sys/dev/pci/drm/i915/display')
-rw-r--r-- | sys/dev/pci/drm/i915/display/intel_display.c | 28 |
1 files changed, 3 insertions, 25 deletions
diff --git a/sys/dev/pci/drm/i915/display/intel_display.c b/sys/dev/pci/drm/i915/display/intel_display.c index 887a9a5df97..65de50781be 100644 --- a/sys/dev/pci/drm/i915/display/intel_display.c +++ b/sys/dev/pci/drm/i915/display/intel_display.c @@ -7123,8 +7123,6 @@ static void intel_update_crtc(struct intel_atomic_state *state, intel_fbc_update(state, crtc); - drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); - if (!modeset && (new_crtc_state->uapi.color_mgmt_changed || new_crtc_state->update_pipe)) @@ -7501,28 +7499,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) drm_atomic_helper_wait_for_dependencies(&state->base); drm_dp_mst_atomic_wait_for_dependencies(&state->base); - /* - * During full modesets we write a lot of registers, wait - * for PLLs, etc. Doing that while DC states are enabled - * is not a good idea. - * - * During fastsets and other updates we also need to - * disable DC states due to the following scenario: - * 1. DC5 exit and PSR exit happen - * 2. Some or all _noarm() registers are written - * 3. Due to some long delay PSR is re-entered - * 4. DC5 entry -> DMC saves the already written new - * _noarm() registers and the old not yet written - * _arm() registers - * 5. DC5 exit -> DMC restores a mixture of old and - * new register values and arms the update - * 6. PSR exit -> hardware latches a mixture of old and - * new register values -> corrupted frame, or worse - * 7. New _arm() registers are finally written - * 8. Hardware finally latches a complete set of new - * register values, and subsequent frames will be OK again - */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); + if (state->modeset) + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); intel_atomic_prepare_plane_clear_colors(state); @@ -7661,8 +7639,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * the culprit. */ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); } - intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); /* |