Update the drm headers based on libdrm 2.4.51

but make sure we still reject DRM_MODE_PAGE_FLIP_ASYNC.

ok mpi@ kettenis@

5 files changed, 43 insertions, 6 deletions

diff --git a/sys/dev/pci/drm/drm.h b/sys/dev/pci/drm/drm.h
index 32aa044577c..13d52234677 100644
--- a/sys/dev/pci/drm/drm.h
+++ b/sys/dev/pci/drm/drm.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: drm.h,v 1.13 2013/11/17 14:23:22 kettenis Exp $ */
+/* $OpenBSD: drm.h,v 1.14 2014/01/18 08:25:06 jsg Exp $ */
 /**
  * \file drm.h
  * Header for the Direct Rendering Manager
@@ -671,6 +671,7 @@ struct drm_event_vblank {
 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4
 #define DRM_CAP_PRIME 0x5
 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
+#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
 
 #define DRM_PRIME_CAP_IMPORT 0x1
 #define DRM_PRIME_CAP_EXPORT 0x2
diff --git a/sys/dev/pci/drm/drm_crtc.c b/sys/dev/pci/drm/drm_crtc.c
index 054dcb51b33..d979a509e42 100644
--- a/sys/dev/pci/drm/drm_crtc.c
+++ b/sys/dev/pci/drm/drm_crtc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: drm_crtc.c,v 1.5 2013/12/16 19:57:08 kettenis Exp $	*/
+/*	$OpenBSD: drm_crtc.c,v 1.6 2014/01/18 08:25:06 jsg Exp $	*/
 /*
  * Copyright (c) 2006-2008 Intel Corporation
  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
@@ -3634,6 +3634,10 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
 	    page_flip->reserved != 0)
 		return -EINVAL;
 
+	/* XXX always reject async until we have a newer drm version */
+	if (page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC)
+		return -EINVAL;
+
 	rw_enter_write(&dev->mode_config.rwl);
 	obj = drm_mode_object_find(dev, page_flip->crtc_id, DRM_MODE_OBJECT_CRTC);
 	if (!obj)
diff --git a/sys/dev/pci/drm/drm_mode.h b/sys/dev/pci/drm/drm_mode.h
index 53a35c0834e..9ed0c13779a 100644
--- a/sys/dev/pci/drm/drm_mode.h
+++ b/sys/dev/pci/drm/drm_mode.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: drm_mode.h,v 1.4 2013/11/17 14:23:22 kettenis Exp $	*/
+/*	$OpenBSD: drm_mode.h,v 1.5 2014/01/18 08:25:06 jsg Exp $	*/
 /*
  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
  * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
@@ -422,7 +422,8 @@ struct drm_mode_crtc_lut {
 };
 
 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
-#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
+#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
+#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
 
 /*
  * Request a page flip on the specified crtc.
diff --git a/sys/dev/pci/drm/i915_drm.h b/sys/dev/pci/drm/i915_drm.h
index 6414141be62..279d70c83a6 100644
--- a/sys/dev/pci/drm/i915_drm.h
+++ b/sys/dev/pci/drm/i915_drm.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drm.h,v 1.19 2013/06/15 11:27:59 jsg Exp $ */
+/* $OpenBSD: i915_drm.h,v 1.20 2014/01/18 08:25:06 jsg Exp $ */
 /*
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
@@ -190,6 +190,7 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_SET_CACHING	0x2f
 #define DRM_I915_GEM_GET_CACHING	0x30
 #define DRM_I915_REG_READ		0x31
+#define DRM_I915_GET_RESET_STATS	0x32
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -239,6 +240,7 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
+#define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -900,4 +902,21 @@ struct drm_i915_reg_read {
 	uint64_t offset;
 	uint64_t val; /* Return value */
 };
+
+struct drm_i915_reset_stats {
+	uint32_t ctx_id;
+	uint32_t flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	uint32_t reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	uint32_t batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	uint32_t batch_pending;
+
+	uint32_t pad;
+};
+
 #endif				/* _I915_DRM_H_ */
diff --git a/sys/dev/pci/drm/radeon_drm.h b/sys/dev/pci/drm/radeon_drm.h
index 5555e1e4f23..535b7a22f1d 100644
--- a/sys/dev/pci/drm/radeon_drm.h
+++ b/sys/dev/pci/drm/radeon_drm.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: radeon_drm.h,v 1.9 2013/11/17 14:23:22 kettenis Exp $ */
+/* $OpenBSD: radeon_drm.h,v 1.10 2014/01/18 08:25:06 jsg Exp $ */
 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
  *
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
@@ -809,6 +809,7 @@ struct drm_radeon_gem_create {
 #define RADEON_TILING_MACRO				0x1
 #define RADEON_TILING_MICRO				0x2
 #define RADEON_TILING_SWAP_16BIT			0x4
+#define RADEON_TILING_R600_NO_SCANOUT                   RADEON_TILING_SWAP_16BIT
 #define RADEON_TILING_SWAP_32BIT			0x8
 /* this object requires a surface when mapped - i.e. front buffer */
 #define RADEON_TILING_SURFACE				0x10
@@ -982,6 +983,10 @@ struct drm_radeon_cs {
 #define RADEON_INFO_RING_WORKING	0x15
 /* SI tile mode array */
 #define RADEON_INFO_SI_TILE_MODE_ARRAY	0x16
+/* query if CP DMA is supported on the compute ring */
+#define RADEON_INFO_SI_CP_DMA_COMPUTE	0x17
+/* CIK macrotile mode array */
+#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY	0x18
 
 
 struct drm_radeon_info {
@@ -1008,6 +1013,13 @@ struct drm_radeon_info {
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2
 
+#define CIK_TILE_MODE_COLOR_2D			14
+#define CIK_TILE_MODE_COLOR_2D_SCANOUT		10
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64       0
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128      1
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256      2
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512      3
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4
 #define CIK_TILE_MODE_DEPTH_STENCIL_1D		5
 
 #endif