diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2019-09-16 15:29:49 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2019-09-16 15:29:49 +0000 |
| commit | 34a80e263d9150ccae49f4a98631c8aede2c1821 (patch) | |
| tree | 3fcddd43c3a31f883b19803a62a9c8c18eb889b3 /sys/dev/pci/drm | |
| parent | 6722bcdb5c7e107ab5ae05fa7e1088de3a40136e (diff) | |
drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
From Ville Syrjala
057cdb6f0f47c643905df5557fdf9d56f46d2931 in linux 4.19.y/4.19.73
a8f196a0fa6391a436f63f360a1fb57031fdf26c in mainline linux
Diffstat (limited to 'sys/dev/pci/drm')
| -rw-r--r-- | sys/dev/pci/drm/i915/intel_cdclk.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sys/dev/pci/drm/i915/intel_cdclk.c b/sys/dev/pci/drm/i915/intel_cdclk.c index 29075c76342..7b4906ede14 100644 --- a/sys/dev/pci/drm/i915/intel_cdclk.c +++ b/sys/dev/pci/drm/i915/intel_cdclk.c @@ -2209,6 +2209,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max(2 * 96000, min_cdclk); /* + * "For DP audio configuration, cdclk frequency shall be set to + * meet the following requirements: + * DP Link Frequency(MHz) | Cdclk frequency(MHz) + * 270 | 320 or higher + * 162 | 200 or higher" + */ + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) + min_cdclk = max(crtc_state->port_clock, min_cdclk); + + /* * On Valleyview some DSI panels lose (v|h)sync when the clock is lower * than 320000KHz. */ |