sync i915_tiling_ok with 3.8.2

2 files changed, 31 insertions, 22 deletions

diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index c10f5e59c81..251676a3e4b 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -1170,7 +1170,7 @@ void	i915_gem_detect_bit_6_swizzle(struct inteldrm_softc *,
 void	i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *);
 void	i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *);
 int	i915_gem_swizzle_page(struct vm_page *page);
-int	i915_tiling_ok(struct drm_device *, int, int, int);
+bool	i915_tiling_ok(struct drm_device *, int, int, int);
 bool	i915_gem_object_fence_ok(struct drm_i915_gem_object *, int);
 
 /* i915_gem_debug.c */
diff --git a/sys/dev/pci/drm/i915_gem_tiling.c b/sys/dev/pci/drm/i915_gem_tiling.c
index 7360e28c890..74dac451937 100644
--- a/sys/dev/pci/drm/i915_gem_tiling.c
+++ b/sys/dev/pci/drm/i915_gem_tiling.c
@@ -232,47 +232,56 @@ i915_gem_detect_bit_6_swizzle(struct inteldrm_softc *dev_priv,
 	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }
 
-int
+/* Check pitch constriants for all chips & tiling formats */
+bool
 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 {
-	int			 tile_width;
+	int tile_width;
 
-	/* Linear is always ok */
+	/* Linear is always fine */
 	if (tiling_mode == I915_TILING_NONE)
-		return (1);
+		return true;
 
-	if (!IS_I9XX(dev) || (tiling_mode == I915_TILING_Y &&
-	    HAS_128_BYTE_Y_TILING(dev)))
+	if (IS_GEN2(dev) ||
+	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
 		tile_width = 128;
 	else
 		tile_width = 512;
 
-	/* Check stride and size constraints */
+	/* check maximum stride & object size */
 	if (INTEL_INFO(dev)->gen >= 4) {
-		/* fence reg has end address, so size is ok */
+		/* i965 stores the end address of the gtt mapping in the fence
+		 * reg, so dont bother to check the size */
 		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
-			return (0);
-	} else if (IS_GEN3(dev) || IS_GEN2(dev)) {
+			return false;
+	} else {
 		if (stride > 8192)
-			return (0);
+			return false;
+
 		if (IS_GEN3(dev)) {
 			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
-				return (0);
-		} else if (size > I830_FENCE_MAX_SIZE_VAL << 19)
-			return (0);
+				return false;
+		} else {
+			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
+				return false;
+		}
 	}
 
-	/* 965+ just needs multiples of the tile width */
-	if (INTEL_INFO(dev)->gen >= 4)
-		return ((stride & (tile_width - 1)) == 0);
+	/* 965+ just needs multiples of tile width */
+	if (INTEL_INFO(dev)->gen >= 4) {
+		if (stride & (tile_width - 1))
+			return false;
+		return true;
+	}
 
-	/* Pre-965 needs power-of-two */
+	/* Pre-965 needs power of two tile widths */
 	if (stride < tile_width)
-		return (0);
+		return false;
 
 	if (stride & (stride - 1))
-		return (0);
-	return (1);
+		return false;
+
+	return true;
 }
 
 bool