diff options
| author | Jonathan Gray <jsg@jsg.id.au> | 2013-07-05 22:36:00 +1000 |
|---|---|---|
| committer | Jonathan Gray <jsg@jsg.id.au> | 2013-08-12 10:44:39 +1000 |
| commit | b7a5267f86d80cc4a54d0640f54498ee807fb424 (patch) | |
| tree | 66f4e980365abe43d3968b792be98f17297e4b2b /sys/dev/pci/drm | |
| parent | 7e65693b0dbd3044f2ecf37b2cf68d4dcc70f816 (diff) | |
use inline udelay/mdelay funcs instead of macros & reduce the diff to linux
Diffstat (limited to 'sys/dev/pci/drm')
23 files changed, 168 insertions, 168 deletions
diff --git a/sys/dev/pci/drm/radeon/atom.c b/sys/dev/pci/drm/radeon/atom.c index caddef7eb88..290d47c8c7f 100644 --- a/sys/dev/pci/drm/radeon/atom.c +++ b/sys/dev/pci/drm/radeon/atom.c @@ -665,9 +665,9 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) unsigned count = U8((*ptr)++); SDEBUG(" count: %d\n", count); if (arg == ATOM_UNIT_MICROSEC) - DRM_UDELAY(count); + udelay(count); else if (!drm_can_sleep()) - DRM_MDELAY(count); + mdelay(count); else drm_msleep(count, "atomop"); } diff --git a/sys/dev/pci/drm/radeon/atombios_dp.c b/sys/dev/pci/drm/radeon/atombios_dp.c index 2ddd129cac2..f86d736b6e0 100644 --- a/sys/dev/pci/drm/radeon/atombios_dp.c +++ b/sys/dev/pci/drm/radeon/atombios_dp.c @@ -138,7 +138,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) return send_bytes; else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) - DRM_UDELAY(400); + udelay(400); else return -EIO; } @@ -171,7 +171,7 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) return ret; else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) - DRM_UDELAY(400); + udelay(400); else return -EIO; } @@ -258,7 +258,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_controller *adapter, int mode, return -EIO; case AUX_NATIVE_REPLY_DEFER: DRM_DEBUG_KMS("aux_ch native defer\n"); - DRM_UDELAY(400); + udelay(400); continue; default: DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); @@ -275,7 +275,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_controller *adapter, int mode, return -EIO; case AUX_I2C_REPLY_DEFER: DRM_DEBUG_KMS("aux_i2c defer\n"); - DRM_UDELAY(400); + udelay(400); break; default: DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); @@ -682,7 +682,7 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) { - DRM_UDELAY(400); + udelay(400); /* disable the training pattern on the sink */ radeon_write_dpcd_reg(dp_info->radeon_connector, @@ -710,7 +710,7 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) memset(dp_info->train_set, 0, 4); radeon_dp_update_vs_emph(dp_info); - DRM_UDELAY(400); + udelay(400); /* clock recovery loop */ clock_recovery = false; diff --git a/sys/dev/pci/drm/radeon/atombios_encoders.c b/sys/dev/pci/drm/radeon/atombios_encoders.c index 186bc9f3ce9..18ba1b04bcd 100644 --- a/sys/dev/pci/drm/radeon/atombios_encoders.c +++ b/sys/dev/pci/drm/radeon/atombios_encoders.c @@ -1348,7 +1348,7 @@ atombios_set_edp_panel_power(struct drm_connector *connector, int action) for (i = 0; i < 300; i++) { if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) return true; - DRM_MDELAY(1); + mdelay(1); } return false; } diff --git a/sys/dev/pci/drm/radeon/evergreen.c b/sys/dev/pci/drm/radeon/evergreen.c index facd11661cb..7e8927dff85 100644 --- a/sys/dev/pci/drm/radeon/evergreen.c +++ b/sys/dev/pci/drm/radeon/evergreen.c @@ -236,7 +236,7 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) break; - DRM_UDELAY(1); + udelay(1); } DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); @@ -1201,7 +1201,7 @@ int evergreen_mc_wait_for_idle(struct radeon_device *rdev) tmp = RREG32(SRBM_STATUS) & 0x1F00; if (!tmp) return 0; - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -1228,7 +1228,7 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) if (tmp) { return; } - DRM_UDELAY(1); + udelay(1); } } @@ -1388,7 +1388,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav for (j = 0; j < rdev->usec_timeout; j++) { if (radeon_get_vblank_counter(rdev, i) != frame_count) break; - DRM_UDELAY(1); + udelay(1); } /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ @@ -1415,7 +1415,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); } /* wait for the MC to settle */ - DRM_UDELAY(100); + udelay(100); /* lock double buffered regs */ for (i = 0; i < rdev->num_crtc; i++) { @@ -1475,7 +1475,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) break; - DRM_UDELAY(1); + udelay(1); } } } @@ -1507,13 +1507,13 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s for (j = 0; j < rdev->usec_timeout; j++) { if (radeon_get_vblank_counter(rdev, i) != frame_count) break; - DRM_UDELAY(1); + udelay(1); } } } /* Unlock vga access */ WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); - DRM_MDELAY(1); + mdelay(1); WREG32(VGA_RENDER_CONTROL, save->vga_render_control); } @@ -1745,7 +1745,7 @@ static int evergreen_cp_resume(struct radeon_device *rdev) SOFT_RESET_SPI | SOFT_RESET_SX)); RREG32(GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(GRBM_SOFT_RESET, 0); RREG32(GRBM_SOFT_RESET); @@ -1781,7 +1781,7 @@ static int evergreen_cp_resume(struct radeon_device *rdev) WREG32(SCRATCH_UMSK, 0); } - DRM_MDELAY(1); + mdelay(1); WREG32(CP_RB_CNTL, tmp); WREG32(CP_RB_BASE, ring->gpu_addr >> 8); @@ -2354,7 +2354,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); - DRM_UDELAY(50); + udelay(50); } @@ -2480,7 +2480,7 @@ static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev) dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); WREG32(GRBM_SOFT_RESET, grbm_reset); (void)RREG32(GRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(GRBM_SOFT_RESET, 0); (void)RREG32(GRBM_SOFT_RESET); @@ -2520,7 +2520,7 @@ static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev) /* Reset dma */ WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); RREG32(SRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(SRBM_SOFT_RESET, 0); dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", @@ -2554,7 +2554,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) evergreen_gpu_soft_reset_dma(rdev); /* Wait a little for things to settle down */ - DRM_UDELAY(50); + udelay(50); evergreen_mc_resume(rdev, &save); return 0; @@ -2978,7 +2978,7 @@ static void evergreen_irq_disable(struct radeon_device *rdev) { r600_disable_interrupts(rdev); /* Wait and acknowledge irq */ - DRM_MDELAY(1); + mdelay(1); evergreen_irq_ack(rdev); evergreen_disable_interrupt_state(rdev); } diff --git a/sys/dev/pci/drm/radeon/evergreen_cs.c b/sys/dev/pci/drm/radeon/evergreen_cs.c index 1457fb1cdac..b95ecd362fe 100644 --- a/sys/dev/pci/drm/radeon/evergreen_cs.c +++ b/sys/dev/pci/drm/radeon/evergreen_cs.c @@ -2854,7 +2854,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) #if 0 for (r = 0; r < p->ib.length_dw; r++) { printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); - DRM_MDELAY(1); + mdelay(1); } #endif free(p->track, M_DRM); @@ -3305,7 +3305,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) #if 0 for (r = 0; r < p->ib->length_dw; r++) { printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); - DRM_MDELAY(1); + mdelay(1); } #endif return 0; diff --git a/sys/dev/pci/drm/radeon/ni.c b/sys/dev/pci/drm/radeon/ni.c index 4d31acf1023..6517606e9d2 100644 --- a/sys/dev/pci/drm/radeon/ni.c +++ b/sys/dev/pci/drm/radeon/ni.c @@ -269,7 +269,7 @@ int ni_mc_load_microcode(struct radeon_device *rdev) for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) break; - DRM_UDELAY(1); + udelay(1); } if (running) @@ -733,7 +733,7 @@ static void cayman_gpu_init(struct radeon_device *rdev) WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); - DRM_UDELAY(50); + udelay(50); } /* @@ -1080,7 +1080,7 @@ static int cayman_cp_resume(struct radeon_device *rdev) SOFT_RESET_SPI | SOFT_RESET_SX)); RREG32(GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(GRBM_SOFT_RESET, 0); RREG32(GRBM_SOFT_RESET); @@ -1130,7 +1130,7 @@ static int cayman_cp_resume(struct radeon_device *rdev) WREG32(ring->rptr_reg, ring->rptr); WREG32(ring->wptr_reg, ring->wptr); - DRM_MDELAY(1); + mdelay(1); WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); } @@ -1244,7 +1244,7 @@ int cayman_dma_resume(struct radeon_device *rdev) /* Reset dma */ WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); RREG32(SRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(SRBM_SOFT_RESET, 0); for (i = 0; i < 2; i++) { @@ -1375,7 +1375,7 @@ static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev) dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); WREG32(GRBM_SOFT_RESET, grbm_reset); (void)RREG32(GRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(GRBM_SOFT_RESET, 0); (void)RREG32(GRBM_SOFT_RESET); @@ -1421,7 +1421,7 @@ static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev) /* Reset dma */ WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); RREG32(SRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(SRBM_SOFT_RESET, 0); dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", @@ -1465,7 +1465,7 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) cayman_gpu_soft_reset_dma(rdev); /* Wait a little for things to settle down */ - DRM_UDELAY(50); + udelay(50); evergreen_mc_resume(rdev, &save); return 0; diff --git a/sys/dev/pci/drm/radeon/r100.c b/sys/dev/pci/drm/radeon/r100.c index 5c8975cd6f8..eb692ac9296 100644 --- a/sys/dev/pci/drm/radeon/r100.c +++ b/sys/dev/pci/drm/radeon/r100.c @@ -195,7 +195,7 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) break; - DRM_UDELAY(1); + udelay(1); } DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); @@ -370,7 +370,7 @@ void r100_pm_misc(struct radeon_device *rdev) tmp &= ~(voltage->gpio.mask); WREG32(voltage->gpio.reg, tmp); if (voltage->delay) - DRM_UDELAY(voltage->delay); + udelay(voltage->delay); } else { tmp = RREG32(voltage->gpio.reg); if (voltage->active_high) @@ -379,7 +379,7 @@ void r100_pm_misc(struct radeon_device *rdev) tmp |= voltage->gpio.mask; WREG32(voltage->gpio.reg, tmp); if (voltage->delay) - DRM_UDELAY(voltage->delay); + udelay(voltage->delay); } } @@ -748,7 +748,7 @@ void r100_irq_disable(struct radeon_device *rdev) WREG32(R_000040_GEN_INT_CNTL, 0); /* Wait and acknowledge irq */ - DRM_MDELAY(1); + mdelay(1); tmp = RREG32(R_000044_GEN_INT_STATUS); WREG32(R_000044_GEN_INT_STATUS, tmp); } @@ -960,7 +960,7 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev) if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -1163,7 +1163,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) } WREG32(RADEON_CP_RB_CNTL, tmp); - DRM_UDELAY(10); + udelay(10); ring->rptr = RREG32(RADEON_CP_RB_RPTR); /* Set cp mode to bus mastering & enable cp*/ WREG32(RADEON_CP_CSQ_MODE, @@ -2560,7 +2560,7 @@ static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) if (tmp >= n) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -2579,7 +2579,7 @@ int r100_gui_wait_for_idle(struct radeon_device *rdev) if (!(tmp & RADEON_RBBM_ACTIVE)) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -2595,7 +2595,7 @@ int r100_mc_wait_for_idle(struct radeon_device *rdev) if (tmp & RADEON_MC_IDLE) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -2630,16 +2630,16 @@ void r100_bm_disable(struct radeon_device *rdev) /* disable bus mastering */ tmp = RREG32(R_000030_BUS_CNTL); WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); - DRM_MDELAY(1); + mdelay(1); WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); - DRM_MDELAY(1); + mdelay(1); WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); tmp = RREG32(RADEON_BUS_CNTL); - DRM_MDELAY(1); + mdelay(1); #ifdef notyet pci_clear_master(rdev->pdev); #endif - DRM_MDELAY(1); + mdelay(1); } int r100_asic_reset(struct radeon_device *rdev) @@ -2673,17 +2673,17 @@ int r100_asic_reset(struct radeon_device *rdev) S_0000F0_SOFT_RESET_PP(1) | S_0000F0_SOFT_RESET_RB(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* reset CP */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* restore PCI & busmastering */ @@ -2952,7 +2952,7 @@ static void r100_pll_errata_after_data(struct radeon_device *rdev) * or the chip could hang on a subsequent access */ if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { - DRM_MDELAY(5); + mdelay(5); } /* This function is required to workaround a hardware bug in some (all?) @@ -3743,7 +3743,7 @@ int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) if (tmp == 0xDEADBEEF) { break; } - DRM_UDELAY(1); + udelay(1); } if (i < rdev->usec_timeout) { DRM_INFO("ring test succeeded in %d usecs\n", i); @@ -3814,7 +3814,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) if (tmp == 0xDEADBEEF) { break; } - DRM_UDELAY(1); + udelay(1); } if (i < rdev->usec_timeout) { DRM_INFO("ib test succeeded in %u usecs\n", i); diff --git a/sys/dev/pci/drm/radeon/r300.c b/sys/dev/pci/drm/radeon/r300.c index 669d980ce0f..97619ca2a08 100644 --- a/sys/dev/pci/drm/radeon/r300.c +++ b/sys/dev/pci/drm/radeon/r300.c @@ -316,7 +316,7 @@ int r300_mc_wait_for_idle(struct radeon_device *rdev) if (tmp & R300_MC_IDLE) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -406,9 +406,9 @@ int r300_asic_reset(struct radeon_device *rdev) WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | S_0000F0_SOFT_RESET_GA(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* resetting the CP seems to be problematic sometimes it end up @@ -418,9 +418,9 @@ int r300_asic_reset(struct radeon_device *rdev) */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* restore PCI & busmastering */ diff --git a/sys/dev/pci/drm/radeon/r520.c b/sys/dev/pci/drm/radeon/r520.c index c6ab0b33faa..0b41a5f23fc 100644 --- a/sys/dev/pci/drm/radeon/r520.c +++ b/sys/dev/pci/drm/radeon/r520.c @@ -44,7 +44,7 @@ int r520_mc_wait_for_idle(struct radeon_device *rdev) if (tmp & R520_MC_STATUS_IDLE) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } diff --git a/sys/dev/pci/drm/radeon/r600.c b/sys/dev/pci/drm/radeon/r600.c index 015f8f5d548..d38fb15bb6c 100644 --- a/sys/dev/pci/drm/radeon/r600.c +++ b/sys/dev/pci/drm/radeon/r600.c @@ -860,7 +860,7 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) if (tmp) { return; } - DRM_UDELAY(1); + udelay(1); } } @@ -1021,7 +1021,7 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev) tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; if (!tmp) return 0; - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -1318,7 +1318,7 @@ static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); WREG32(R_008020_GRBM_SOFT_RESET, tmp); RREG32(R_008020_GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(R_008020_GRBM_SOFT_RESET, 0); } /* Reset CP (we always reset CP) */ @@ -1326,7 +1326,7 @@ static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); WREG32(R_008020_GRBM_SOFT_RESET, tmp); RREG32(R_008020_GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(R_008020_GRBM_SOFT_RESET, 0); dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", @@ -1367,7 +1367,7 @@ static void r600_gpu_soft_reset_dma(struct radeon_device *rdev) else WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); RREG32(SRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(SRBM_SOFT_RESET, 0); dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", @@ -1401,7 +1401,7 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) r600_gpu_soft_reset_dma(rdev); /* Wait a little for things to settle down */ - DRM_MDELAY(1); + mdelay(1); rv515_mc_resume(rdev, &save); return 0; @@ -2147,7 +2147,7 @@ static int r600_cp_load_microcode(struct radeon_device *rdev) /* Reset cp */ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); RREG32(GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(GRBM_SOFT_RESET, 0); WREG32(CP_ME_RAM_WADDR, 0); @@ -2210,7 +2210,7 @@ int r600_cp_resume(struct radeon_device *rdev) /* Reset cp */ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); RREG32(GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(GRBM_SOFT_RESET, 0); /* Set ring buffer size */ @@ -2244,7 +2244,7 @@ int r600_cp_resume(struct radeon_device *rdev) WREG32(SCRATCH_UMSK, 0); } - DRM_MDELAY(1); + mdelay(1); WREG32(CP_RB_CNTL, tmp); WREG32(CP_RB_BASE, ring->gpu_addr >> 8); @@ -2341,7 +2341,7 @@ int r600_dma_resume(struct radeon_device *rdev) else WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); RREG32(SRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(SRBM_SOFT_RESET, 0); WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); @@ -2459,7 +2459,7 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) break; - DRM_UDELAY(1); + udelay(1); } if (i < rdev->usec_timeout) { DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); @@ -2513,7 +2513,7 @@ int r600_dma_ring_test(struct radeon_device *rdev, tmp = *ptr; if (tmp == 0xDEADBEEF) break; - DRM_UDELAY(1); + udelay(1); } if (i < rdev->usec_timeout) { @@ -3087,7 +3087,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) break; - DRM_UDELAY(1); + udelay(1); } if (i < rdev->usec_timeout) { DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); @@ -3155,7 +3155,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) tmp = *ptr; if (tmp == 0xDEADBEEF) break; - DRM_UDELAY(1); + udelay(1); } if (i < rdev->usec_timeout) { DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); @@ -3284,7 +3284,7 @@ void r600_rlc_stop(struct radeon_device *rdev) /* r7xx asics need to soft reset RLC before halting */ WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); RREG32(SRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(SRBM_SOFT_RESET, 0); RREG32(SRBM_SOFT_RESET); } @@ -3780,7 +3780,7 @@ void r600_irq_disable(struct radeon_device *rdev) { r600_disable_interrupts(rdev); /* Wait and acknowledge irq */ - DRM_MDELAY(1); + mdelay(1); r600_irq_ack(rdev); r600_disable_interrupt_state(rdev); } diff --git a/sys/dev/pci/drm/radeon/r600_cs.c b/sys/dev/pci/drm/radeon/r600_cs.c index 31cfc7637f6..65445be5014 100644 --- a/sys/dev/pci/drm/radeon/r600_cs.c +++ b/sys/dev/pci/drm/radeon/r600_cs.c @@ -2447,7 +2447,7 @@ int r600_cs_parse(struct radeon_cs_parser *p) #if 0 for (r = 0; r < p->ib.length_dw; r++) { printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); - DRM_MDELAY(1); + mdelay(1); } #endif free(p->track, M_DRM); @@ -2757,7 +2757,7 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) #if 0 for (r = 0; r < p->ib->length_dw; r++) { printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); - DRM_MDELAY(1); + mdelay(1); } #endif return 0; diff --git a/sys/dev/pci/drm/radeon/radeon_clocks.c b/sys/dev/pci/drm/radeon/radeon_clocks.c index d8524a35bee..b36c08eb56e 100644 --- a/sys/dev/pci/drm/radeon/radeon_clocks.c +++ b/sys/dev/pci/drm/radeon/radeon_clocks.c @@ -404,19 +404,19 @@ void radeon_legacy_set_engine_clock(struct radeon_device *rdev, tmp &= ~RADEON_SCLK_SRC_SEL_MASK; WREG32_PLL(RADEON_SCLK_CNTL, tmp); - DRM_UDELAY(10); + udelay(10); tmp = RREG32_PLL(RADEON_SPLL_CNTL); tmp |= RADEON_SPLL_SLEEP; WREG32_PLL(RADEON_SPLL_CNTL, tmp); - DRM_UDELAY(2); + udelay(2); tmp = RREG32_PLL(RADEON_SPLL_CNTL); tmp |= RADEON_SPLL_RESET; WREG32_PLL(RADEON_SPLL_CNTL, tmp); - DRM_UDELAY(200); + udelay(200); tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); @@ -436,13 +436,13 @@ void radeon_legacy_set_engine_clock(struct radeon_device *rdev, tmp &= ~RADEON_SPLL_SLEEP; WREG32_PLL(RADEON_SPLL_CNTL, tmp); - DRM_UDELAY(2); + udelay(2); tmp = RREG32_PLL(RADEON_SPLL_CNTL); tmp &= ~RADEON_SPLL_RESET; WREG32_PLL(RADEON_SPLL_CNTL, tmp); - DRM_UDELAY(200); + udelay(200); tmp = RREG32_PLL(RADEON_SCLK_CNTL); tmp &= ~RADEON_SCLK_SRC_SEL_MASK; @@ -463,13 +463,13 @@ void radeon_legacy_set_engine_clock(struct radeon_device *rdev, } WREG32_PLL(RADEON_SCLK_CNTL, tmp); - DRM_UDELAY(20); + udelay(20); tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); tmp |= RADEON_DONT_USE_XTALIN; WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); - DRM_UDELAY(10); + udelay(10); } void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) @@ -637,7 +637,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) tmp &= ~(R300_SCLK_FORCE_VAP); tmp |= RADEON_SCLK_FORCE_CP; WREG32_PLL(RADEON_SCLK_CNTL, tmp); - DRM_MDELAY(15); + mdelay(15); tmp = RREG32_PLL(R300_SCLK_CNTL2); tmp &= ~(R300_SCLK_FORCE_TCL | @@ -655,12 +655,12 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) tmp |= (RADEON_ENGIN_DYNCLK_MODE | (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); - DRM_MDELAY(15); + mdelay(15); tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); tmp |= RADEON_SCLK_DYN_START_CNTL; WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); - DRM_MDELAY(15); + mdelay(15); /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 to lockup randomly, leave them as set by BIOS. @@ -700,7 +700,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) tmp |= RADEON_SCLK_MORE_FORCEON; } WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); - DRM_MDELAY(15); + mdelay(15); } /* RV200::A11 A12, RV250::A11 A12 */ @@ -713,7 +713,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) tmp |= RADEON_TCL_BYPASS_DISABLE; WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); } - DRM_MDELAY(15); + mdelay(15); /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); @@ -726,14 +726,14 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) RADEON_PIXCLK_TMDS_ALWAYS_ONb); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); - DRM_MDELAY(15); + mdelay(15); tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); tmp |= (RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); - DRM_MDELAY(15); + mdelay(15); } } else { /* Turn everything OFF (ForceON to everything) */ @@ -865,7 +865,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) } WREG32_PLL(RADEON_SCLK_CNTL, tmp); - DRM_MDELAY(16); + mdelay(16); if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { @@ -874,7 +874,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); WREG32_PLL(R300_SCLK_CNTL2, tmp); - DRM_MDELAY(16); + mdelay(16); } if (rdev->flags & RADEON_IS_IGP) { @@ -882,7 +882,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) tmp &= ~(RADEON_FORCEON_MCLKA | RADEON_FORCEON_YCLKA); WREG32_PLL(RADEON_MCLK_CNTL, tmp); - DRM_MDELAY(16); + mdelay(16); } if ((rdev->family == CHIP_RV200) || @@ -891,7 +891,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); tmp |= RADEON_SCLK_MORE_FORCEON; WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); - DRM_MDELAY(16); + mdelay(16); } tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); @@ -904,7 +904,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) RADEON_PIXCLK_TMDS_ALWAYS_ONb); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); - DRM_MDELAY(16); + mdelay(16); tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | diff --git a/sys/dev/pci/drm/radeon/radeon_combios.c b/sys/dev/pci/drm/radeon/radeon_combios.c index e87d00bcb03..c22d1bc20e2 100644 --- a/sys/dev/pci/drm/radeon/radeon_combios.c +++ b/sys/dev/pci/drm/radeon/radeon_combios.c @@ -2996,12 +2996,12 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) case 3: val = RBIOS16(index); index += 2; - DRM_UDELAY(val); + udelay(val); break; case 4: val = RBIOS16(index); index += 2; - DRM_MDELAY(val); + mdelay(val); break; case 6: slave_addr = id & 0xff; @@ -3050,7 +3050,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) case 4: val = RBIOS16(index); index += 2; - DRM_UDELAY(val); + udelay(val); break; case 5: reg = id & 0x1fff; @@ -3128,7 +3128,7 @@ static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) case 4: val = RBIOS16(offset); offset += 2; - DRM_UDELAY(val); + udelay(val); break; case 5: val = RBIOS16(offset); @@ -3197,10 +3197,10 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) tmp = 1000; switch (addr) { case 1: - DRM_UDELAY(150); + udelay(150); break; case 2: - DRM_MDELAY(1); + mdelay(1); break; case 3: while (tmp--) { @@ -3231,13 +3231,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) /*mclk_cntl |= 0x00001111;*//* ??? */ WREG32_PLL(RADEON_MCLK_CNTL, mclk_cntl); - DRM_MDELAY(10); + mdelay(10); #endif WREG32_PLL (RADEON_CLK_PWRMGT_CNTL, tmp & ~RADEON_CG_NO1_DEBUG_0); - DRM_MDELAY(10); + mdelay(10); } break; default: diff --git a/sys/dev/pci/drm/radeon/radeon_i2c.c b/sys/dev/pci/drm/radeon/radeon_i2c.c index 06cc158c01f..4e9237a0bd2 100644 --- a/sys/dev/pci/drm/radeon/radeon_i2c.c +++ b/sys/dev/pci/drm/radeon/radeon_i2c.c @@ -572,7 +572,7 @@ static int r100_hw_i2c_xfer(struct i2c_controller *i2c_adap, (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); WREG32(i2c_cntl_0, reg); for (k = 0; k < 32; k++) { - DRM_UDELAY(10); + udelay(10); tmp = RREG32(i2c_cntl_0); if (tmp & RADEON_I2C_GO) continue; @@ -604,7 +604,7 @@ static int r100_hw_i2c_xfer(struct i2c_controller *i2c_adap, (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); for (k = 0; k < 32; k++) { - DRM_UDELAY(10); + udelay(10); tmp = RREG32(i2c_cntl_0); if (tmp & RADEON_I2C_GO) continue; @@ -632,7 +632,7 @@ static int r100_hw_i2c_xfer(struct i2c_controller *i2c_adap, (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); WREG32(i2c_cntl_0, reg); for (k = 0; k < 32; k++) { - DRM_UDELAY(10); + udelay(10); tmp = RREG32(i2c_cntl_0); if (tmp & RADEON_I2C_GO) continue; @@ -733,7 +733,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); for (i = 0; i < 50; i++) { - DRM_UDELAY(1); + udelay(1); if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) break; } @@ -767,7 +767,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, AVIVO_DC_I2C_NACK | AVIVO_DC_I2C_HALT)); WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); - DRM_UDELAY(1); + udelay(1); WREG32(AVIVO_DC_I2C_RESET, 0); WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); @@ -780,7 +780,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, WREG32(AVIVO_DC_I2C_CONTROL1, reg); WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); for (j = 0; j < 200; j++) { - DRM_UDELAY(50); + udelay(50); tmp = RREG32(AVIVO_DC_I2C_STATUS1); if (tmp & AVIVO_DC_I2C_GO) continue; @@ -811,7 +811,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, AVIVO_DC_I2C_NACK | AVIVO_DC_I2C_HALT)); WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); - DRM_UDELAY(1); + udelay(1); WREG32(AVIVO_DC_I2C_RESET, 0); WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); @@ -822,7 +822,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); for (j = 0; j < 200; j++) { - DRM_UDELAY(50); + udelay(50); tmp = RREG32(AVIVO_DC_I2C_STATUS1); if (tmp & AVIVO_DC_I2C_GO) continue; @@ -851,7 +851,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, AVIVO_DC_I2C_NACK | AVIVO_DC_I2C_HALT)); WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); - DRM_UDELAY(1); + udelay(1); WREG32(AVIVO_DC_I2C_RESET, 0); WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); @@ -865,7 +865,7 @@ static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, WREG32(AVIVO_DC_I2C_CONTROL1, reg); WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); for (j = 0; j < 200; j++) { - DRM_UDELAY(50); + udelay(50); tmp = RREG32(AVIVO_DC_I2C_STATUS1); if (tmp & AVIVO_DC_I2C_GO) continue; @@ -890,7 +890,7 @@ done: AVIVO_DC_I2C_NACK | AVIVO_DC_I2C_HALT)); WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); - DRM_UDELAY(1); + udelay(1); WREG32(AVIVO_DC_I2C_RESET, 0); WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); diff --git a/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c b/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c index e429d9ca626..aadd0930304 100644 --- a/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c +++ b/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c @@ -879,7 +879,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) (unsigned)((pll_fb_post_div & RADEON_P2PLL_POST0_DIV_MASK) >> 16)); - DRM_MDELAY(50); /* Let the clock to lock */ + mdelay(50); /* Let the clock to lock */ WREG32_PLL_P(RADEON_PIXCLKS_CNTL, RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, @@ -984,7 +984,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); - DRM_MDELAY(50); /* Let the clock to lock */ + mdelay(50); /* Let the clock to lock */ WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, RADEON_VCLK_SRC_SEL_PPLLCLK, diff --git a/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c b/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c index 13d25af467a..8ebd8cce247 100644 --- a/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c +++ b/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c @@ -89,7 +89,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl |= RADEON_LVDS_PLL_EN; WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); - DRM_MDELAY(1); + mdelay(1); lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; @@ -102,7 +102,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); if (is_mac) lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; - DRM_MDELAY(panel_pwr_delay); + mdelay(panel_pwr_delay); WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); break; case DRM_MODE_DPMS_STANDBY: @@ -119,10 +119,10 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); } - DRM_MDELAY(panel_pwr_delay); + mdelay(panel_pwr_delay); WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); - DRM_MDELAY(panel_pwr_delay); + mdelay(panel_pwr_delay); break; } @@ -691,7 +691,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc WREG32(RADEON_DAC_MACRO_CNTL, tmp); - DRM_MDELAY(2); + mdelay(2); if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) found = connector_status_connected; @@ -1336,7 +1336,7 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder, (6 << RADEON_TV_DAC_DACADJ_SHIFT)); RREG32(RADEON_TV_DAC_CNTL); - DRM_MDELAY(4); + mdelay(4); WREG32(RADEON_TV_DAC_CNTL, RADEON_TV_DAC_NBLANK | @@ -1347,7 +1347,7 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder, (6 << RADEON_TV_DAC_DACADJ_SHIFT)); RREG32(RADEON_TV_DAC_CNTL); - DRM_MDELAY(6); + mdelay(6); tmp = RREG32(RADEON_TV_DAC_CNTL); if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { @@ -1414,7 +1414,7 @@ static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); - DRM_MDELAY(3); + mdelay(3); tmp = RREG32(RADEON_TV_DAC_CNTL); if (tmp & RADEON_TV_DAC_GDACDET) { found = true; @@ -1497,7 +1497,7 @@ static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, break; if (!drm_can_sleep()) - DRM_MDELAY(1); + mdelay(1); else drm_msleep(1, "extdac"); } @@ -1639,7 +1639,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; WREG32(RADEON_DAC_CNTL2, tmp); - DRM_MDELAY(10); + mdelay(10); if (ASIC_IS_R300(rdev)) { if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) diff --git a/sys/dev/pci/drm/radeon/radeon_test.c b/sys/dev/pci/drm/radeon/radeon_test.c index fbbad672c98..e8ea9f3bc70 100644 --- a/sys/dev/pci/drm/radeon/radeon_test.c +++ b/sys/dev/pci/drm/radeon/radeon_test.c @@ -287,7 +287,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, } radeon_ring_unlock_commit(rdev, ringA); - DRM_MDELAY(1000); + mdelay(1000); if (radeon_fence_signaled(fence1)) { DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n"); @@ -308,7 +308,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev, goto out_cleanup; } - DRM_MDELAY(1000); + mdelay(1000); if (radeon_fence_signaled(fence2)) { DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n"); @@ -386,7 +386,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, } radeon_ring_unlock_commit(rdev, ringB); - DRM_MDELAY(1000); + mdelay(1000); if (radeon_fence_signaled(fenceA)) { DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); @@ -406,7 +406,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, radeon_ring_unlock_commit(rdev, ringC); for (i = 0; i < 30; ++i) { - DRM_MDELAY(100); + mdelay(100); sigA = radeon_fence_signaled(fenceA); sigB = radeon_fence_signaled(fenceB); if (sigA || sigB) @@ -431,7 +431,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); radeon_ring_unlock_commit(rdev, ringC); - DRM_MDELAY(1000); + mdelay(1000); r = radeon_fence_wait(fenceA, false); if (r) { diff --git a/sys/dev/pci/drm/radeon/rs400.c b/sys/dev/pci/drm/radeon/rs400.c index 67a77917fd7..4a02080820e 100644 --- a/sys/dev/pci/drm/radeon/rs400.c +++ b/sys/dev/pci/drm/radeon/rs400.c @@ -65,7 +65,7 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev) tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) break; - DRM_UDELAY(1); + udelay(1); timeout--; } while (timeout > 0); WREG32_MC(RS480_GART_CACHE_CNTRL, 0); @@ -235,7 +235,7 @@ int rs400_mc_wait_for_idle(struct radeon_device *rdev) if (tmp & RADEON_MC_IDLE) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } diff --git a/sys/dev/pci/drm/radeon/rs600.c b/sys/dev/pci/drm/radeon/rs600.c index acf81a3df86..1c08c737036 100644 --- a/sys/dev/pci/drm/radeon/rs600.c +++ b/sys/dev/pci/drm/radeon/rs600.c @@ -141,7 +141,7 @@ u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) break; - DRM_UDELAY(1); + udelay(1); } DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); @@ -170,7 +170,7 @@ void rs600_pm_misc(struct radeon_device *rdev) tmp &= ~(voltage->gpio.mask); WREG32(voltage->gpio.reg, tmp); if (voltage->delay) - DRM_UDELAY(voltage->delay); + udelay(voltage->delay); } else { tmp = RREG32(voltage->gpio.reg); if (voltage->active_high) @@ -179,7 +179,7 @@ void rs600_pm_misc(struct radeon_device *rdev) tmp |= voltage->gpio.mask; WREG32(voltage->gpio.reg, tmp); if (voltage->delay) - DRM_UDELAY(voltage->delay); + udelay(voltage->delay); } } else if (voltage->type == VOLTAGE_VDDC) radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); @@ -411,30 +411,30 @@ int rs600_asic_reset(struct radeon_device *rdev) /* disable bus mastering */ pci_clear_master(rdev->pdev); #endif - DRM_MDELAY(1); + mdelay(1); /* reset GA+VAP */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | S_0000F0_SOFT_RESET_GA(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* reset CP */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* reset MC */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - DRM_MDELAY(500); + mdelay(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - DRM_MDELAY(1); + mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* restore PCI & busmastering */ @@ -697,7 +697,7 @@ void rs600_irq_disable(struct radeon_device *rdev) WREG32(R_000040_GEN_INT_CNTL, 0); WREG32(R_006540_DxMODE_INT_MASK, 0); /* Wait and acknowledge irq */ - DRM_MDELAY(1); + mdelay(1); rs600_irq_ack(rdev); } @@ -791,7 +791,7 @@ int rs600_mc_wait_for_idle(struct radeon_device *rdev) for (i = 0; i < rdev->usec_timeout; i++) { if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) return 0; - DRM_UDELAY(1); + udelay(1); } return -1; } diff --git a/sys/dev/pci/drm/radeon/rs690.c b/sys/dev/pci/drm/radeon/rs690.c index 8a4fdb59bab..73d3a8c3c9e 100644 --- a/sys/dev/pci/drm/radeon/rs690.c +++ b/sys/dev/pci/drm/radeon/rs690.c @@ -41,7 +41,7 @@ int rs690_mc_wait_for_idle(struct radeon_device *rdev) tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); if (G_000090_MC_SYSTEM_IDLE(tmp)) return 0; - DRM_UDELAY(1); + udelay(1); } return -1; } diff --git a/sys/dev/pci/drm/radeon/rv515.c b/sys/dev/pci/drm/radeon/rv515.c index 60dc81ccfde..b33bc928809 100644 --- a/sys/dev/pci/drm/radeon/rv515.c +++ b/sys/dev/pci/drm/radeon/rv515.c @@ -136,7 +136,7 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) if (tmp & MC_STATUS_IDLE) { return 0; } - DRM_UDELAY(1); + udelay(1); } return -1; } @@ -311,7 +311,7 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) for (j = 0; j < rdev->usec_timeout; j++) { if (radeon_get_vblank_counter(rdev, i) != frame_count) break; - DRM_UDELAY(1); + udelay(1); } /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ @@ -346,7 +346,7 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) } } /* wait for the MC to settle */ - DRM_UDELAY(100); + udelay(100); /* lock double buffered regs */ for (i = 0; i < rdev->num_crtc; i++) { @@ -414,7 +414,7 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) break; - DRM_UDELAY(1); + udelay(1); } } } @@ -444,13 +444,13 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) for (j = 0; j < rdev->usec_timeout; j++) { if (radeon_get_vblank_counter(rdev, i) != frame_count) break; - DRM_UDELAY(1); + udelay(1); } } } /* Unlock vga access */ WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); - DRM_MDELAY(1); + mdelay(1); WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); } diff --git a/sys/dev/pci/drm/radeon/rv770.c b/sys/dev/pci/drm/radeon/rv770.c index a8bf3550a01..bf1eb5c37c7 100644 --- a/sys/dev/pci/drm/radeon/rv770.c +++ b/sys/dev/pci/drm/radeon/rv770.c @@ -67,7 +67,7 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) break; - DRM_UDELAY(1); + udelay(1); } DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); @@ -334,7 +334,7 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev) /* Reset cp */ WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); RREG32(GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(GRBM_SOFT_RESET, 0); fw_data = (const __be32 *)rdev->pfp_fw; diff --git a/sys/dev/pci/drm/radeon/si.c b/sys/dev/pci/drm/radeon/si.c index 62625573c53..cb2e08c9b6e 100644 --- a/sys/dev/pci/drm/radeon/si.c +++ b/sys/dev/pci/drm/radeon/si.c @@ -262,12 +262,12 @@ static int si_mc_load_microcode(struct radeon_device *rdev) for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) break; - DRM_UDELAY(1); + udelay(1); } for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) break; - DRM_UDELAY(1); + udelay(1); } if (running) @@ -1724,7 +1724,7 @@ static void si_gpu_init(struct radeon_device *rdev) WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); - DRM_UDELAY(50); + udelay(50); } /* @@ -1844,7 +1844,7 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable) rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; } - DRM_UDELAY(50); + udelay(50); } static int si_cp_load_microcode(struct radeon_device *rdev) @@ -1986,7 +1986,7 @@ static int si_cp_resume(struct radeon_device *rdev) SOFT_RESET_SPI | SOFT_RESET_SX)); RREG32(GRBM_SOFT_RESET); - DRM_MDELAY(15); + mdelay(15); WREG32(GRBM_SOFT_RESET, 0); RREG32(GRBM_SOFT_RESET); @@ -2025,7 +2025,7 @@ static int si_cp_resume(struct radeon_device *rdev) WREG32(SCRATCH_UMSK, 0); } - DRM_MDELAY(1); + mdelay(1); WREG32(CP_RB0_CNTL, tmp); WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); @@ -2051,7 +2051,7 @@ static int si_cp_resume(struct radeon_device *rdev) WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); - DRM_MDELAY(1); + mdelay(1); WREG32(CP_RB1_CNTL, tmp); WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); @@ -2077,7 +2077,7 @@ static int si_cp_resume(struct radeon_device *rdev) WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); - DRM_MDELAY(1); + mdelay(1); WREG32(CP_RB2_CNTL, tmp); WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); @@ -2167,7 +2167,7 @@ static void si_gpu_soft_reset_gfx(struct radeon_device *rdev) dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); WREG32(GRBM_SOFT_RESET, grbm_reset); (void)RREG32(GRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(GRBM_SOFT_RESET, 0); (void)RREG32(GRBM_SOFT_RESET); @@ -2206,7 +2206,7 @@ static void si_gpu_soft_reset_dma(struct radeon_device *rdev) /* Reset dma */ WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); RREG32(SRBM_SOFT_RESET); - DRM_UDELAY(50); + udelay(50); WREG32(SRBM_SOFT_RESET, 0); dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", @@ -2245,7 +2245,7 @@ static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) si_gpu_soft_reset_dma(rdev); /* Wait a little for things to settle down */ - DRM_UDELAY(50); + udelay(50); evergreen_mc_resume(rdev, &save); return 0; @@ -3626,7 +3626,7 @@ static void si_irq_disable(struct radeon_device *rdev) { si_disable_interrupts(rdev); /* Wait and acknowledge irq */ - DRM_MDELAY(1); + mdelay(1); si_irq_ack(rdev); si_disable_interrupt_state(rdev); } |