diff options
| author | Patrick Wildt <patrick@cvs.openbsd.org> | 2021-02-26 12:28:47 +0000 |
|---|---|---|
| committer | Patrick Wildt <patrick@cvs.openbsd.org> | 2021-02-26 12:28:47 +0000 |
| commit | ae60823607096f8977ba96310ea3ab43298a3e27 (patch) | |
| tree | de3a333d8aadef0b9daa63279dac2ec7cebc25f8 /sys/dev/pci/if_bwfm_pci.h | |
| parent | 0114e347bd51980b866692e43d6ae7ced2abb8bc (diff) | |
Add support for BCM4378 as implemented on the Apple M1. This chip seems
to use a different set of PCIE2REG registers. Accessing the "old" ones
even leads to faults. There are two surprises though. One is that it
seems that the interrupt status register always returns 0, and the other
one is that we receive the interrupts way too early, but both can be
worked around for now.
Diffstat (limited to 'sys/dev/pci/if_bwfm_pci.h')
| -rw-r--r-- | sys/dev/pci/if_bwfm_pci.h | 42 |
1 files changed, 40 insertions, 2 deletions
diff --git a/sys/dev/pci/if_bwfm_pci.h b/sys/dev/pci/if_bwfm_pci.h index 0e42df6d910..d045ca89875 100644 --- a/sys/dev/pci/if_bwfm_pci.h +++ b/sys/dev/pci/if_bwfm_pci.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_bwfm_pci.h,v 1.5 2021/02/26 00:19:41 patrick Exp $ */ +/* $OpenBSD: if_bwfm_pci.h,v 1.6 2021/02/26 12:28:46 patrick Exp $ */ /* * Copyright (c) 2010-2016 Broadcom Corporation * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se> @@ -45,12 +45,50 @@ BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1) - #define BWFM_PCI_PCIE2REG_CONFIGADDR 0x120 #define BWFM_PCI_PCIE2REG_CONFIGDATA 0x124 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX_0 0x140 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX_1 0x144 +#define BWFM_PCI_64_PCIE2REG_INTMASK 0xC14 +#define BWFM_PCI_64_PCIE2REG_MAILBOXINT 0xC30 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK 0xC34 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 1 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 2 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 4 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 8 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x10 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x20 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x40 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x80 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB0 0x100 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB1 0x200 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB0 0x400 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB1 0x800 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB0 0x1000 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB1 0x2000 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB0 0x4000 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB1 0x8000 +#define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ + (BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB1 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB0 | \ + BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB1) +#define BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_0 0xA20 +#define BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_1 0xA24 + #define BWFM_PCI_CFGREG_STATUS_CMD 0x004 #define BWFM_PCI_CFGREG_PM_CSR 0x04C #define BWFM_PCI_CFGREG_MSI_CAP 0x058 |