diff options
| author | Brad Smith <brad@cvs.openbsd.org> | 2008-02-20 00:00:07 +0000 |
|---|---|---|
| committer | Brad Smith <brad@cvs.openbsd.org> | 2008-02-20 00:00:07 +0000 |
| commit | 0bab2cdc90d3a5ce8d2f3c2167e6ca1b7e70adff (patch) | |
| tree | abbbdfed77d27b8a2bfbf7d6520cc2401e526e78 /sys/dev/pci/if_em_hw.h | |
| parent | 126e71f88f9a7d718b9f8213bb6328c0ed6fb756 (diff) | |
Add support for the Intel ICH9 chipsets.
Initial diff from Henry Precheur based on a commit from matthias@dragonflybsd
which was derived from the FreeBSD driver. Additional Flash changes from
sephe@dragonflybsd which was derived from the FreeBSD driver. Typo fixes
in Henry's diff and a few other improvements from the FreeBSD driver from
brad@.
Tested on a variety of different em(4) adapters in addition to ICH8/9.
ok dlg@
Diffstat (limited to 'sys/dev/pci/if_em_hw.h')
| -rw-r--r-- | sys/dev/pci/if_em_hw.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/sys/dev/pci/if_em_hw.h b/sys/dev/pci/if_em_hw.h index 2cd7476fe80..396a62032d3 100644 --- a/sys/dev/pci/if_em_hw.h +++ b/sys/dev/pci/if_em_hw.h @@ -31,7 +31,7 @@ *******************************************************************************/ -/* $OpenBSD: if_em_hw.h,v 1.23 2008/02/04 00:30:01 brad Exp $ */ +/* $OpenBSD: if_em_hw.h,v 1.24 2008/02/20 00:00:06 brad Exp $ */ /* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */ /* if_em_hw.h @@ -69,6 +69,7 @@ typedef enum { em_82573, em_80003es2lan, em_ich8lan, + em_ich9lan, em_num_macs } em_mac_type; @@ -582,7 +583,7 @@ int32_t em_check_phy_reset_block(struct em_hw *hw); * E1000_RAR_ENTRIES - 1 multicast addresses. */ #define E1000_RAR_ENTRIES 15 -#define E1000_RAR_ENTRIES_ICH8LAN 6 +#define E1000_RAR_ENTRIES_ICH8LAN 7 #define MIN_NUMBER_OF_DESCRIPTORS 8 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 @@ -1071,7 +1072,7 @@ struct em_ffvt_entry { #define E1000_SWSM 0x05B50 /* SW Semaphore */ #define E1000_FWSM 0x05B54 /* FW Semaphore */ #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ -#define E1000_HICR 0x08F00 /* Host Inteface Control */ +#define E1000_HICR 0x08F00 /* Host Interface Control */ /* RSS registers */ #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ @@ -2416,6 +2417,7 @@ struct em_host_command_info { /* PBA constants */ #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ +#define E1000_PBA_10K 0x000A #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ #define E1000_PBA_22K 0x0016 @@ -3263,6 +3265,7 @@ struct em_host_command_info { #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ #define ICH_FLASH_SEG_SIZE_256 256 #define ICH_FLASH_SEG_SIZE_4K 4096 +#define ICH_FLASH_SEG_SIZE_8K 8192 #define ICH_FLASH_SEG_SIZE_64K 65536 #define ICH_CYCLE_READ 0x0 @@ -3292,6 +3295,7 @@ struct em_host_command_info { #define ICH_FLASH_SECTOR_SIZE 4096 #define ICH_GFPREG_BASE_MASK 0x1FFF #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF +#define ICH_FLASH_SECT_ADDR_SHIFT 12 /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ /* Offset 04h HSFSTS */ |