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authorChris Cappuccio <chris@cvs.openbsd.org>2000-02-01 18:01:43 +0000
committerChris Cappuccio <chris@cvs.openbsd.org>2000-02-01 18:01:43 +0000
commite68fb82f07f3d13d45357f91edb7ca2d5f067ba0 (patch)
treecbdd89e03bbfa209cce0f8b00a5b5c63b8a6549b /sys/dev/pci/if_lmcvar.h
parent00e2d83579a628087496d77321547374d28dd089 (diff)
general cleanup (remove LMC_IOMAPPED crud entirely)
add correct rcs tags sync w/lmc's lmc_media.c regarding watchdog support (So, the LEDs on the T1/T3 cards [the ones with built-in CSU/DSUs], and also the DS1 "SSI" card should now change according to various line conditions, as ths manual says they do)
Diffstat (limited to 'sys/dev/pci/if_lmcvar.h')
-rw-r--r--sys/dev/pci/if_lmcvar.h40
1 files changed, 7 insertions, 33 deletions
diff --git a/sys/dev/pci/if_lmcvar.h b/sys/dev/pci/if_lmcvar.h
index bd85a8e07ce..115b449ab7a 100644
--- a/sys/dev/pci/if_lmcvar.h
+++ b/sys/dev/pci/if_lmcvar.h
@@ -1,3 +1,4 @@
+/* $OpenBSD: if_lmcvar.h,v 1.3 2000/02/01 18:01:42 chris Exp $ */
/* $NetBSD: if_lmcvar.h,v 1.1 1999/03/25 03:32:43 explorer Exp $ */
/*-
@@ -62,22 +63,11 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#if !defined(_DEVAR_H)
-#define _DEVAR_H
-
#define LMC_MTU 1500
#define PPP_HEADER_LEN 4
#define BIG_PACKET
/*
- * Intel CPUs should use I/O mapped access. XXXMLG Is this true on NetBSD
- * too?
- */
-#if defined(__i386__)
-#define LMC_IOMAPPED
-#endif
-
-/*
* This turns on all sort of debugging stuff and make the
* driver much larger.
*/
@@ -141,12 +131,6 @@
bus_space_write_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
#endif /* __NetBSD__ */
-#ifdef LMC_IOMAPPED
-#define LMC_EISA_CSRSIZE 16
-#define LMC_EISA_CSROFFSET 0
-#define LMC_PCI_CSRSIZE 8
-#define LMC_PCI_CSROFFSET 0
-
#if !defined(__NetBSD__) && !defined(__OpenBSD__)
#define LMC_CSR_READ(sc, csr) (inl((sc)->lmc_csrs.csr))
#define LMC_CSR_WRITE(sc, csr, val) outl((sc)->lmc_csrs.csr, val)
@@ -155,8 +139,6 @@
#define LMC_CSR_WRITEBYTE(sc, csr, val) outb((sc)->lmc_csrs.csr, val)
#endif /* __NetBSD__ */
-#else /* LMC_IOMAPPED */
-
#define LMC_PCI_CSRSIZE 8
#define LMC_PCI_CSROFFSET 0
@@ -170,12 +152,9 @@
#define LMC_CSR_WRITE(sc, csr, val) ((void)(*(sc)->lmc_csrs.csr = (val)))
#endif /* __NetBSD__ */
-#endif /* LMC_IOMAPPED */
-
/*
* This structure contains "pointers" for the registers on
- * the various 21x4x chips. CSR0 through CSR8 are common
- * to all chips. After that, it gets messy...
+ * the various 21x4x chips.
*/
typedef struct {
lmc_csrptr_t csr_busmode; /* CSR0 */
@@ -187,7 +166,7 @@ typedef struct {
lmc_csrptr_t csr_command; /* CSR6 */
lmc_csrptr_t csr_intr; /* CSR7 */
lmc_csrptr_t csr_missed_frames; /* CSR8 */
- lmc_csrptr_t csr_9; /* CSR9 */
+ lmc_csrptr_t csr_9; /* CSR9 */
lmc_csrptr_t csr_10; /* CSR10 */
lmc_csrptr_t csr_11; /* CSR11 */
lmc_csrptr_t csr_12; /* CSR12 */
@@ -258,11 +237,8 @@ struct lmc_ringinfo {
#define LMC_RX_BUFLEN ((MCLBYTES < 2048 ? MCLBYTES : 2048) - 16)
-/*
- * The various controllers support. Technically the DE425 is just
- * a 21040 on EISA. But since it remarkably difference from normal
- * 21040s, we give it its own chip id.
- */
+#define LMC_LINK_UP 1
+#define LMC_LINK_DOWN 0
typedef enum {
LMC_21140, LMC_21140A,
@@ -373,6 +349,7 @@ struct lmc___softc {
#endif
u_int32_t lmc_crcSize;
+ char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
char lmc_timing; /* for HSSI and SSI */
u_int16_t t1_alarm1_status;
u_int16_t t1_alarm2_status;
@@ -468,8 +445,7 @@ static const char * const lmc_status_bits[] = {
};
/*
- * This driver supports a maximum of 32 tulip boards.
- * This should be enough for the forseeable future.
+ * This driver supports a maximum of 32 devices.
*/
#define LMC_MAX_DEVICES 32
@@ -610,5 +586,3 @@ extern struct cfdriver lmc_cd;
&& ((u_int16_t *)a1)[2] == 0xFFFFU)
typedef int lmc_spl_t;
-
-#endif /* !defined(_DEVAR_H) */