diff options
| author | Michael Shalayeff <mickey@cvs.openbsd.org> | 2004-07-14 21:54:20 +0000 |
|---|---|---|
| committer | Michael Shalayeff <mickey@cvs.openbsd.org> | 2004-07-14 21:54:20 +0000 |
| commit | 83ed57ef80de637661b9f6f753f95ef33f816c3d (patch) | |
| tree | 992feb14aee7fc00145b11fe574b3299f61f22e8 /sys/dev/pci/pccbbreg.h | |
| parent | d0bb3d5a0d737debd5c14848041be109d5324c60 (diff) | |
tweaks for ti12xx bridges; from freebsd via rees@
Diffstat (limited to 'sys/dev/pci/pccbbreg.h')
| -rw-r--r-- | sys/dev/pci/pccbbreg.h | 31 |
1 files changed, 29 insertions, 2 deletions
diff --git a/sys/dev/pci/pccbbreg.h b/sys/dev/pci/pccbbreg.h index 130b755563c..238f07bcaaa 100644 --- a/sys/dev/pci/pccbbreg.h +++ b/sys/dev/pci/pccbbreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pccbbreg.h,v 1.3 2003/06/25 21:53:45 mickey Exp $ */ +/* $OpenBSD: pccbbreg.h,v 1.4 2004/07/14 21:54:19 mickey Exp $ */ /* $NetBSD: pccbbreg.h,v 1.5 2000/06/07 09:02:47 haya Exp $ */ /* * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. @@ -40,6 +40,7 @@ #define PCI_BUSNUM 0x18 /* latency timer, Subordinate bus number */ #define PCI_BCR_INTR 0x3C /* intr line, intr pin, bridge control regs */ #define PCI_LEGACY 0x44 /* legacy IO register address (32 bits) */ +#define PCI_SYSCTRL 0x80 /* System control */ #define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */ #define PCI_CLASS_INTERFACE_MASK 0xffffff00 @@ -82,6 +83,21 @@ #define CB_BCR_PREFETCH_MEMWIN1 0x02000000 #define CB_BCR_WRITE_POST_ENABLE 0x04000000 +/* TI [14][245]xx */ +#define PCI12XX_MMCTRL 0x84 + +/* TI 12xx/14xx/15xx (except 1250, 1251, 1251B/1450) */ +#define PCI12XX_MFUNC 0x8c +#define PCI12XX_MFUNC_PIN0 0x0000000f +#define PCI12XX_MFUNC_PIN0_INTA 0x02 +#define PCI12XX_MFUNC_PIN1 0x000000f0 +#define PCI12XX_MFUNC_PIN1_INTB 0x20 +#define PCI12XX_MFUNC_PIN2 0x00000f00 +#define PCI12XX_MFUNC_PIN3 0x0000f000 +#define PCI12XX_MFUNC_PIN4 0x000f0000 +#define PCI12XX_MFUNC_PIN5 0x00f00000 +#define PCI12XX_MFUNC_PIN6 0x0f000000 + /* PCI_CBCTRL bits for TI PCI113X */ #define PCI113X_CBCTRL_INT_SERIAL 0x040000 #define PCI113X_CBCTRL_INT_ISA 0x020000 @@ -96,7 +112,18 @@ #define PCI113X_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */ /* PCI_CBCTRL bits for TI PCI12XX */ -#define PCI12XX_CBCTRL_INT_SERIAL 0x040000 +#define PCI12XX_SYSCTRL_INTRTIE 0x20000000u +#define PCI12XX_SYSCTRL_VCCPROT 0x200000 +#define PCI12XX_SYSCTRL_PWRSAVE 0x000040 +#define PCI12XX_SYSCTRL_SUBSYSRW 0x000020 +#define PCI12XX_SYSCTRL_CB_DPAR 0x000010 +#define PCI12XX_SYSCTRL_CDMA_EN 0x000008 +#define PCI12XX_SYSCTRL_KEEPCLK 0x000002 +#define PCI12XX_SYSCTRL_RIMUX 0x000001 +#define PCI12XX_CBCTRL_CSC 0x20000000u +#define PCI12XX_CBCTRL_ASYNC_CSC 0x01000000u +#define PCI12XX_CBCTRL_INT_SERIAL 0x060000 +#define PCI12XX_CBCTRL_INT_PCI_SERIAL 0x040000 #define PCI12XX_CBCTRL_INT_ISA 0x020000 #define PCI12XX_CBCTRL_INT_PCI 0x000000 #define PCI12XX_CBCTRL_INT_MASK 0x060000 |